JPH1126804A - Photo coupler type semiconductor relay - Google Patents

Photo coupler type semiconductor relay

Info

Publication number
JPH1126804A
JPH1126804A JP17430797A JP17430797A JPH1126804A JP H1126804 A JPH1126804 A JP H1126804A JP 17430797 A JP17430797 A JP 17430797A JP 17430797 A JP17430797 A JP 17430797A JP H1126804 A JPH1126804 A JP H1126804A
Authority
JP
Japan
Prior art keywords
light
relay
ldmosfet
electrically connected
ldmosfets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17430797A
Other languages
Japanese (ja)
Other versions
JP3468033B2 (en
Inventor
Masamichi Takano
仁路 高野
Masahiko Suzumura
正彦 鈴村
Yuji Suzuki
裕二 鈴木
Yoshiki Hayazaki
嘉城 早崎
Yoshifumi Shirai
良史 白井
Takashi Kishida
貴司 岸田
Takeshi Yoshida
岳司 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP17430797A priority Critical patent/JP3468033B2/en
Publication of JPH1126804A publication Critical patent/JPH1126804A/en
Application granted granted Critical
Publication of JP3468033B2 publication Critical patent/JP3468033B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PROBLEM TO BE SOLVED: To provide a photo coupler type semiconductor relay which never increases the output terminal capacitance at the time of the relay off. SOLUTION: A relay comprises a solar cell 1 to be a photo detector and LDMOSFETs 2, 3 each having an ISO structure on a floating frame electrically independent of the external potential in a resin package 7. The anodes 1a, 1b of the cell 1 are directly electrically connected to the gate electrodes 2a, 3a of the LDMOSFETs 2, 3 through bonding wires 5, without running through the frame 4; the cathodes 1c, 1d of the cell 1 are directly electrically connected to the source electrodes 2b, 3b of the LDMOSFETs 2, 3 through bonding wires 5, without running through the frame 4; and the drain electrodes 2c, 3c of the LDMOSFETs 2, 3 are electrically connected to output terminal frames 6a, 6b through bonding wires 5.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、発光素子と受光素
子とを光結合し、受光素子の出力によってＭＯＳＦＥＴ
にスイッチング動作を行わせる光結合型半導体リレ−に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device and a light receiving device which are optically coupled to each other.
The present invention relates to an optically coupled semiconductor relay that causes a switching operation to be performed.

【０００２】[0002]

【従来の技術】図３に示すように、従来の縦型ＭＯＳＦ
ＥＴを出力用ＭＯＳＦＥＴとして用いたフォトモスリレ
−は、受光素子である太陽電池１がＧＮＤ端子フレ−ム
８上に配設され、このＧＮＤ端子フレ−ム８の両側に並
設された出力端子フレ−ム６ａ，６ｂ上に縦型ＭＯＳＦ
ＥＴ９，１０が配設されている。2. Description of the Related Art As shown in FIG.
A photo-MOS relay using an ET as an output MOSFET is such that a solar cell 1 as a light receiving element is disposed on a GND terminal frame 8, and output terminal frames arranged side by side on both sides of the GND terminal frame 8. Vertical MOSF on the memory 6a, 6b
ETs 9 and 10 are provided.

【０００３】また、図４に示すように、ＧＮＤ端子フレ
−ム８に対向して配置された入力端子フレ−ム１２上に
は発光素子である発光ダイオ−ド１１が配設され、太陽
電池１のアノ−ド１ａ，１ｂと縦型ＭＯＳＦＥＴ９，１
０のゲ−ト電極９ａ，１０ａとは、それぞれボンディン
グワイヤ５により電気的に接続され、太陽電池１のカソ
−ド１ｃ及び縦型ＭＯＳＦＥＴ９，１０のソ−ス電極９
ｂ，１０ｂは、ボンディングワイヤ５によりＧＮＤ端子
フレ−ム８に電気的に接続されている。Further, as shown in FIG. 4, a light emitting diode 11 as a light emitting element is provided on an input terminal frame 12 arranged opposite to the GND terminal frame 8, and a solar cell is provided. 1 and the vertical MOSFETs 9, 1
The gate electrodes 9a and 10a of the solar cell 1 are electrically connected by bonding wires 5, respectively, and the cathode 1c of the solar cell 1 and the source electrodes 9 of the vertical MOSFETs 9 and 10 are connected.
b and 10b are electrically connected to the GND terminal frame 8 by bonding wires 5.

【０００４】そして、全体を不透明な樹脂パッケ−ジ７
でモ−ルドして１パッケ−ジ化し、太陽電池１と発光ダ
イオ−ド１１との間を透明なシリコン樹脂１３からなる
導光路により光結合し、発光ダイオ−ド１１からの光を
受光素子である太陽電池１で受光できるようになってい
る。[0004] The entire resin package 7 is opaque.
To form a package, and optically couples the solar cell 1 and the light emitting diode 11 by a light guide path made of a transparent silicon resin 13, and receives light from the light emitting diode 11 as a light receiving element. The solar cell 1 can receive light.

【０００５】このように構成されたフォトモスリレ−
は、発光ダイオ−ド１１を外部駆動信号で発光させ、そ
の発光ダイオ−ド１１からの光を受光した太陽電池１は
電圧を発生し、この電圧が一定レベルに達すると出力用
の縦型ＭＯＳＦＥＴ９，１０がスイッチングし、フォト
モスリレ−がオン、またはオフする。[0005] The photo mosley relay constructed as described above.
The light emitting diode 11 emits light by an external drive signal, and the solar cell 1 receiving the light from the light emitting diode 11 generates a voltage. When the voltage reaches a certain level, the output vertical MOSFET 9 is turned on. , 10 are switched, and the photo MOS relay is turned on or off.

【０００６】また、上述のようなフォトモスリレ−にお
いては、出力端子フレ−ム６ａ，６ｂの間に負荷をかけ
る場合と、一方の出力端子フレ−ム６ａ，６ｂとＧＮＤ
端子フレ−ム８との間に負荷をかける場合とで、交流電
流用途と直流電流用途とに使い分けることが可能であ
る。In the above-mentioned photo mosley relay, a load is applied between the output terminal frames 6a and 6b, and one of the output terminal frames 6a and 6b is connected to GND.
When a load is applied between the terminal frame 8 and the terminal frame 8, it can be selectively used for AC current application and DC current application.

【０００７】ところで、このようなフォトモスリレ−に
おいて、リレ−の出力端子間容量は、リレ−オフ時の絶
縁特性に関わる重要な特性である。出力端子間容量は、
出力用ＭＯＳＦＥＴの特性によって決まり、出力端子間
容量が小さいほど、リレ−の高周波絶縁性は大きくな
る。Incidentally, in such a photomos relay, the capacitance between the output terminals of the relay is an important characteristic related to the insulation characteristics when the relay is off. The capacitance between output terminals is
Determined by the characteristics of the output MOSFET, the smaller the capacitance between the output terminals, the greater the high-frequency insulation of the relay.

【０００８】近年、リレ−オフ時の出力容量低減化を目
的として、出力用ＭＯＳＦＥＴとして縦型ＭＯＳＦＥＴ
９，１０の代わりに、ＳＯＩ（Silicon on Insulato
r）構造を有する横型２重拡散ＭＯＳ電解効果トランジ
スタ、いわゆるＬＤＭＯＳＦＥＴ（Lateral Double D
iffused MOSFET）が用いられている。In recent years, a vertical MOSFET has been used as an output MOSFET for the purpose of reducing the output capacitance at the time of relay-off.
Instead of 9 and 10, SOI (Silicon on Insulato)
r) Lateral double diffusion MOS field effect transistor having a structure, so-called LDMOSFET (Lateral Double D)
iffused MOSFET).

【０００９】これは、ＭＯＳＦＥＴの出力容量は、ドレ
イン・ソ−ス関容量Ｃds、ゲ−ト・ドレイン間容量Ｃgd
の和で表され、ＳＯＩ構造を有するＬＤＭＯＳＦＥＴは
縦型ＭＯＳＦＥＴに比べ、ドレイン・ソ−ス間容量Ｃds
を大幅に小さくできるからである。This is because the output capacitance of the MOSFET is a drain-source capacitance Cds, a gate-drain capacitance Cgd.
The LDMOSFET having the SOI structure is compared with the vertical MOSFET in that the drain-source capacitance Cds
Is significantly reduced.

【００１０】図５に示すように、ＳＯＩ構造を有するＬ
ＤＭＯＳＦＥＴ２，３を出力用ＭＯＳＦＥＴとして用い
たフォトモスリレ−は、出力用ＭＯＳＦＥＴとして縦型
ＭＯＳＦＥＴ９，１０を用いた場合と同様、受光素子で
ある太陽電池１がＧＮＤ端子フレ−ム８上に配設され、
このＧＮＤ端子フレ−ム８の両側に並設された出力端子
フレ−ム６ａ，６ｂ上にＬＤＭＯＳＦＥＴ２，３が配設
されている。そして、太陽電池１のアノ−ド１ａ，１ｂ
とＬＤＭＯＳＦＥＴ２，３のゲ−ト電極２ａ，３ａと
は、それぞれボンディングワイヤ５により電気的に接続
され、太陽電池１のカソ−ド１ｃ及びＬＤＭＯＳＦＥＴ
２，３のソ−ス電極２ｂ，３ｂは、ボンディングワイヤ
５によりＧＮＤ端子フレ−ム８に電気的に接続され、Ｌ
ＤＭＯＳＦＥＴ２，３のドレイン電極２ｃ，３ｃは出力
端子フレ−ム６ａ，６ｂにボンディングワイヤ５により
電気的に接続されている。As shown in FIG. 5, L having an SOI structure
In a photo-MOS relay using DMOSFETs 2 and 3 as output MOSFETs, a solar cell 1 as a light receiving element is disposed on a GND terminal frame 8 in the same manner as when vertical MOSFETs 9 and 10 are used as output MOSFETs.
LDMOSFETs 2 and 3 are arranged on output terminal frames 6a and 6b arranged on both sides of the GND terminal frame 8, respectively. Then, the anodes 1a and 1b of the solar cell 1
And the gate electrodes 2a and 3a of the LDMOSFETs 2 and 3 are electrically connected by bonding wires 5, respectively.
A few source electrodes 2b, 3b are electrically connected to a GND terminal frame 8 by bonding wires 5,
The drain electrodes 2c and 3c of the DMOSFETs 2 and 3 are electrically connected to output terminal frames 6a and 6b by bonding wires 5.

【００１１】[0011]

【発明が解決しようとする課題】ところが、ＳＯＩ構造
を有するＬＤＭＯＳＦＥＴ２，３を出力用ＭＯＳＦＥＴ
として用いた場合においては、出力用ＭＯＳＦＥＴが出
力端子フレ−ム６ａ，６ｂ上に配設されていると、リレ
−オフ時の出力端子間容量の増加を引き起こしてしまう
という問題が発生する。However, the LDMOSFETs 2 and 3 having the SOI structure are replaced with output MOSFETs.
When the output MOSFET is provided on the output terminal frames 6a and 6b, there arises a problem that the capacitance between the output terminals at the time of relay-off is increased.

【００１２】つまり、ＬＤＭＯＳＦＥＴ２，３におい
て、リレ−オフ時の出力端子間容量は、通常、ドレイン
・ソ−ス間容量Ｃdsとゲ−ト・ドレイン間容量Ｃgdの和
であるが、図５に示すような実装状態において出力端子
フレ−ム６ａ，６ｂの電位が上がった場合には、図６に
示すように、ＬＤＭＯＳＦＥＴ２，３の支持基板１４ａ
がドレインの電位まで上昇するので、埋込酸化膜１４ｂ
を介してゲ−ト・支持基板間容量Ｃgsubとソ−ス・支持
基板間容量Ｃssubが発生する。That is, in the LDMOSFETs 2 and 3, the capacitance between the output terminals when the relay is turned off is usually the sum of the capacitance Cds between the drain and the source and the capacitance Cgd between the gate and the drain, as shown in FIG. When the potential of the output terminal frames 6a, 6b rises in such a mounting state, as shown in FIG.
Rises to the potential of the drain, the buried oxide film 14b
A capacitance Cgsub between the gate and the supporting substrate and a capacitance Cssub between the source and the supporting substrate are generated through the gate.

【００１３】その結果、図７に示すように、通常のドレ
イン・ソ−ス間容量Ｃds，ゲ−ト・ドレイン間容量Ｃgd
に加え、ゲ−ト・支持基板間容量Ｃgsub，ソ−ス・支持
基板間容量Ｃssubが並列に重畳されるため、出力端子間
容量の増加を引き起こしてしまうことになる。As a result, as shown in FIG. 7, a normal drain-source capacitance Cds and a gate-drain capacitance Cgd are obtained.
In addition, since the capacitance Cgsub between the gate and the supporting substrate and the capacitance Cssub between the source and the supporting substrate are superposed in parallel, the capacitance between the output terminals is increased.

【００１４】本発明は、上記の点に鑑みて成されたもの
であり、その目的とするところは、リレ−オフ時の出力
端子間容量の増加を引き起こすことのない光結合型半導
体リレ−を提供することにある。The present invention has been made in view of the above points, and an object of the present invention is to provide an optically coupled semiconductor relay which does not cause an increase in capacitance between output terminals when the relay is turned off. To provide.

【００１５】[0015]

【課題を解決するための手段】請求項１記載の発明は、
入力側の信号に応答して発光する発光素子と、該発光素
子からの光信号を受けて光起電力を発生する受光素子
と、該受光素子の光起電力に呼応してオン／オフする出
力開閉素子とから成る光結合型半導体リレ−において、
前記出力開閉素子としてＳＯＩ構造を有するＬＤＭＯＳ
ＦＥＴを用い、前記受光素子と前記ＬＤＭＯＳＦＥＴの
内、少なくとも前記ＬＤＭＯＳＦＥＴが電気的に浮遊状
態で外部電位に依存しないフロ−ティングフレ−ム上に
配設され、前記受光素子のアノ−ドと前記ＬＤＭＯＳＦ
ＥＴのゲ−ト電極とが電気的に接続され、前記受光素子
のカソ−ドと前記ＬＤＭＯＳＦＥＴのソ−ス電極とが電
気的に接続され、前記ＬＤＭＯＳＦＥＴのドレイン電極
が出力端子フレ−ムに電気的に接続されて成ることを特
徴とするものである。According to the first aspect of the present invention,
A light-emitting element that emits light in response to a signal on the input side, a light-receiving element that generates a photovoltaic power by receiving an optical signal from the light-emitting element, and an output that is turned on / off in response to the photovoltaic power of the light-receiving element In an optical coupling type semiconductor relay comprising a switching element,
LDMOS having SOI structure as output switching element
At least the LDMOSFET of the light receiving element and the LDMOSFET is disposed in an electrically floating state on a floating frame that does not depend on an external potential, and an anode of the light receiving element and the LDMOSF are used.
The gate electrode of the ET is electrically connected, the cathode of the light receiving element is electrically connected to the source electrode of the LDMOSFET, and the drain electrode of the LDMOSFET is electrically connected to the output terminal frame. It is characterized by being connected to each other.

【００１６】[0016]

【発明の実施の形態】以下、本発明の一実施形態につい
て図面に基づき説明する。図１は、本発明の一実施形態
に係るＳＯＩ構造を有するＬＤＭＯＳＦＥＴ２，３を出
力用ＭＯＳＦＥＴとして用いたフォトモスリレ−の実装
状態を示す略平面図である。本実施形態に係るフォトモ
スリレ−は、樹脂パッケ−ジ７内に収納され、電気的に
外部電位に依存しない浮遊状態のフロ−ティングフレ−
ム４上に、受光素子である太陽電池１とＳＯＩ構造を有
するＬＤＭＯＳＦＥＴ２，３が配設されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic plan view showing a mounted state of a photo MOSFET using LDMOSFETs 2 and 3 having an SOI structure as output MOSFETs according to an embodiment of the present invention. The photomoss relay according to the present embodiment is housed in a resin package 7 and is a floating floating frame that does not depend on an external electric potential electrically.
A solar cell 1 as a light receiving element and LDMOSFETs 2 and 3 having an SOI structure are disposed on a system 4.

【００１７】また、太陽電池１のアノ−ド１ａ，１ｂと
ＬＤＭＯＳＦＥＴ２，３のゲ−ト電極２ａ，３ａとがフ
ロ−ティングフレ−ム４を介することなく、それぞれ直
接にボンディングワイヤ５により電気的に接続され、太
陽電池１のカソ−ド１ｃ，１ｄとＬＤＭＯＳＦＥＴ２，
３のソ−ス電極２ｂ，３ｂとがフロ−ティングフレ−ム
４を介することなく、それぞれ直接にボンディングワイ
ヤ５により電気的に接続され、ＬＤＭＯＳＦＥＴ２，３
のドレイン電極２ｃ，３ｃは出力端子フレ−ム６ａ，６
ｂにそれぞれボンディングワイヤ５により電気的に接続
されている。Also, the anodes 1a and 1b of the solar cell 1 and the gate electrodes 2a and 3a of the LDMOSFETs 2 and 3 are electrically connected directly by bonding wires 5 without passing through the floating frame 4, respectively. Are connected to the cathodes 1c, 1d of the solar cell 1 and the LDMOSFETs 2,
3 are directly connected to the source electrodes 2b and 3b by the bonding wires 5 without passing through the floating frame 4, respectively.
Are connected to the output terminal frames 6a, 6c.
b are electrically connected to each other by bonding wires 5.

【００１８】従って、本実施形態においては、ＬＤＭＯ
ＳＦＥＴ２，３のソ−ス電極２ｂ，３ｂと太陽電池１の
カソ−ド１ｃ，１ｄとがフロ−ティングフレ−ム４を介
さずに直接に接続されているので、フロ−ティングフレ
−ム４は、外部電位にもＬＤＭＯＳＦＥＴ２，３のソ−
ス電極２ｂ，３ｂの電位にも依存しない。このため、Ｌ
ＤＭＯＳＦＥＴ２，３の支持基板に起因する寄生容量成
分が発生せず、出力端子間容量は低減化される。Therefore, in this embodiment, the LDMO
Since the source electrodes 2b and 3b of the SFETs 2 and 3 and the cathodes 1c and 1d of the solar cell 1 are directly connected without passing through the floating frame 4, the floating frame 4 Is the source of the LDMOSFETs 2 and 3
It does not depend on the potentials of the electrodes 2b and 3b. Therefore, L
No parasitic capacitance component due to the support substrates of the DMOSFETs 2 and 3 is generated, and the capacitance between output terminals is reduced.

【００１９】なお、本実施形態においては、ＬＤＭＯＳ
ＦＥＴ２，３として図６に示すようなｎ型ＭＯＳＦＥＴ
を用いたが、これに限定される必要はなく、ｐ型ＭＯＳ
ＦＥＴを用いても良い。In this embodiment, the LDMOS
N-type MOSFET as shown in FIG.
However, the present invention is not limited to this.
An FET may be used.

【００２０】また、本実施形態においては、出力開閉素
子としてＳＯＩ構造を有するＬＤＭＯＳＦＥＴ２，３を
用いたが、これに限定される必要はなく、ＳＯＩ構造を
有するＪＦＥＴ，ＩＧＢＴ，ＵＭＯＳＦＥＴ，バイポ−
ラトランジスタでも良く、また、エピ基板上に形成され
たＬＤＭＯＳＦＥＴ，ＪＦＥＴ，ＩＧＢＴ，ＵＭＯＳＦ
ＥＴでも良く、また、バルク基板上に形成されたＬＤＭ
ＯＳＦＥＴ，ＪＦＥＴ，ＩＧＢＴ，ＵＭＯＳＦＥＴでも
良い。Further, in the present embodiment, the LDMOSFETs 2 and 3 having the SOI structure are used as the output switching elements. However, the present invention is not limited to this.
Transistor, or an LDMOSFET, JFET, IGBT, UMOSF formed on an epi-substrate.
ET may be used, and LDM formed on bulk substrate
OSFET, JFET, IGBT, UMOSFET may be used.

【００２１】また、本実施形態においては、太陽電池１
及びＬＤＭＯＳＦＥＴ２，３を同一のフロ−ティングフ
レ−ム４上に配設したが、これに限定される必要はな
く、図２に示すように、異なるフロ−ティングフレ−ム
４ａ〜４ｃ上にそれぞれ配設するようにしてもよい。In the present embodiment, the solar cell 1
And the LDMOSFETs 2 and 3 are arranged on the same floating frame 4. However, the present invention is not limited to this, and as shown in FIG. It may be arranged.

【００２２】更に、図２に示すフォトモスリレ−におい
て、太陽電池１が配設されたフロ−ティングフレ−ム４
ｂをＧＮＤ端子に接地するようにしても良い。Further, in the photo mosley relay shown in FIG. 2, a floating frame 4 provided with the solar cell 1 is provided.
b may be grounded to the GND terminal.

【００２３】[0023]

【発明の効果】請求項１記載の発明は、入力側の信号に
応答して発光する発光素子と、発光素子からの光信号を
受けて光起電力を発生する受光素子と、受光素子の光起
電力に呼応してオン／オフする出力開閉素子とから成る
光結合型半導体リレ−において、出力開閉素子としてＳ
ＯＩ構造を有するＬＤＭＯＳＦＥＴを用い、受光素子と
ＬＤＭＯＳＦＥＴの内、少なくともＬＤＭＯＳＦＥＴが
電気的に浮遊状態で外部電位に依存しないフロ−ティン
グフレ−ム上に配設され、受光素子のアノ−ドとＬＤＭ
ＯＳＦＥＴのゲ−ト電極とが電気的に接続され、受光素
子のカソ−ドとＬＤＭＯＳＦＥＴのソ−ス電極とが電気
的に接続され、ＬＤＭＯＳＦＥＴのドレイン電極が出力
端子フレ−ムに電気的に接続されて成るので、ＬＤＭＯ
ＳＦＥＴの支持基板に起因する寄生容量成分が発生せ
ず、リレ−オフ時の出力端子間容量の増加を引き起こす
ことのない光結合型半導体リレ−を提供することができ
た。According to the first aspect of the present invention, there is provided a light emitting element which emits light in response to a signal on the input side, a light receiving element which generates a photoelectromotive force by receiving an optical signal from the light emitting element, and a light receiving element for receiving light. In an optically coupled semiconductor relay comprising an output switching element which is turned on / off in response to an electromotive force, S
Using an LDMOSFET having an OI structure, at least the LDMOSFET among the light-receiving element and the LDMOSFET is disposed in an electrically floating state on a floating frame that does not depend on an external potential.
The gate electrode of the OSFET is electrically connected, the cathode of the light receiving element and the source electrode of the LDMOSFET are electrically connected, and the drain electrode of the LDMOSFET is electrically connected to the output terminal frame. LDMO
It is possible to provide an optically coupled semiconductor relay that does not generate a parasitic capacitance component due to the supporting substrate of the SFET and does not cause an increase in output terminal capacitance at the time of relay-off.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施形態に係るＳＯＩ構造を有する
ＬＤＭＯＳＦＥＴを出力用ＭＯＳＦＥＴとして用いたフ
ォトモスリレ−の実装状態を示す略平面図である。FIG. 1 is a schematic plan view showing a mounted state of a photo MOSFET using an LDMOSFET having an SOI structure according to an embodiment of the present invention as an output MOSFET.

【図２】本発明の他の実施形態に係るＳＯＩ構造を有す
るＬＤＭＯＳＦＥＴを出力用ＭＯＳＦＥＴとして用いた
フォトモスリレ−の実装状態を示す略平面図である。FIG. 2 is a schematic plan view showing a mounted state of a photo MOSFET using an LDMOSFET having an SOI structure as an output MOSFET according to another embodiment of the present invention.

【図３】従来例に係る縦型ＭＯＳＦＥＴを出力用ＭＯＳ
ＦＥＴとして用いたフォトモスリレ−の実装状態を示す
略平面図である。FIG. 3 shows a conventional vertical MOSFET connected to an output MOS.
FIG. 5 is a schematic plan view showing a mounted state of a photomoss relay used as an FET.

【図４】従来例に係るフォトモスリレ−の概略構成図で
ある。FIG. 4 is a schematic configuration diagram of a photo mosley relay according to a conventional example.

【図５】従来例に係るＳＯＩ構造を有するＬＤＭＯＳＦ
ＥＴを出力用ＭＯＳＦＥＴとして用いたフォトモスリレ
−の実装状態を示す略平面図である。FIG. 5 shows a conventional LDMOSF having an SOI structure.
FIG. 11 is a schematic plan view showing a mounting state of a photo-mosley relay using ET as an output MOSFET.

【図６】従来例に係るフォトモスリレ−のＬＤＭＯＳＦ
ＥＴの略断面図である。FIG. 6 is a photoMOS relay LDMOSF according to a conventional example.
It is a schematic sectional drawing of ET.

【図７】従来例に係るフォトモスリレ−のＬＤＭＯＳＦ
ＥＴの出力端子間容量の等価回路図である。FIG. 7 shows an LDMOSF of a photo mosley relay according to a conventional example.
It is an equivalent circuit diagram of the capacitance between output terminals of ET.

【符号の説明】[Explanation of symbols]

１ 太陽電池 １ａ，１ｂ アノ−ド １ｃ，１ｄ カソ−ド ２，３ ＬＤＭＯＳＦＥＴ ２ａ，３ａ ゲ−ト電極 ２ｂ，３ｂ ソ−ス電極 ２ｃ，３ｃ ドレイン電極 ４，４ａ〜４ｃ フロ−ティングフレ−ム ５ ボンディングワイヤ ６ａ，６ｂ 出力端子フレ−ム ７ 樹脂パッケ−ジ ８ ＧＮＤ端子フレ−ム ９，１０ 縦型ＭＯＳＦＥＴ ９ａ，１０ａ ゲ−ト電極 ９ｂ，１０ｂ ソ−ス電極 １１ 発光ダイオ−ド １２ 入力端子フレ−ム １３ シリコン樹脂 １４ａ 支持基板 １４ｂ 埋込酸化膜 １４ｃ ＳＯＩ層 １５ ｐ型ウェル領域 １６ ｎ＋型ドレイン領域 １７ ｎ＋型ソ−ス領域 DESCRIPTION OF SYMBOLS 1 Solar cell 1a, 1b Anode 1c, 1d Cathode 2, 3 LDMOSFET 2a, 3a Gate electrode 2b, 3b Source electrode 2c, 3c Drain electrode 4, 4a-4c Floating frame 5 Bonding wire 6a, 6b Output terminal frame 7 Resin package 8 GND terminal frame 9, 10 Vertical MOSFET 9a, 10a Gate electrode 9b, 10b Source electrode 11 Light emitting diode 12 Input terminal frame − Memory 13 silicon resin 14 a support substrate 14 b buried oxide film 14 c SOI layer 15 p-type well region 16 n + -type drain region 17 n + -type source region

フロントページの続き (72)発明者 早崎 嘉城 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 白井 良史 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 岸田 貴司 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 吉田 岳司 大阪府門真市大字門真1048番地松下電工株 式会社内Continued on the front page (72) Inventor Kashiro Hayasaki 1048 Kazumasa Kadoma, Osaka Prefecture Inside Matsushita Electric Works, Ltd. Inventor Takashi Kishida 1048 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works, Ltd. (72) Inventor Takeshi Yoshida 1048 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 入力側の信号に応答して発光する発光素
子と、該発光素子からの光信号を受けて光起電力を発生
する受光素子と、該受光素子の光起電力に呼応してオン
／オフする出力開閉素子とから成る光結合型半導体リレ
−において、前記出力開閉素子としてＳＯＩ構造を有す
るＬＤＭＯＳＦＥＴを用い、前記受光素子と前記ＬＤＭ
ＯＳＦＥＴの内、少なくとも前記ＬＤＭＯＳＦＥＴが電
気的に浮遊状態で外部電位に依存しないフロ−ティング
フレ−ム上に配設され、前記受光素子のアノ−ドと前記
ＬＤＭＯＳＦＥＴのゲ−ト電極とが電気的に接続され、
前記受光素子のカソ−ドと前記ＬＤＭＯＳＦＥＴのソ−
ス電極とが電気的に接続され、前記ＬＤＭＯＳＦＥＴの
ドレイン電極が出力端子フレ−ムに電気的に接続されて
成ることを特徴とする光結合型半導体リレ−。1. A light-emitting element that emits light in response to a signal on an input side, a light-receiving element that generates a photoelectromotive force by receiving an optical signal from the light-emitting element, and a light-emitting element that responds to the photoelectromotive force of the light-receiving element. In an optically coupled semiconductor relay comprising an on / off output switching element, an LDMOSFET having an SOI structure is used as the output switching element, and the light receiving element and the LDM are used.
Of the OSFETs, at least the LDMOSFET is electrically floating and is disposed on a floating frame that does not depend on an external potential, and the anode of the light receiving element and the gate electrode of the LDMOSFET are electrically connected. Connected to
Cathode of the light receiving element and source of the LDMOSFET
And a drain electrode of the LDMOSFET is electrically connected to an output terminal frame.
JP17430797A 1997-06-30 1997-06-30 Optically coupled semiconductor relay Expired - Lifetime JP3468033B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17430797A JP3468033B2 (en) 1997-06-30 1997-06-30 Optically coupled semiconductor relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17430797A JP3468033B2 (en) 1997-06-30 1997-06-30 Optically coupled semiconductor relay

Publications (2)

Publication Number Publication Date
JPH1126804A true JPH1126804A (en) 1999-01-29
JP3468033B2 JP3468033B2 (en) 2003-11-17

Family

ID=15976376

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Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612639B2 (en) * 2005-10-25 2009-11-03 Yazaki Corporation Relay module and electrical component unit
CN106020284A (en) * 2016-07-19 2016-10-12 南京工程学院 Electric cooling system for electric car control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612639B2 (en) * 2005-10-25 2009-11-03 Yazaki Corporation Relay module and electrical component unit
CN106020284A (en) * 2016-07-19 2016-10-12 南京工程学院 Electric cooling system for electric car control system

Also Published As

Publication number Publication date
JP3468033B2 (en) 2003-11-17

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