JPH11266171A - Frequency converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the frequency divided-frequency ratio (1/N) of a local oscillation circuit constituted of a PLL to be enlarged by a simple structure, to enable a superior phase noise characteristics to be obtained, and to enable the S/N in a transmitter/receiver to be largely improved. SOLUTION: Any one of local oscillation circuit 6 out of frequency conversion circuits of plural steps consisting of local oscillation circuits 3 and 6 is constituted, so that two frequency signals forming a frequency difference corresponding to the minimum step (for example, 100 kHz) of a reception high frequency signal are switched and outputted in turn. As a result, a tuning function in a frequency conversion circuit is distributed so that it is possible to enlarge a PLL frequency division ratio (1/N) in the other local oscillation circuit 3 and to improve phase noise characteristics in a VCO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a frequency converter of a double superheterodyne type or the like employed in a transceiver for wireless communication.

[0002]

2. Description of the Related Art In a satellite communication employing a frequency division multiple access (FDMA) system, each earth station can connect to a repeater of one satellite using different frequency bands. Frequency division multiplexing (FDM), which modulates voice and data on multiple carriers with different frequencies
Is used.

In mobile communication using one channel for many calls, a frequency division switching system is adopted.
When dividing a frequency, the above-described frequency division multiplexing method (F
DM) is adopted.

In a transceiver that handles the frequency division multiplexing method,
Although a frequency converter is incorporated, in the single super system, spurious such as beat disturbance or image disturbance due to an output signal of a local oscillation circuit or a harmonic thereof is generated.
In order to solve these problems, a frequency conversion circuit using a cascade connection of a plurality of stages such as a double superheterodyne system is often used.

More specifically, a conventional frequency converter incorporating a double superheterodyne system in a receiver will be described with reference to FIG.
The high-frequency signal of ３０30 MHz is supplied to a first frequency conversion circuit (MIX) 2. The first frequency conversion circuit 2 has a frequency of 73.5 to 99.5 in 100 KHz steps.
A first local oscillation circuit 3 for generating a first local oscillation signal 3a of MHz is connected.

Accordingly, the first frequency conversion circuit 2 converts the received high-frequency signal into 69.5 to 7 in steps of 100 KHz.
The first IF signal is converted to a first intermediate frequency (IF) signal of 0.5 MHz, and the first IF signal is passed through a first band-pass filter (BPF) 4 having a bandwidth of 1 MHz to a second frequency conversion circuit (MIX). 5 is supplied.

[0007] The second frequency conversion circuit 5 has a 72.5M
A second local oscillation circuit 6 for generating a second local oscillation signal 6a of 1 Hz is connected. Accordingly, a second intermediate frequency (IF) signal of 2 to 3 MHz in 100 KHz steps is derived from the second frequency conversion circuit 5, and the second I
The F signal is a second band-pass filter (B
The signal is supplied to a demodulation circuit 8 and an audio output circuit 9 via a PF 7.

The first local oscillation circuit 3 has a PLL (Phase Lock Loop) as shown in FIG.
(Ked Loop).

That is, a high-precision reference frequency fr signal from a reference signal oscillator 31 composed of a crystal oscillator or the like is divided by a first frequency divider 32 into a frequency division ratio (1 / R) (R is a positive integer). ), And is supplied to the phase comparator 33. An output signal 3a (from a voltage controlled oscillator (VCO) 35) supplied to a phase comparator 3 through a second frequency divider 34 having a frequency division ratio (1 / N) (N is a positive integer) is provided. The phase is compared with the frequency fo), and the detected phase difference is supplied to the VCO 35 via the loop filter 36.

As described above, the first local oscillation circuit 3 in the conventional frequency converter is constituted by a direct frequency-divided frequency synthesizer using a PLL.
In order to obtain a tuning output frequency fo (73.5 to 99.5 MHz) at an interval (step) of 5 to 100 KHz, as shown in FIG.
7 indicates that the frequency division ratio 1 / N in the frequency divider 34 is 1 in response to the oscillation output of the VCO 35 in steps of 100 KHz.
/ 735 to 1/995.

By the way, in the direct frequency dividing type frequency synthesizer using the PLL, the VCO 35 constituted cannot originally expect high-precision frequency stabilization like a crystal oscillator or the like, so that the tuning output signal is well known. Carrier waves undergo phase modulation by noise due to frequency fluctuations of the oscillation frequency itself, and thus have a property of exhibiting a so-called phase noise characteristic.

The phase noise characteristic depends on the loop gain of the PLL. Generally, the smaller the loop gain K is, the larger the phase noise is generated in the loop band. The loop gain K of the PLL is obtained by setting the gain of the phase comparator 33 to Kφ, the VCO 35
In the circuit shown in FIG. 7, the loop gain K is Kφ · Kv / 735 to 995, where Kv is the gain of Kv and the frequency division ratio of the frequency divider 34 is 1 / N. Becomes

As described above, in a frequency conversion device composed of a direct frequency-divided frequency synthesizer using a PLL, the phase noise characteristic is determined by the loop gain K in the PLL, and the minimum tuning step (100 KHz) of the output signal in the conventional device. ) Is set by the frequency division ratio 1 / N of the frequency divider 34 itself.

[0014]

As described above, in a conventional frequency converter of a double superheterodyne system in which a plurality of frequency converters are cascade-connected, a PLL is used for local oscillation of one of the frequency converters. But P
As described above, as the frequency step of the output of the voltage controlled oscillator (VCO) becomes smaller, LL becomes proportional to the PLL.
, The loop gain K of the oscillation output became small, and the phase noise characteristic of the oscillation output deteriorated accordingly.

Therefore, even if the frequency step of the oscillation output in the PLL becomes small, in order to make the loop gain of the PLL sufficiently high, it is conceivable to provide a frequency converter in the PLL itself. Providing a frequency converter in the above has a drawback that the circuit configuration becomes complicated and new spurs are likely to be generated accordingly.

[0016] The circuit configuration of the local oscillating circuit includes a PLL.
(Direct Digital Synthesizer: Di)
Rect Digital Synthesizer)
However, due to the DDS configuration and the required conversion characteristics of the D / A converter, there is a problem that sufficient spurious characteristics cannot be obtained.
When it was desired to obtain a fixed frequency tuning step of a tuning step of 00 KHz, it was an issue how to obtain a good phase noise characteristic.

[0017]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and has a first frequency conversion circuit and a second frequency conversion circuit cascaded to the first frequency conversion circuit. In the frequency conversion device configured by the frequency conversion circuit, at least one of the local oscillation circuits connected to the first or second frequency conversion circuit is configured by a direct frequency-divided frequency synthesizer using a PLL, The local oscillation circuit connected to the other frequency conversion circuit is configured to alternately switch and derive two different frequency signals.

As described above, in the frequency conversion device according to the present invention, one of the first and second frequency conversion circuits is configured such that one local oscillation circuit alternately switches and outputs two different frequency signals. Therefore, decentralization of the tuning function is realized, and to obtain a certain frequency tuning step as a device,
The frequency tuning step of the local oscillation circuit connected to the other frequency conversion circuit can be increased, and the deterioration of the phase noise characteristic due to the decrease in the loop gain of the PLL can be suppressed.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the frequency converter according to the present invention will be described below in detail with reference to FIGS. The same components as those of the conventional device shown in FIGS. 6 and 7 are denoted by the same reference numerals, and detailed description is omitted.

FIG. 1 is a block diagram showing a first embodiment of the frequency converter according to the present invention.

3-30M received via antenna 1
The high-frequency signal of 1 Hz is supplied to a first frequency conversion circuit 2, and the first frequency conversion circuit (MIX) 2 includes a first frequency-divided frequency synthesizer using a PLL as in the related art. In the first embodiment, the first local oscillation circuit 3 has a frequency of 73.4 MHz to 99.4 MHz in steps of 200 KHz as shown in Table 1 below. Local signal 3
Generate and derive a.

[0022]

[Table 1] Therefore, the first frequency conversion circuit 2 converts the received high-frequency signal to 2
The first of 69.4 to 70.5 MHz in steps of 00 KHz
, And the converted first IF signal is supplied to a second frequency conversion circuit (MIX) 5 via a first BPF 4 having a bandwidth of 1.1 MHz.

A second local oscillation circuit 6 is connected to the second frequency conversion circuit 5. The second local oscillation circuit 6 has an output frequency difference of 100 kHz which is the minimum frequency step. The first crystal oscillation circuit 61 of 72.4 MHz and the second crystal oscillation circuit 62 of 72.5 MHz are switched and derived, and a second frequency conversion circuit (MI
X) 5.

As described above, the second local oscillation circuit 6
Two local oscillation signals (72.4 MHz, 7
2.5 MHz) is alternately switched and derived, so that 3.0 to 30.0
The high frequency signal of MHz is applied to the PL in the first local oscillation circuit 3.
L in a direct-divide frequency synthesizer
Although the local oscillation signal 3a is generated in the KHz step, a desired reception IF signal in the 100 KHz step is derived from the second frequency conversion circuit 5 as shown in Table 1 above, as in the conventional case. Second BPF with 1 MHz bandwidth
The signal is supplied to a demodulation circuit 8 and an audio output circuit 9 via a.

In the above description, the second local oscillation circuit 6 is composed of two crystal oscillation circuits 61 and 62 and its switch. However, this local oscillation circuit 6 may be constituted as shown in FIG. it can.

That is, 10 signals from the reference signal oscillator 63
The reference frequency signal of MHz is alternately switched and divided into 1/25 and 1/20 in the frequency divider 64, respectively, and the difference frequency is 0.4 MHz and 0.5 MHz, which are 100 KHz.
A signal of Hz is generated and supplied to the phase comparator 65.

Another frequency divider 66 is connected to the phase comparator 65, and the frequency divider 66 is connected to a voltage controlled oscillator (VCO) 67.
72.4 MHz and 72.5 MH supplied alternately from
The output signal of z is frequency-divided into 1/181 and 1/145, respectively, and signals of 0.4 MHz and 0.5 MHz are similarly generated and supplied to the phase comparator 65.

Therefore, from the VCO 67, 100 KHz
Frequency signals fo (72.4 MHz and 72.5 MHz) consisting of frequency differences corresponding to the intervals (steps)
Are alternately derived. This signal is synchronized with the switching of the output signal of the VCO 67 by the voltage control and supplied from the frequency dividing ratio switch 69 to the frequency dividers 64 and 66 with good timing. Be executed.

As described above, in the first embodiment, each of the first local oscillation circuit 3 and the second local oscillation circuit 6 is constituted by a direct frequency-divided frequency synthesizer using a PLL. , At least the first local oscillation circuit 3
In the PLL configured as described above, the output frequency 7
In the 3.4 to 99.4 MHz band, the tuning frequency step is configured to be 200 KHz, and the frequency division ratio 1 / N in the PLL frequency divider 34 is 1/367 to 1/497.
Can be switched within the range.

Therefore, the loop gain K of the PLL shown in FIG.
Is Kφ · Kv / 367 to 497, and the frequency divider 3 in the conventional first local oscillation circuit 3 shown in FIGS.
4, ie, the loop gain K is approximately twice as large as that in the case of 1/735 to 995, and the phase noise characteristic is approximately 6
dB can be improved.

In the first embodiment, the frequency conversion circuit is constituted by cascade connection of two stages. However, the frequency conversion circuit may be constituted by three stages depending on the reception frequency band and the configuration of the reception circuit.

FIG. 4 is a block diagram showing a second embodiment of the frequency conversion device according to the present invention having a three-stage frequency conversion circuit.

That is, the high-frequency signal in the 1.5 GHz band (1500 to 1532 MHz) received via the antenna 1 is supplied to the first frequency conversion circuit (MIX) 2, and is supplied to the first frequency conversion circuit 2. Is 1432 MHz to 146 in 4 MHz steps as shown in Table 2 below.
A first local oscillation circuit 3 composed of a direct frequency-divided frequency synthesizer using a PLL for generating a local oscillation signal 3a of 0 MHz is connected.

[Table 2] In the first frequency conversion circuit 2, 68.0 to 72.0
After being converted to a first intermediate frequency (IF) signal of 1 MHz, the signal is supplied to a second frequency conversion circuit (MIX) 5 through a first BPF 4 having a bandwidth of 4 MHz, and the second frequency conversion circuit 5 200K as in the first embodiment.
A second local oscillator 6 composed of a direct frequency-divided frequency synthesizer using a PLL that generates a local oscillation signal 6a of 98.0 MHz to 101.8 MHz in Hz steps is connected.

Accordingly, the second IF of 29.8 MHz to 30.0 MHz converted and output by the second frequency conversion circuit 5 is used.
The signal is supplied to a third frequency conversion circuit (MIX) 10 via a second BPF 7 having a pass bandwidth of 200 KHz.

A third local oscillation circuit 11 is connected to the third frequency conversion circuit 10, and the third local oscillation circuit 11
The output signals 111a and 112a of the 32.4 MHz first crystal oscillation circuit 111 and the 32.5 MHz second crystal oscillation circuit 112, in which the frequency difference becomes 100 KHz, are alternately switched and derived. It is supplied to the conversion circuit 10.

Therefore, as shown in Table 2, the third IF signal converted and output by the third frequency conversion circuit 10 is converted into a third B signal as a received signal in 100 KHz steps.
The signal is supplied to the demodulation circuit 8 and the audio output circuit 9 via the PF 12.

As described above, in the frequency converter according to the second embodiment shown in FIG. 4, the output of the PLL included in the first local oscillation circuit 3 is tuned in 4 MHz steps, and the second local oscillation is performed. 200 KHz in PLL of oscillation circuit 6
The output is tuned in steps, and 32.4 MHz and 32.5 MHz are switched and derived in the third local oscillation circuit 11.

Therefore, in the first local oscillation circuit 3,
Since the frequency step of the PLL is 4 MHz, the frequency divider 3
4 has a sufficiently large frequency division ratio of 1/358 to 1/365, and the PLL in the second local oscillation circuit 6
Of 1 / N is also 1/49 as in the first embodiment.
0 to 1/509, the value of the loop gain K of the PLL is also at most about Kφ · Kv / 500 in the device according to the second embodiment. The characteristics can be improved.

The third local oscillation circuit 11 shown in FIG.
Has been described as comprising two crystal oscillation circuits 111 and 112 and a switch thereof, but the local oscillation circuit 11 can also be constituted by a direct frequency-divided frequency synthesizer using a PLL as shown in FIG.

That is, 1 from the reference signal oscillator 113
The reference signal of 0 MHz is divided by 1 in the frequency divider 114.
The frequency is switched to / 25 and 1/20, and the signals of 0.4 MHz and 0.5 MHz are switched and supplied to the phase comparator 115.

This phase comparator 115 has a frequency division ratio of 1 /
Via a second divider 166 which is 81 and 1/65,
An output signal (frequency fo: 32.4 MHz and 32.5 MHz) from the voltage controlled oscillator (VCO) 117 is supplied, and the detected phase difference is supplied to the VCO 117 via the loop filter 118.

Therefore, each of the frequency dividers 114 and 116 is synchronously switched by the switching signal from the frequency division ratio switch 119, and has a frequency difference corresponding to the interval (step) of 100 KHz from the VCO 117. The two frequency signals fo are alternately derived.

In each of the above embodiments, the configuration in which the receiver includes a double or more superheterodyne is described, but the same effect can be obtained in the transmitter.

In each of the first to third local oscillation circuits 3, 6, and 11 constituted by a PLL, each of the frequency division ratio switches 3
The switching operations in 6, 37, 69, and 119 can be executed by program control by a prescaler or the like corresponding to the timing of voltage control of the VCO.

As described above, in the frequency converter according to the present invention, in the local oscillation circuit connected to the frequency conversion circuit having a plurality of stages, at least one of the local oscillation circuits has the difference frequency corresponding to the minimum step. Since the two frequency signals are alternately switched and derived, the tuning function is distributed as a whole, and the frequency division ratio 1 / N of the frequency divider formed in the PLL can be increased. Therefore, as a result, the phase noise characteristic accompanying the loop gain reduction is greatly improved, and a remarkable effect can be obtained when applied to satellite communication as well as general wireless communication.

[0046]

As described above, according to the frequency converter of the present invention, the frequency division ratio (1 / N) of the local oscillation circuit constituted by the PLL can be increased with a simple configuration. Therefore, good phase noise characteristics can be obtained, and S / N in the transceiver can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a frequency conversion device according to the present invention.

FIG. 2 is a circuit diagram of a first local oscillation circuit in the device shown in FIG.

FIG. 3 is a circuit diagram of a second local oscillation circuit in FIG. 1;

FIG. 4 is a configuration diagram showing a second embodiment of the frequency conversion device according to the present invention.

FIG. 5 is a circuit diagram of a third local oscillation circuit in FIG. 4;

FIG. 6 is a configuration diagram showing a conventional frequency conversion device.

FIG. 7 is a circuit diagram of a first local oscillation circuit shown in FIG. 6;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 antenna 2 first frequency conversion circuit (MIX) 3 first local oscillation circuit 31 reference signal oscillator 33 phase comparator 34 frequency divider (1 / N) 35 voltage controlled oscillator (VCO) 37 frequency division ratio switch 4 First band pass filter (BPF) 5 Second frequency conversion circuit (MIX) 6 Second local oscillation circuit 61 First crystal oscillation circuit 62 Second crystal oscillation circuit 63 Reference signal oscillator 64 Divider (1) / R) 65 Phase comparator 66 Frequency divider (1 / N) 67 Voltage controlled oscillator (VCO) 69 Frequency division ratio switch 7 Second band pass filter (BPF) 8 Demodulation circuit 9 Audio output circuit 10 Third Frequency conversion circuit (MIX) 11 Third local oscillation circuit

Claims (4)

[Claims] 1. A frequency conversion device comprising a first frequency conversion circuit and a second frequency conversion circuit cascade-connected to the first frequency conversion circuit, wherein the first or second frequency conversion circuit is provided. At least one of the local oscillation circuits connected to the circuit is constituted by a direct frequency-divided frequency synthesizer using a PLL, and the local oscillation circuit connected to the other frequency conversion circuit alternately outputs two different frequency signals. A frequency conversion device configured to perform switching derivation. 2. The frequency conversion device according to claim 1, wherein the frequency difference between the two frequency signals alternately switched and derived is a minimum frequency step. 3. A local oscillation circuit connected to the other frequency conversion circuit is constituted by a direct frequency-divided frequency synthesizer using a PLL, and the two different frequency signals are output from a direct frequency-divided frequency synthesizer using a PLL. 3. The frequency divider according to claim 1, wherein said frequency divider is generated by switching a frequency dividing ratio of a frequency divider forming a synthesizer.
The frequency conversion device according to item 1. 4. The frequency divider is controlled to simultaneously switch and divide each output signal of a voltage controlled oscillator and a reference signal oscillator forming a direct frequency divider type frequency synthesizer using the PLL. The frequency converter according to claim 3.