JPH11251548A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably read minute cell signals by reducing word line drive noise. SOLUTION: Dummy word lines WD1, WD2 and dummy transistors TD1, TD2 constituted of MOS transistors are formed on a memory mat 2. The dummy transistor TD1 is arranged in common with memory cells S of a data line D, and the dummy transistor TD2 is arranged in common to memory cells S of a data line/D. When a word line W of the data line/D side is driven, a dummy word line DW1 of the data line D side is driven at the same time. The same capacitance as an overlapped capacitance Cv in a transistor T of the memory cell S added to the data line/D is driving to the data line D by having the dummy transistor TD1 driven, and noise is canceled by having the noise which has the same magnitude as the noise of the data line/D couple with the data line D as a pair line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a DRAM (Dynamic Land).
The present invention relates to a technology that is effective when applied to noise reduction at the time of data reading in an Om Access Memory.

[0002]

2. Description of the Related Art According to studies made by the present inventor, D
In RAM, as a technology for reducing word line driving noise,
There is a so-called two-intersection bit system in which the data lines have a paired structure and the data lines for the sense amplifiers are arranged in a folded shape.

In this case, the word lines and the data lines are arranged so that the cross-coupling capacitances thereof are substantially equal to each other for each one data line in the paired line structure. The configuration is such that generation of a noise voltage on the data line is canceled.

An example of this type of semiconductor integrated circuit device is described in detail in November 30, 1984.
Published by Ohm Co., Ltd., published by The Institute of Electronics and Communication Engineers (eds.), "LSI Handbook" P494, P495. This document describes a layout method of bit lines in a DRAM.

[0005]

However, the inventor of the present invention has found that the two-intersection bit scheme as described above has the following problems.

That is, the parasitic capacitance of the switch MOS transistor forming the memory cell is added to only one of the data lines, so that there is a problem that differential noise is generated.

[0007] With the recent miniaturization of memory cells,
The gate oxide film of the switch MOS transistor described above is formed thin. Accordingly, the parasitic capacitance of the MOS transistor tends to increase, and a large noise voltage is generated on the data line, which may make data reading difficult.

An object of the present invention is to provide a semiconductor integrated circuit device capable of greatly reducing word line driving noise and stably reading out a minute cell signal.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device of the present invention, the memory cell on one data line side of the two-intersection bit type data line in which the data line has a pair structure and the data line for the sense amplifier is arranged in a folded shape. , Which has a capacitance equivalent to an overlap capacitance parasitic on a transistor used as a switch of a memory cell, and has a capacitance on one data line based on a drive signal input to a drive control unit. Is provided in common to the first capacitance means for adding
A second capacitor that has a capacitance equivalent to an overlap capacitance parasitic to a transistor used as a switch of a memory cell, and adds a capacitance to one data line based on a drive signal input to a drive control unit; Capacitance means, the first
A first dummy word line corresponding to the first capacitance means, a second dummy word line corresponding to the second capacitance means, and a first static word line for selecting the first static word line. First driving means for generating a driving signal for driving the capacitance means;
And second driving means for selecting the second dummy word line and generating a driving signal for driving the second capacitance means.

Further, in the semiconductor integrated circuit device according to the present invention, the first and second capacitance means are MOS transistors, and a driving signal is inputted to a gate so that one or the other of the data lines is electrostatically charged. This is to add capacity.

Further, the semiconductor integrated circuit device of the present invention
A memory cell is provided between a word line corresponding to a memory cell on one data line side and another data line in a two-intersection bit system in which a data line has a paired structure and a data line for a sense amplifier is folded. One of the data lines which has a capacitance equivalent to the parasitic capacitance of a transistor used as a switch, and which selects a word line corresponding to a memory cell on one of the data lines and is input to the drive control unit A third capacitance means for adding a capacitance to the other data line based on a drive signal for driving the memory cell on the side, and a static capacitance equivalent to an overlap capacitance parasitic on a transistor used as a switch of the memory cell. The word line corresponding to the memory cell on the other data line side having the capacitance is selected and the memory cell on the other data line side inputted to the drive control unit is selected. On one of the data lines on the basis of a drive signal for moving it is provided with a fourth of the capacitance means for adding a capacitance.

Further, in the semiconductor integrated circuit device according to the present invention, the third and fourth capacitance means are MOS transistors, and a driving signal is inputted to a gate so that one or the other of the data lines is electrostatically charged. This is to add capacity.

Accordingly, the parasitic capacitance of one and the other data lines can be made the same, so that data line noise can be significantly reduced.

Furthermore, the semiconductor integrated circuit device of the present invention
A MOS transistor used as a switch of a memory cell in a two-intersection bit system in which a data line has a paired structure and a data line with respect to a sense amplifier is arranged in a folded shape is an N ⁺ which serves as a gate electrode and a source and a drain.
The P ^- type semiconductor region is formed offset from the P ^- type semiconductor region, the P ^- type semiconductor region is formed on the surface of the semiconductor wafer where the gate is located, and the N ^- type semiconductor region serving as a drain and a source is formed below the P ^- type semiconductor region. Things.

Thus, the MOS constituting the memory cell
Since the overlap capacitance, which is the parasitic capacitance of the transistor, can be greatly reduced, data line noise can be further reduced.

As described above, the reading of the memory cell can be performed stably, and the reliability of the semiconductor integrated circuit device can be improved.

Further, since the memory cell itself can be reduced, the layout area of the memory cell can be reduced, and the semiconductor integrated circuit device can be reduced in size.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a memory according to Embodiment 1 of the present invention, and FIG. 2 is an explanatory diagram of a memory mat in the memory according to Embodiment 1 of the present invention.

In the first embodiment, a memory (semiconductor integrated circuit device) 1, which is a DRAM, is provided with a memory mat 2 in which memory cells, which are minimum units of storage, are regularly arranged in an array.

A word driver 3 and a row decoder 4 are connected to the memory mat 2. The word driver 3 receives the output of the row decoder 4 and applies a selection pulse voltage to a word line. 2, the word line in the row (row) direction is selected.

Further, a sense amplifier 5 is connected to the memory mat 2, and the sense amplifier 5 amplifies a cell read signal of the memory mat 2. Sense amplifier 5
Is connected to a column driver 6 and a column decoder 7. The column driver 6 includes a column decoder 7
, A selection pulse voltage is applied to the bit line, and the column decoder 7 selects the bit line in the column (column) direction.

A row address buffer 8 is connected to the row decoder 4. The row address buffer 8 receives an address signal in the row direction, generates respective internal address signals, and supplies the row decoder 4 with the row address. Output.

Further, a column address buffer 9 is connected to the column decoder 7, and the column address buffer 9 receives an address signal in a column direction.
Each internal address signal is generated and output to the column decoder 7.

The sense amplifier 5 includes a control circuit 10
Are connected to the control circuit 10, and a data input buffer 11 and a data output buffer 12 are connected to the control circuit 10. The control circuit 10 controls data exchange between the sense amplifier 5 and the data input buffer 11 and the data output buffer 12. The data input buffer 11 takes in input data at a predetermined timing, and the data output buffer 12 outputs output data at a predetermined timing.

Next, the memory configuration of the memory mat 2 will be described.

As shown in FIG. 2, the memory mat 2
It is configured by the intersection bit method.
^{When N + M} bits of information can be stored, 2 ^{N + M} memory cells S are two-dimensionally arranged in a matrix structure. The data lines D and / D connecting the same number of memory cells S form a pair, and the sense amplifier 5 is connected thereto.

The memory cell S is composed of a transistor T, which is a MOS transistor serving as a switch, and a capacitor C for storing charges.

A word line W is provided so as to be orthogonal to these data lines D and / D.
The memory cell S is provided at each intersection of D and the word line W. Also, the word line W
A word driver WD is connected, and the word driver WD drives a word line W to directly drive a memory cell S.

Further, the memory mat 2 includes a dummy word line (first dummy word line) DW1 and a dummy word line (second dummy word line) DW2, and a dummy transistor (first electrostatic word line) composed of a MOS transistor. A capacitance means) TD1 and a dummy transistor (second capacitance means) TD2. Dummy transistor TD
Reference numeral 1 is commonly arranged in the memory cell S of the data line D, and the dummy transistor TD2 is arranged in common to the memory cell S of the data line / D.

The gate (drive control section) of the dummy transistor TD1 is connected to the dummy word line DW1, and one connection section is connected to the data line D. The gate (drive control section) of the dummy transistor TD2 is connected to the dummy word line DW2, and one connection section is connected to the data line / D, and the dummy transistor TD2
Neither of the other connection portions of the TD1 and TD2 is connected.

Therefore, these dummy transistors TD
1, TD2 are used as capacitance elements, and the capacitance Cd, which is the overlap capacitance of the dummy transistors DT1 and DT2, is equal to the overlap capacitance Cv between the gate of the transistor T and the diffusion layer in the memory cell S. It has the same capacity.

The dummy word lines DW1 and DW2 have dummy word drivers (first driving means), respectively.
DWD1, dummy word driver (second driving means) D
WD2 is connected. Dummy word driver DWD
1, DWD2 are the dummy word lines DW1, DW2
To drive the dummy transistors TD1, T
D2 is driven directly.

Next, the operation of the present embodiment will be described.

For example, when the word line W on the data line / D side is driven, the dummy word line DW1 on the data line D side, which is a pair of the data line / D, is driven at the same time.

When the word line W is driven, the data line / D is added with the above-described overlap capacitance Cv in the memory cell S and the cross-coupling capacitance Cc between the word line W and the data line / D. , Large noise is coupled to the data line / D.

On the other hand, the data line D is connected to the dummy word line DW
1 is driven, the cross-coupling capacitance Cc between the word line W and the data line D and the dummy transistor T
The overlap capacitance Cv between the gate and the diffusion layer at D1
Is added, and a large noise is also coupled to the data line D.

Thus, a small signal appearing on the data line / D from the selected memory cell S can be stably discriminated. That is, even if a large noise is coupled to the data line / D, the same amount of noise is coupled to the data line D as a pair, so that the sense amplifier 5 amplifies only the voltage of the difference between the pair, Since the same voltage cancels out, the coupling noise is canceled out as a common mode voltage, and only the signal is amplified.

Thus, according to the present embodiment, dummy word lines DW1 and DW2 and dummy transistor T
By providing D1 and TD2, the dummy transistor on the other data line side of the selected memory cell S can be driven, and the data lines D and / D can have the same parasitic capacitance. Noise can be significantly reduced.

Further, since reading from the high-sensitivity memory cell can be performed stably, the capacitance value of the memory cell S can be reduced, the layout area of the memory cell S can be reduced, and the reliability of the memory 1 can be reduced. Performance can also be improved.

(Embodiment 2) FIG. 3 is an explanatory diagram of a memory mat in a memory according to Embodiment 2 of the present invention.

In the second embodiment, the memory 1 (FIG. 1), which is a DRAM, includes a memory mat 2, a word driver 3, a row decoder 4, a sense amplifier 5, and a column driver 6 as in the first embodiment. , Column decoder 7,
Row address buffer 8, column address buffer 9,
It comprises a control circuit 10, a data input buffer 11 and a data output buffer 12.

As shown in FIG. 3, the memory configuration of the memory mat 2 includes a word line W and a data line / D corresponding to the memory cell S on the data line D side of the paired data lines D and / D. Is provided so that a dummy transistor (third capacitance means) TD3 is located between the word line W and the data line D corresponding to the memory cell S on the data line / D side. Fourth capacitance means) TD4 is provided.

The gate (drive control section) of the dummy transistor TD3 is connected to the word line W on the data line D side, and one connection section is connected to the data line D. The gate of the dummy transistor TD4 (drive control unit)
Is connected to the word line W on the data line / D side, and one connection portion is connected to the data line / D. The other connection portions of these dummy transistors TD3 and TD4 are in an NC state where none of them is connected.

Also in this case, for example, when the word line W on the data line / D side is driven, the overlap capacitance Cv and the cross-coupling capacitance Cc of the memory cell S are added to the data line / D, Although large noise is coupled to the line / D, the dummy transistor TD3 is also driven at the same time, so that the data line D is also added with the cross-coupling capacitance Cc and the overlap capacitance Cv of the dummy transistor TD3. Large noise is also coupled to D, and the noise becomes a common-mode voltage and is canceled.

As a result, in the second embodiment,
With the dummy transistors TD3 and TD4, an electrostatic capacitance having noise as a common-mode voltage can be added to one of the data lines D and / D, so that data line noise can be significantly reduced.

Further, since a dummy word line and a dummy word driver are not required, the area of the peripheral circuit can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

For example, according to the first and second embodiments, the dummy transistor adds the same overlap capacitance as that of the memory cell transistor.
Without providing these dummy transistors, the generation of noise may be reduced by reducing the overlap capacitance Cv of the transistor T in the memory cell as shown in FIG. Here, an insulating film is not shown in FIG. 4 for simplification.

In the transistor T in this case, a gate electrode G is located above a P-type silicon substrate (semiconductor wafer) PK as a semiconductor chip, and a surface of the P-type silicon substrate PK below the gate electrode G is P ^- type semiconductor region P
S is formed.

At both sides of the P ⁻ type semiconductor region PS, semiconductor regions functioning as the source and drain of the transistor T are formed, and the impurity regions are composed of N ⁺ type semiconductor regions NS1 and N ⁻ type. And a semiconductor region NS2.

The N ⁺ type semiconductor region NS1 is formed so as to sandwich the P ⁻ type semiconductor region PS from both sides.
^On the side surface of the ⁺ type semiconductor region NS1, an N ⁻ type semiconductor region N
S2 is formed so as to be located immediately below P ⁻ type semiconductor region PS. Further, immediately below the gate electrode G, N ⁺
The mold semiconductor region NS1 is formed so as to be offset so as not to be located.

Therefore, in addition to the fact that the N ⁺ type semiconductor region NS1 does not overlap immediately below the gate electrode G and that the P ⁻ type semiconductor region PS acts as a shield layer, the gate voltage is lower than the threshold voltage. Since the capacitance between the gate and the impurity region functioning as the source and drain in the above, that is, the overlap capacitance can be eliminated,
Data line noise can be significantly reduced.

[0056] Further, as shown in FIG. 5, N ⁺ -type semiconductor region NS1 vicinity is increased to overlap capacitance and distance between the N ⁺ -type semiconductor region NS1 and the gate electrode G by scraping the corner portion of the gate electrode G of Cv can be reduced. Similarly, FIG. 5 does not show an insulating film for simplicity.

[0057]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the first and second capacitance means make the same parasitic capacitance on one data line and the other data line of the selected memory cell. Therefore, data line noise can be greatly reduced.

(2) Further, in the present invention, the third and fourth capacitance means make the capacitances of one and the other data lines of the selected memory cell equal to each other. Therefore, data line noise can be greatly reduced.

(3) Further, in the present invention, the data line noise can be further reduced by greatly reducing the overlap capacitance of the MOS transistor itself used as the switch of the memory cell in the two-intersection bit system. it can.

(4) According to the present invention, (1)
According to (3), the reading of the memory cell can be performed stably, and the reliability of the semiconductor integrated circuit device can be improved.
In addition, since the memory cell itself can be reduced, the layout area of the memory cell can be reduced, and the semiconductor integrated circuit device can be reduced in size.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a memory mat in the memory according to the first embodiment of the present invention;

FIG. 3 is an explanatory diagram of a memory mat in a memory according to a second embodiment of the present invention;

FIG. 4 is a cross-sectional view of a transistor in a memory cell provided in a memory according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view of a transistor in a memory cell provided in a memory according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 memory (semiconductor integrated circuit device) 2 memory mat 3 word driver 4 row decoder 5 sense amplifier 6 column driver 7 column decoder 8 row address buffer 9 column address buffer 10 control circuit 11 data input buffer 12 data output buffer S memory cell D, / D data line T transistor C capacitor W word line WD word driver DW1 dummy word line (first dummy word driver) DW2 dummy word line (second dummy word driver) TD1 dummy transistor (first capacitance means) TD2 Dummy transistor (second capacitance means) TD3 Dummy transistor (third capacitance means) TD4 Dummy transistor (fourth capacitance means) DWD1 Dummy word driver (first driving means) DWD2 dummy word driver (second driving means) Cd capacitance Cv overlap capacitance Cc cross-coupling capacitance PK P-type silicon substrate (semiconductor wafer) G gate electrode PS P ^- -type semiconductor region NS1 N ⁺ -type semiconductor region NS2 N ^- -type semiconductor region

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hitoko Aoyama 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Makoto Yoshida 6--16 Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center (72) Inventor Masatoshi Hasegawa 3-16, Shinmachi, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (5)

[Claims] 1. A two-intersection bit type semiconductor integrated circuit device in which a data line has a paired structure and a data line for a sense amplifier has a folded arrangement, wherein one of the data lines having the paired structure is provided. Is provided in common to the memory cells on the side, has the same capacitance as an overlap capacitance parasitic on a transistor used as a switch of the memory cell, and performs the one data based on a drive signal input to a drive control unit. A first capacitance means for adding capacitance to a line, and a parasitic element provided in a memory cell on the other data line side of the data line having the paired line structure and parasitic on a transistor used as a switch of the memory cell A second device that has a capacitance equivalent to the overlap capacitance and adds a capacitance to the one data line based on a drive signal input to a drive control unit; Capacitance means, a first dummy word line corresponding to the first capacitance means, a second dummy word line corresponding to the second capacitance means, and the first dummy word A first driving unit that generates a driving signal for driving the first capacitance unit by selecting a line; and a second driving unit that selects the second dummy word line to drive the second capacitance unit. A semiconductor integrated circuit device provided with second driving means for generating a driving signal. 2. The semiconductor integrated circuit device according to claim 1, wherein said first and second capacitance means are MOS transistors, and said one or other data line is provided by inputting a drive signal to a gate. A semiconductor integrated circuit device, wherein a capacitance is added to a semiconductor integrated circuit device. 3. A two-intersection bit type semiconductor integrated circuit device in which a data line has a paired structure and a data line for a sense amplifier has a folded arrangement, wherein one of the data lines having the paired structure is provided. Between the word line corresponding to the memory cell on the side and the other data line in the data line having the paired structure, the same capacitance as an overlap capacitance parasitic on a transistor used as a switch of the memory cell. The word line corresponding to the memory cell on one data line side is selected, and the capacitance is applied to the other data line based on a drive signal input to the drive control unit for driving the memory cell on one data line side. A third capacitance means to be added, and a capacitance equivalent to an overlap capacitance parasitic to a transistor used as a switch of a memory cell, and the other data A fourth method for selecting a word line corresponding to the memory cell on the side and adding a capacitance to one data line based on a drive signal input to the drive control unit for driving the memory cell on the other data line side A semiconductor integrated circuit device provided with capacitance means. 4. The semiconductor integrated circuit device according to claim 3, wherein said third and fourth capacitance means are MOS transistors, and said one or other data line is provided by inputting a drive signal to a gate. A semiconductor integrated circuit device, wherein a capacitance is added to a semiconductor integrated circuit device. 5. A two-intersection bit type semiconductor integrated circuit device in which a data line has a paired structure and a data line for a sense amplifier is folded, wherein a MOS transistor used as a switch of a memory cell has a gate. and the N ⁺ -type semiconductor region serving as an electrode and the drain and source are formed by offset, P on the semiconductor wafer surface of the gate is positioned ^- -type semiconductor region is formed, the P ^-
N serving as a drain and a source below the semiconductor region
^- a semiconductor integrated circuit device characterized by consisting of structure type semiconductor region is formed.