JPH1125068A - Filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain over-sampling by dividing a sample/hold circuit into plural sample/hold circuit groups, and adding data held by each sample/hold circuit group by switching one adding circuit. SOLUTION: This filter circuit is provided with a first sample/hold circuit group G1 constituted of plural sample/hold circuits SH11-SH1n, and a second sample/hold circuit group G2 constituted of sample/hold circuits SH21-SH2n. An analog input voltage Vin is inputted in parallel to those sample/hold circuits. First and second adding circuits SUM1 and SUM2 respectively add two outputs from multiplexers MUX2i, and input the added results to a subtracting circuit SUB. The adding circuits SUM1 and SUM2 are commonly used for the first and second groups G1 and G2. Thus, the addition of data held by each sample/ hold circuit group can be attained by switching one adding circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter circuit, and more particularly to a filter circuit effective as a matched filter circuit for a spread spectrum communication system in mobile communication or wireless LAN.

[0002]

2. Description of the Related Art A matched filter (matched filter) circuit is a filter for determining the identity of two signals. In a spread spectrum communication system, a user who should receive a signal transmits a received signal to its own spreading code. , And a correlation peak is detected, and synchronization acquisition and holding are performed.

Here, the spreading code is PN (i), the chip time Tc, the spreading factor M, and the input signal at a certain time (t) is S
(T) Assuming that the correlation output signal R (t) is at a certain time t, Expression (1) is obtained.

(Equation 1) Becomes PN (i) is a data string of 1-bit data.

For synchronous acquisition, it is necessary to perform double sampling or more samplings. Using a matched filter circuit of a plurality of systems, the operation of the above equation (1) is executed simultaneously by a plurality of systems, and the operation result is selected. Output or add together. Conventionally, to realize such a matched filter circuit, a digital circuit or a SAW
(Surface sound wave) elements have been used, but digital circuits have a large circuit scale and large power consumption, and are not suitable for mobile communication. On the other hand, SAW elements cannot easily realize an entire circuit with one element. There is a problem that the S / N ratio is low.

Accordingly, the inventors have filed Japanese Patent Application No. Hei 9-11652.
In No. 3, paying attention to the fact that the spreading code is a 1-bit data sequence, sample and hold the input signal as a time-series analog signal, and then branch this into a "1" or "-1" sequence by a multiplexer. Proposed a matched filter circuit that performs parallel addition of respective time-series signals by capacitive coupling and performs high-speed processing by a small-scale and power-saving LSI.

However, at present, further reduction in circuit scale and power consumption is desired.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above background, and it is an object of the present invention to provide a matched filter circuit which is capable of oversampling and which is smaller and consumes less power than before. Aim.

[0008]

A filter circuit according to the present invention divides a sample-and-hold circuit into a plurality of sample-and-hold circuit groups, and switches and uses one adder circuit. The addition is performed for the data held in.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment as a matched filter circuit of the filter circuit according to the present invention will be described with reference to the drawings.

In FIG. 1, a matched filter circuit includes a plurality of sample and hold circuits SH11 and SH1.
2,. . . , SH1n, the first sample-and-hold circuit group G1, the sample-and-hold circuits SH21, SH2
2,. . . , SH2n, and a second sample-and-hold circuit group G2 to which the analog input voltage Vin is input in parallel. First
Each of the sample and hold circuits SH1i of the sample and hold circuit group and each of the sample and hold circuits SH2i of the second sample and hold circuit group are provided so as to correspond to each other. Import as time series data. The sample / hold circuit group G1 and the sample / hold circuit group G2 have their capture timing set by clocks CLK1 and CLK2, respectively. Each clock has a chip time as a cycle, and each clock has a shift of a cycle of 1/2 chip time. Have. Therefore, for example, every half chip time, SH1
1, SH21, SH12, SH22,. . . , SH1
Vin is sequentially taken in n and SH2n. After that, data fetching by SH11 to SH2n is repeated with respect to the data after the next cycle. With such a configuration in which data transfer is not performed between the sample and hold circuits, it is possible to prevent a transfer error from occurring.

The sample and hold circuits SH of both groups
1i, multiple multiplexers MUX corresponding to SH2i
11 to MUX1n are provided, and the outputs of the corresponding sample and hold circuits SH1i and SH2i are input to the corresponding multiplexer MUX1i. The multiplexer MUX1i is a clock CLK having a cycle of the chip time.
3 is a control signal, switching is controlled by this control signal, and the output of the group G1 or G2 is selectively output every 1/2 chip time. Therefore, it is possible to hold two sets of time-series data shifted by チ ッ プ chip time, and double sampling is performed.

A plurality of multiplexers MUX2i are provided corresponding to the multiplexers MUX1i, and the output of each multiplexer MUX1i is output from the corresponding multiplexer MUX1.
2i. The multiplexer MUX2i is 1
It is an input 2 output, the output of which is a first output corresponding to a PN code of “1” (shown with a “+” sign in the figure),
It consists of a second output corresponding to a PN code of "0" (shown with a "-" sign in the figure). The first output is input to the first adder SUM1 in parallel, and the second output is the second adder SU.
M2 is input in parallel. The processing here corresponds to the multiplication of the equation (1).

The first and second addition circuits SUM1 and SUM2 add the first and second outputs from the multiplexer MUX2i, respectively, and input the addition result to the subtraction circuit SUB. The output switching of the multiplexers MUX21 to MUX2n is P
This is performed by the PN code stored in the N register PNG. As described above, the first output is selected when the PN code is “1” and the second output is selected when the PN code is “0”. Subtraction circuit S
UB subtracts the second output from the first output. PN register P
NG is a shift register in which the data of the last stage is fed back to the first stage, and the PN code is shifted every chip time.
Used cyclically.

The sample and hold circuit SH11 is configured as shown in FIG. 2, and the input voltage Vin2 is connected to the switch SW. The output of the switch SW is the capacitance C
21 and the output of the capacitance C21 is connected to three serial MOS inverters I1, I2 and I3. The output Vo2 of the final stage MOS inverter I3 is connected to the input of I1 via the feedback capacitance C22, so that Vin is generated at the output of I3 with good linearity. When SW is closed,
C21 is charged with a charge corresponding to Vin2, and I1 to I3
The feedback function guarantees a linear characteristic of the output. Then, when the switch SW is opened thereafter, the sample / hold circuit SH11 holds S (t).

The switch SW is controlled by a control signal S2, and the switch S1 is opened when the input voltage is to be taken after the SW is closed once.

The output of the last stage I3 is connected to ground via a ground capacitance C23, and the output of the second stage I2
Is connected to the power supply voltage Vdd and the ground via a pair of balanced resistances R21 and R22. With such a configuration, oscillation of the inverting amplifier circuit including the feedback system is prevented. SH12 to SH1
n, SH21 to SH2n are configured in the same manner, and the description is omitted.

As shown in FIG. 3, the switch SW is an n-type M
It comprises a transistor circuit T3 in which the source and the drain of the OS transistor are respectively connected to the drain and the source of the p-type MOS transistor. The input voltage Vin3 is connected to the drain side terminal of the nMOS of this transistor circuit, and the source terminal of the nMOS is connected. Is connected to an output terminal Vout3 via a dummy transistor DT3 having a similar configuration. S3 is input to the gate of the nMOS transistor in the transistor circuit T3, and a signal obtained by inverting S3 by the inverter I4 is input to the gate of the pMOS transistor. Thus, when S3 is at a high level, T3 is conductive, and when S3 is at a low level, T3 is cut off.

As shown in FIG. 4, the multiplexer MUX
Reference numeral 11 denotes a transistor circuit T4 in which the drain and the source of a pair of n-type and p-type MOS transistors are connected to each other.
1. The terminal on the source side of the nMOS of T42 is connected to the common output terminal Vout4, and the output of SH11 (Vin41 in the figure) is connected to the terminal on the drain side of the nMOS in T41.
Indicated by ), And the output of SH21 (indicated by Vin42 in the figure) is connected to the drain of T42. Gate of nMOS transistor in transistor circuit T41 and pMOS in transistor circuit T42
The signal S4 is input to the gate of the transistor, and T41
The signal obtained by inverting S4 with an inverter I5 is input to the gates of the pMOS and the nMOS of T42. Thus, when S4 is at a high level, T41 conducts and T42 is cut off, and when S4 is at a low level, T42 conducts and T41 is cut off. That is, MUX11 is S
By the control of 4, the output of SH11 or SH21 can be output alternatively. Note that MUX12 to MUX1n are configured in the same manner as MUX11, and will not be described.

In FIG. 5, the MUX 21 has a pair of multiplexers MUX51 and MUX52 similar to the MUX 11, and each multiplexer outputs the output (Vin
Shown at 51. ) And the reference voltage Vref. The control signal S5 is input to the MUX 51,
A signal obtained by inverting S5 with an inverter I6 is input to the MUX 51. That is, when S5 is at a high level, M
UX51 outputs Vin5 as output Vout51,
On the other hand, the MUX 52 outputs Vref as the output Vout 52. Conversely, when S5 is low, MUX 51
ref is output as output Vout51, while MUX5 is output.
2 outputs Vin5 as the output Vout52. Vo
out51 corresponds to the first output, and Vout52 corresponds to the second output.
Corresponds to output.

As described above, the addition circuits SUM1, SUM
Since 2 is used in common by the first and second groups G1 and G2, the circuit size of the adder circuit can be reduced to half of that in the conventional case, and the power consumption decreases accordingly.

In the equation (1), S (ti · Tc) is a voltage held by each sample and hold circuit, and PN
(I) is a signal S5 (spreading code) to be given to each sample and hold circuit at that time. The spreading code is constant with respect to the order of the signals held at a certain point in time, and a new signal is taken in at the timing of taking in a new signal instead of the oldest signal. At this time, each sample and hold circuit S
The correspondence between H11 to SH1n, SH21 to SH2n and PN (i) is shifted, and the PN code is shifted and circulated in the shift register in synchronization with the clock CLK4 as described above.

FIG. 8 shows the timing of the clocks CLK1 to CLK4. When the sampling period of one sample and hold circuit is ts, CLK1
And CLK2 have a phase difference of ts / 2, and CLK3 and C
LK4 uses the same clock as CLK1.
Here, if CLK1 is expressed by a function CLK (t) of time t, CLK2 is CLK (t + ts / 2), CL
K3 = CLK4 = CLK (t). Thus, even with double sampling, the PN register can be used at a relatively low speed.

Further, there are three sample-hold circuit groups, and a configuration in which the first multiplexer selects one of these sample-hold circuit groups can be similarly realized. The sampling clocks of the hold circuit group are CLKG1, CLKG2, CLKG
3. The control signal of the first multiplexer is CLKM
UX, shift register control signal CLKSR
If G, these relationships are as shown in FIG. In FIG. 11, CLKG1, CLKG2, CLKG
G3 has a period of ts and shifts by ts / 3, and CLKMUX has a period of ts / 3. Also CL
KSRG is the same signal as CLKG1.

In general, when the number of sample-and-hold circuit groups is m, the sampling period of each sample-and-hold circuit group is ts, and the clock for sampling the first sample-and-hold circuit group is CLK (t), The clock for sampling the i-th sample-hold circuit group is

The control signal of the first multiplexer selects one of the sample-and-hold circuits sequentially in a cycle of ts / m, and the control signal of the shift register is any one of the sample-and-hold circuits. The same clock as the group clock is used.

As shown in FIG. 6, the addition circuit SUM1 has M
UX21 to first output of MUX2n (Vin61 to Vin
6n. ) Are input to the capacitances C61 to C
6n, and these capacitances are connected to the same inverting amplifier circuit as in FIG. 2 while their outputs are integrated.
When the feedback capacitance of the inverting amplifier circuit is C64,
The output Vout6 of the addition circuit SUM1 is as shown in Expression (2).

(Equation 2) In the figure, I61, I62 and I63 are MOS inverters, R61 and R62 are balanced resistances, and C6g is a ground capacitance. Thus, all MUX21-
Instead of adding the outputs of the MUXs 2n by one set of capacitive coupling, it is of course possible to make the capacitive coupling hierarchical and add it stepwise.

As shown in FIG. 7, the subtraction circuit SUB has the SU
It has a capacitance C71 connected to the M1 output (shown as Vin71) and a capacitance C74 connected to the SUM2 output (shown as Vin72). The output of C71 is a three-stage series MOS inverter I71, I72, I7.
3 is connected. Last-stage MOS inverter I73
Is connected to the input of I71 via a feedback capacitance C72, such that Vin71 occurs at the output of I73 with good linearity. I7
The output of C3 is connected to a capacitance C75, and the output of C75 is integrated with the output of C74 and connected to MOS inverters I74, I75, and I76. The output of the final stage MOS inverter I76 is a feedback capacitance C.
76, connected to the input of I74, C74, C75
The output of the capacitive coupling consisting of I76 with good linearity
Output. Here, the output of I76, Vout7, is expressed by equation (3),

(Equation 3) If C71 = C72 and C74 = C75 = C76, equation (3) is simplified as equation (4).

(Equation 4) This means that the addition result is subtracted. In the figure, the pair of R71, R72 and the pair of R73, R74 are balanced resistances, respectively, and C73, C77
Is the ground capacitance.

The reference voltage Vref is set equal to the threshold voltage of the MOS inverter, and the threshold voltage is set to V in order to secure a sufficiently large dynamic range in both the positive and negative directions.
dd / 2 is often set. Where Vdd is MO
This is the power supply voltage of the S inverter.

FIG. 9 shows a second embodiment of the present invention.
The same or corresponding parts as in the embodiment are denoted by the same reference numerals. This embodiment is a more general filter circuit than the first embodiment. The multiplier is digital data of a plurality of bits. The difference from the first embodiment is that the multiplication circuit MUL is used instead of the multiplication circuit.
11 to MUL1n, and a multiplier register MREG is used instead of the PN register. The multiplier register is a multi-bit shift register.

In FIG. 10, the multiplication circuit MUL11 is k
Multiplied by a bit multiplier, and k capacitances C101, C102,. . . , C
Has 10k. These capacitances have their outputs integrated and input to a three-stage MOS inverter INV,
The output of NV is connected to its input via feedback capacitance C10f. Capacitance C101 to C1
Multiplexers MUX101 to MUX1
0k is connected to these multiplexers and the input voltage V
in10 (first multiplexer output) and reference voltage V
ref is connected. C101-C10k

[Outside 2] When the value of each bit of the multiplier mul is “1”, the multiplexer is connected to the Vin10 side, and when the value is “0”, the multiplexer is connected to the Vref side. Further, an output multiplexer MUXo is provided at the output of INV.
ut is connected, and MUXout has a sign bit s of the multiplier.
mul has been entered. When smul is “0”, that is, when the multiplier is positive, the first output Vou connected to SUM1
When t101 is selected and smul is “1”, SUM
2 is selected as the second output Vout2. This allows signed multiplication for the filter circuit.

Since the above filter circuit performs analog addition by capacitive coupling, the circuit scale is significantly reduced as compared with the case of digital processing, and the processing speed is high because of parallel addition. Further, since all the inputs and outputs of the sample and hold circuit and the addition circuit are voltage signals, current consumption is small and power consumption is small.

In the above embodiment, the configuration of double sampling has been described. However, by providing a larger number of sample-hold circuits and performing higher-speed switching corresponding thereto, it is possible to cope with higher-order oversampling. It goes without saying that you get it.

[0032]

As described above, the filter circuit and the sample and hold circuit according to the present invention are divided into a plurality of sample and hold circuit groups, and one adder circuit is switched and used.
Since the data held in each sample and hold circuit group is added, oversampling is possible, and there is an excellent effect that it is smaller and consumes less power than in the past.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a filter circuit according to the present invention.

FIG. 2 is a circuit diagram showing a sample hold circuit in the embodiment.

FIG. 3 is a circuit diagram showing a switch in FIG. 3;

FIG. 4 is a circuit diagram showing a first-stage multiplexer in FIG. 1;

FIG. 5 is a circuit diagram showing a second-stage multiplexer in FIG. 1;

FIG. 6 is a circuit diagram showing an adding circuit in FIG. 1;

FIG. 7 is a circuit diagram showing a subtraction circuit in FIG. 1;

FIG. 8 is a timing chart showing a relationship between signals CLK1 to CLK4 in FIG. 1;

FIG. 9 is a block diagram showing a second embodiment of the present invention.

FIG. 10 is a circuit diagram showing a multiplication circuit according to the embodiment.

FIG. 11 is a timing chart showing a mutual relationship between signals when three sample / hold circuit groups exist.

[Explanation of symbols]

G1, G2. . . Group SH11 to SH1n, SH21 to SH2n. . . Sample and hold circuits MUX11-MUX1n, MUX21-MUX2
n. . . Multiplexers SUM1, SUM2. . . Adder circuit SUB. . . Subtraction circuit PNG. . . PN registers C21 to C23, C61 to C6n, C6f, C6g, C
71 to C77. . . Capacitance SW. . . Switches I1, I2, I3, I4, I5, I61, I62, I6
3, I71, I72, I73, I74, I75, I76
. . . MOS inverters R21, R22, R61, R62, R71, R72
. . . Resistance T3, T41, T42. . . The transistor circuit Vref. . . Reference voltage generation circuits CLK1 to CLK4. . . Clock Vin. . . The output voltage Vout. . . Input voltage. 15 Reference number = YZ19707037A

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[Procedure amendment]

[Submission date] September 9, 1997

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG.

FIG. 7

FIG. 8

FIG. 9

FIG. 10

FIG. 11

Claims (7)

[Claims] A plurality of sample-hold circuits connected to an analog input voltage and having a plurality of sample-hold circuits for holding the analog input voltage in time series;
The corresponding sample and
A plurality of first multiplexers provided corresponding to the hold circuits and receiving the outputs of the corresponding sample / hold circuits of all the sample / hold circuit groups, wherein only the output of any one of the sample / hold circuit groups is provided A first multiplexer that outputs a positive multiplication result and a second output that outputs a negative multiplication result. A shift register in which a multiplier to be multiplied by the analog input voltage is stored in correspondence with the multiplication circuit;
A first adder circuit for calculating the sum of one output; a second adder circuit for the multiplication circuit
A second adder circuit for calculating the sum of outputs; and a subtractor circuit for subtracting the output of the second adder circuit from the output of the first adder circuit. The sample and hold circuit group cyclically converts the analog input voltage in the same cycle. A filter circuit which is controlled so as to take in, and wherein the first multiplexer is controlled in accordance with the control of the sample and hold circuit. 2. The multiplying circuit is a second multiplexer having a first output and a second output. The second multiplexer has its output switched and controlled by a corresponding PN code, and the sample and hold circuit group cyclically operates in the same cycle. 2. The filter circuit according to claim 1, wherein the filter circuit is controlled so as to receive an analog input voltage, and wherein the first multiplexer is controlled corresponding to the control of the sample and hold circuit. 3. The number of sample and hold circuit groups is m,
Let the sampling period of each sample and hold circuit group be t
s When the clock for sampling the first sample-hold circuit group is CLK (t), the clock for sampling the i-th sample-hold circuit group is And the control signal of the first multiplexer is ts
The sample / hold circuit group is sequentially selected alternately at a period of / m, and the control signal of the shift register is the same clock as the clock of any one of the sample / hold circuit groups. Item 3. The filter circuit according to item 1 or 2. 4. The sample and hold circuit comprises: a switch connected to an input voltage; a first capacitance connected to an output of the switch; and an odd-numbered stage CMOS inverter connected to an output of the first capacitance. A first inverting amplifier; a first feedback capacitance connecting an output of the first inverting amplifier to an input; a first multiplexer and a multiplying circuit for selectively outputting an output of the first inverting amplifier or a reference voltage; And a sample-and-hold circuit comprising:
The filter circuit as described. 5. A first adder circuit comprising: a plurality of second capacitances connected to a first output of each multiplication circuit; and an odd-numbered stage CMOS inverter connected while integrating the outputs of the second capacitances. A second inverting amplifying unit; and a second feedback capacitance connecting an output of the second inverting amplifying unit to an input. The second adding circuit includes: a plurality of third capacitances connected to a second output of each of the multiplying circuits. A third inverting amplifier comprising odd-numbered stages of CMOS inverters connected together while integrating the outputs of the third capacitances; and a third feedback capacitance for connecting the output of the third inverting amplifier to the input. 3. The filter circuit according to claim 1, wherein: 6. The subtraction circuit includes: a fourth capacitance connected to an output of the first addition circuit; a fourth inverting amplifier including an odd-numbered stage CMOS inverter connected to an output of the fourth capacitance; A fourth feedback capacitance connecting the output of the four inverting amplifier to the input; a fifth capacitance connected to the output of the second adding circuit; a sixth capacitance connecting the output of the fourth inverting amplifier; A fifth inverting amplifying section comprising an odd-numbered stage CMOS inverter in which outputs of the fifth and sixth capacitances are connected while being integrated; and a fifth feedback capacitance for connecting an output of the fifth inverting amplifying section to an input. 3. The filter circuit according to claim 1, wherein: 7. A multiplying circuit comprising: a capacitive coupling that integrates the outputs of a plurality of input capacitances having a capacity corresponding to the weight of each bit of a binary number; and a CMOS inverter in an odd-numbered stage connected to the output of the capacitive coupling. An inverter circuit; a feedback capacitor connecting an output of the inverter circuit to an input; a two-input one-output multiplexer connected to an input of the input capacitance;
A 1-input 2-output sign multiplexer connected to the output of the inverter circuit; a first multiplexer output connected to a first input of the multiplication multiplexer;
A voltage equal to the threshold voltage of the inverter circuit is connected to the second input, each bit of the binary multiplier is input to the multiplication multiplexer as a control signal, and the code bit of the multiplier is controlled to the code multiplexer. 2. The filter circuit according to claim 1, wherein the signal is input as a signal.