JPH11239056A - Pll oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce floor noise and to improve C/N. SOLUTION: A voltage-controlled oscillator(VCO) 18 has 1st and 2nd input terminals 16 and 17. A 1st error signal corresponding to the phase difference between a reference signal Fr and an output signal of a frequency dividing circuit 20 is inputted to the terminal 16. An output signal of the VCO 18 and the signal Fr are inputted to a mixer 22. Frequency components that meet an N=K condition make beat among themselves with an output frequency (=N/Fr) of the VCO 18 because harmonic (=K/Fr) is generated in the reference signal due to the non-linear characteristic of the mixer 22. An LPF 24 extracts a frequency component that is acquired by making the beat and supplies it as a 2nd error signal to the terminal 17. When a phase lock owing to the 1st error signal becomes stable, a switch 26 is controlled in such a manner that the 2nd error signal is supplied to the 2nd input terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL oscillation circuit, and more particularly to a PLL oscillation circuit capable of realizing a high C / N ratio.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an example of a general PLL oscillation circuit. A crystal oscillator is used for the reference signal generation circuit 10 and oscillates with high accuracy. The frequency dividing circuit 20
Frequency F of output signal of voltage controlled oscillator (VCO) 18
Divide o. The frequency of the frequency-divided signal (hereinafter referred to as comparison frequency) Fp is compared with the frequency of the reference signal (hereinafter referred to as reference frequency) Fr by the phase comparison circuit 12. The phase comparison circuit 12 includes a reference frequency Fr and a comparison frequency Fp.
And outputs a signal having a frequency component corresponding to the phase difference. The low-pass filter 14 compensates the loop phase by cutting a high frequency component of the output signal of the phase comparison circuit 12, and a signal corresponding to a phase difference between the reference frequency Fr and the comparison frequency Fp (hereinafter, referred to as an error signal). ). In addition, the low-pass filter (LPF) 14
As shown in the figure, it is often constituted by an integrating circuit using an amplifier. The frequency Fo of the output signal of the VCO 18 is controlled by the error signal output from the low-pass filter 14 so that the reference frequency Fr and the comparison frequency Fp have the same frequency and phase.

The frequency dividing circuit 20 often uses a program counter capable of arbitrarily setting a frequency dividing ratio N. The frequency dividing ratio N is controlled by, for example, a CPU (microprocessor, not shown) or the like. change. As a result, the output frequency Fo has the frequency Fr of the reference signal as the minimum step, and is N times the reference frequency Fr.

FIG. 8 is a frequency Fo distribution diagram of an output signal when a voltage controlled oscillator (VCO) is adjusted to oscillate at a frequency fo without a phase locked loop (PLL). It can be seen that even if the frequency is adjusted to oscillate at the frequency fo, the frequency component is not only fo but also other frequency components are generated.

FIG. 9 shows a frequency distribution of an output signal of an oscillation circuit using a PLL as shown in FIG. Compared to FIG. 8, it can be seen that the fluctuation of the frequency is reduced. That is, other frequency components are reduced as compared with the desired frequency fo component, and the C / N ratio is improved.

[0006]

By using a phase locked loop as shown in FIG. 9, the C / N ratio of the oscillation circuit is improved. Conventionally, the gain of the phase locked loop has been increased to further increase the C / N ratio. However, even with this, the frequency component of the floor noise could not be reduced. This is because floor noise is caused by noise generated in the phase comparator 12, the LPF 14, the frequency divider 20, and the like.

[0007]

In the PLL oscillation circuit according to the present invention, the voltage controlled oscillation means has first and second input terminals, which respectively receive a control signal and control the oscillation frequency of the output signal. . The reference signal generating means is, for example,
A reference signal having a reference frequency is generated from a crystal oscillator or the like. The frequency divider divides the frequency of the output signal of the voltage controlled oscillator according to a frequency division ratio that can be changed by control of the CPU or the like. The first error signal generating means includes a well-known circuit such as a phase comparison circuit and a low-pass filter, and generates a first error signal corresponding to a phase difference between output signals of the reference signal generating means and the frequency dividing means. The voltage is supplied to a first input terminal of the voltage controlled oscillator. The second error signal generating means includes a multiplying means and a filter means. At this time, the multiplication means multiplies the output signal of the voltage controlled oscillation means by the reference signal, and the filter means passes a desired frequency component in the output signal of the multiplication means and supplies the same as a second error signal. The switch supplies the second error signal to the second input terminal when the phase lock by the first error signal is stabilized.

By the way, the desired frequency component in the output signal of the multiplying means passed by the filter means is generated by multiplying the output signal of the voltage controlled oscillating means and the harmonic component of the reference signal, that is, beats. It is a frequency component. That is, the filter unit extracts a signal having a frequency corresponding to the phase difference between these signals as the second error signal.

As the multiplying means, for example, a mixer for mixing the output signal of the voltage controlled oscillating means and the reference signal is used.
More specifically, the mixer has a double balanced
It is good to use what is generally used widely, such as a mixer (DBM). Such a general mixer generates harmonics due to its non-linear characteristics.
In the present invention, such non-linear characteristics are rather positively used, and a frequency (= N) of the reference frequency Fr (where N is a frequency division ratio) is used.
N · Fr) is multiplied by a harmonic (= K · Fr) of the reference signal and a component (= desired frequency component) obtained by beating N = K frequencies. It is taken out by the filter means and used for phase lock.

As the second error signal generating means, a sampling means may be used instead of the above-mentioned configuration. At this time, the sampling means samples the output signal of the voltage controlled oscillation means using the reference frequency of the reference signal as a clock. Then, the output signal of the voltage controlled oscillator is sampled at a frequency much lower than twice that frequency, so that an aliasing phenomenon always occurs. At this time, if there is no phase difference between the reference signal and the output signal of the voltage controlled oscillator, the sampling means samples the point where the voltage of the output signal of the voltage controlled oscillator is zero V every time. However, if there is a phase difference between these signals, a point at which the voltage of the output signal of the voltage controlled oscillator deviates from the point of zero volts is sampled each time. This voltage is supplied to the second input terminal of the voltage controlled oscillator as a second error signal. As a result, the voltage-controlled oscillation means is controlled so that its output frequency is set to zero the voltage of the second error signal.

The voltage controlled oscillator has an amplifying means and a loop for applying a positive feedback to the amplifying means, and first and second variable capacitors for changing the impedance are provided on the loop. The first and second variable capacitance capacitors change their capacitances by receiving the first and second error signals, respectively, and as a result, change the impedance of the loop. At this time, it is preferable that the variable capacitance ranges of the first and second variable capacitance capacitors are set to differ by at least 10 times or more. Thereby, the oscillation frequency of the PLL oscillation circuit in a large range is determined by the change in the capacitance of the first variable capacitor that has received the first error signal, and subsequently, the oscillation frequency of the second variable capacitor that has received the second error signal is determined by the change in capacitance. In addition, the oscillation frequency of the PLL oscillation circuit can be driven to a desired frequency with higher accuracy. As a result, a PLL oscillation circuit having a high C / N ratio and suppressing occurrence of floor noise can be realized.

[0012]

FIG. 1 is a functional block diagram showing an example of a preferred embodiment of the present invention. Components corresponding to those in FIG. 7 are described with the same reference numerals. At this time, one of the significant differences from the circuit shown in FIG. 7 is that the voltage controlled oscillation circuit (VCO) 18 has two control voltage input terminals. That is, the VCO 18 is provided with the first and second input terminals 16 and 17. This also results in two phase locked loops.

The first loop includes the VCO 18 and the frequency divider 2
0, the phase comparison circuit 12 and the low-pass filter (LP
F) 14 and its function is almost the same as that of the conventional circuit shown in FIG. Note that the phase comparison circuit 12 and the low-pass filter LPF 14 function as first error signal generation means 15. The second loop is a VCO 18, a mixer 2
2. It is composed of a low-pass filter 24 and a switch 26. The mixer 22 and the low-pass filter 24
Functions as the second error signal generating means 25. VCO
The 18 first and second input terminals 16 and 17 receive control voltages (first and second error signals to be described later) from the first and second loops, respectively, and thereby control the output frequency Fo of the VCO 18.

FIG. 2 is a circuit diagram of an example of a preferred embodiment of the voltage controlled oscillator (VCO) 18 according to the present invention. The VCO 18 oscillates by providing a positive feedback loop in the amplifier circuit 28. On this loop, first and second variable capacitance diodes (varicaps) D1 and D2 for changing impedance are provided. The output signal frequency of the VCO 18 is controlled by changing the voltage between both ends of the first and second variable capacitance diodes D1 and D2 to change the capacitance of these diodes. At this time, the voltage between both ends of the first and second variable capacitance diodes D1 and D2 is
The first and second input terminals 16 and 1 of the VCO 18 respectively
7 is controlled by the voltage applied.

The variable capacitance range of the first and second variable capacitance diodes D1 and D2 is, for example, 1000: 1
It should be about. By doing so, the oscillation frequency of the VCO 18 can be determined by the voltage applied to the first input terminal 16 in a large range, and determined by the voltage applied to the second input terminal 17 in a small range.

Referring again to FIG. 1, the output signal of the VCO 18 and the reference signal are input to the mixer 22 and multiplied. As the mixer 22, for example, a double balanced mixer (DBM) is preferably used. DBM
Is widely used at present because it is configured using a plurality of diodes and can achieve high performance relatively easily.

The diode of the mixer 22 has a non-linear characteristic. Therefore, a harmonic is generated in the reference signal input to the mixer 22. That is, a component of a frequency (K · Fr) that is an integer (K) times the frequency Fr of the reference signal is generated. On the other hand, the output frequency Fo of the VCO 18 is N times the reference frequency Fr (N is the frequency division ratio), that is, the frequency of N · Fr. Therefore, the output frequency Fo of the VCO 18 is a harmonic (K) of a plurality of reference frequencies Fr.
(Including the case where is 1).

At this time, the harmonic K of the reference frequency K = N
If there is a phase difference between Fr and the output frequency Fo of the VCO 18, the output signal Fb of the mixer 22 has a frequency component several orders of magnitude lower than the reference frequency Fr according to this phase difference. The low-pass filter (LPF) 24 is provided to extract only a relatively low frequency component obtained by beating the harmonic K · Fr of the reference frequency K = N and the output frequency Fo of the VCO 18. The output signal of the LPF 24 is used as a second error signal F2 as described later. The LPF 24 may be set, for example, so as to pass only frequencies that are about 1/1000 or less of the reference frequency. Thus, the mixer 22 and the filter 24 function as the second error signal generation unit 25.

The on / off of the switch 26 is controlled by a CPU (microprocessor, not shown) to open and close the second loop. Furthermore, the second loop is the first loop
It is controlled to close after the phase lock of the loop is completed. This control will be described later.

FIG. 3 is a graph showing the frequency characteristics of the first and second error signals F1 and F2 theoretically applied to the first and second input terminals of the VCO 18 with respect to the output frequency Fo of the VCO 18. 4 and 5 are partial enlarged views of FIG. FIG. 4 shows that the frequency of the output signal of the VCO 18 is fo
FIG. 4 is an enlarged view of a frequency characteristic of a first error signal F1 applied to a first input terminal 16 when the frequency is. FIG. 5 is an enlarged view of the frequency characteristic of the second error signal F2 applied to the second input terminal 17 when the output frequency Fo is fo. Note that the frequency fo is the output frequency Fo of the VCO 18.
, Ie, N times the reference frequency Fr (N
Is the frequency of the frequency dividing circuit 20).

Referring to FIG. 4, the first error signal F1 is
When the output frequency of the VCO is at the desired frequency fo, the phase lock of the first loop is performed, and ideally, it should stabilize at the voltage V1 and stabilize by drawing the line Lo. But,
Actually, due to the floor noise, the signal fluctuates between the lines L1 and L2, so that the output frequency Fo of the VCO 18 cannot be made only the desired frequency fo component, and d
It fluctuates in the width of f.

After the phase of the first loop is locked, the switch 26 is closed, and the phase lock by the second loop functions. At this time, the second loop sets the second error signal F2 to 0.
It works in the direction of (zero) V, so that the frequency variation width df
And reduce the occurrence of frequency components other than the desired frequency fo (see FIG. 5). That is, the C / N ratio of the output frequency Fo of the VCO 18 is improved.

The reason why the second loop is closed by closing the switch 26 after the phase lock of the first loop will be described. When the second loop is closed and functions, the second error signal F2 applied to the second input terminal of the VCO 18 from the second loop is controlled to become 0 (zero) V. However, the second error signal F2 has a point at which the voltage becomes 0 V at various frequencies as shown in FIG. Therefore, the second
If the loop is not closed in an appropriate state, the output frequency Fo of the VCO 18 will function to be phase-locked at a frequency other than the desired frequency fo. Therefore, the first loop is locked, and after the output frequency of the VCO 18 falls within the fluctuation range df near fo, the second loop is closed to enable effective phase lock. Become.

In order to control the ON / OFF of the switch 26, it is necessary to detect whether or not the first loop has entered the phase locked state. To do this, the output signal Fd of the phase comparison circuit 12 is converted into digital data by an analog-to-digital converter (A / D) 21 and the microprocessor (CP)
U) or other control means (not shown). When the microprocessor (control means) determines that the first loop has entered the phase locked state, it turns on the switch 26 to close the second loop.

In FIG. 1, the mixer 22 and the filter 24 are used to generate the second error signal, but sampling means may be used instead. FIG. 6 is a functional block diagram of the sampling means used as the second error signal generating means 25. Output signal Fo of VCO18
Are sampled by the sampling circuit 30 using the reference frequency Fr as a clock. The hold circuit 32 holds and outputs the voltage at the sample point obtained by the sampling circuit 30 until the next sample point.

At this time, the reference frequency Fr is 1 / N of the frequency of the output signal of the voltage controlled oscillator, that is, a frequency much lower than twice. Therefore, the reference frequency Fr
, The aliasing phenomenon always occurs. If there is no phase difference between the reference frequency Fr and the output signal of the VCO 18, the sampling circuit 30
The point where the voltage of the output signal 18 is zero V is sampled every time. However, if there is a phase difference between these signals, a position where the voltage of the output signal of the VCO 18 deviates from the point of zero V is sampled every time, and a voltage corresponding to the phase difference is obtained from the hold circuit 32. This is supplied to the second input terminal of the voltage controlled oscillator as a second error signal. As a result, the second phase lock loop controls the output frequency of the VCO so that the output voltage (second error signal) of the hold circuit 32 becomes zero volt.

As described above, in the present invention, in addition to the phase lock by the first loop, which is the same as the conventional phase lock loop, a frequency component of a small range which cannot be controlled by itself is phase-locked in the second loop. Lock it. As a result, an effective phase lock is realized, so that a PLL oscillation circuit having a higher C / N ratio than before can be realized.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of an example of an embodiment of a PLL oscillation circuit according to the present invention.

FIG. 2 is a circuit diagram of an example of a preferred embodiment of a voltage-controlled oscillation circuit according to the present invention.

FIG. 3 shows first and second output frequencies Fo of a VCO.
5 is a graph illustrating frequency characteristics of error signals F1 and F2.

FIG. 4 shows a first example when the frequency of the output signal of the VCO is fo.
It is an enlarged view of the frequency characteristic of error signal F1.

FIG. 5 shows a second example when the frequency of the output signal of the VCO is fo.
It is an enlarged view of the frequency characteristic of error signal F2.

FIG. 6 is a functional block diagram of a sampling unit used as a second error signal generation unit.

FIG. 7 is a block diagram of an example of a conventional general PLL oscillation circuit.

FIG. 8 is a frequency distribution diagram of an output signal when the voltage controlled oscillation circuit is adjusted to oscillate at a frequency fo without a phase locked loop.

FIG. 9 shows a frequency distribution of an output signal in a conventional PLL oscillation circuit.

[Explanation of symbols]

 Reference Signs List 10 Reference signal generation circuit 12 Phase comparison circuit 14 Low-pass filter 15 First error signal generation means 16 First input terminal 17 Second input terminal 20 Divider circuit 22 Mixer 24 Low-pass filter 25 Second error signal generation means 26 Switch 28 Amplification circuit 30 Sampling circuit 32 Hold circuit D1 First variable capacitance diode D2 Second variable capacitance diode Fo Output frequency of VCO fo Desired output frequency of VCO Fp Comparison frequency Fr Reference frequency F1 First error signal F2 Second error signal Lo Ideal line L1 line L2 line df Frequency fluctuation range N Division ratio K Order of harmonics of reference signal

Claims (5)

[Claims] 1. A voltage controlled oscillator having first and second input terminals, a reference signal generator for generating a reference signal having a reference frequency, and a frequency divider for dividing an output signal of the voltage controlled oscillator. And a first error signal generating means for generating a first error signal corresponding to a phase difference between output signals of the reference signal generating means and the frequency dividing means and supplying the first error signal to the first input terminal of the voltage controlled oscillating means. A multiplying means for multiplying the output signal of the voltage-controlled oscillating means and the reference signal, and a filter means for passing a desired frequency component in the output signal of the multiplying means and supplying it as a second error signal. A PLL oscillation circuit comprising: an error signal generating unit; and a switch unit that supplies the second error signal to the second input terminal when the phase lock by the first error signal is stabilized. 2. The method according to claim 1, wherein the second error signal output from the filter means is a frequency component generated by beating an output signal of the voltage controlled oscillator and a harmonic component of the reference signal. The PLL oscillation circuit according to claim 1, wherein 3. The PLL oscillation circuit according to claim 1, wherein said multiplication means is a mixer for mixing an output signal of said voltage controlled oscillation means and said reference signal. 4. A voltage controlled oscillating means having first and second input terminals, a reference signal generating means for generating a reference signal having a reference frequency, and a frequency dividing means for dividing an output signal of the voltage controlled oscillating means. And a first error signal generating means for generating a first error signal corresponding to a phase difference between output signals of the reference signal generating means and the frequency dividing means and supplying the first error signal to the first input terminal of the voltage controlled oscillating means. A second error signal generating unit that samples an output signal of the voltage controlled oscillation unit at the reference frequency and supplies the second error signal as a second error signal; A switching circuit for supplying a signal to the second input terminal. 5. The voltage controlled oscillating means includes: an amplifying means; a loop for applying a positive feedback to the amplifying means; and a first and a second means for receiving the first and second error signals, respectively, and changing an impedance of the loop. 5. The PLL oscillation circuit according to claim 1, further comprising a second variable capacitor, wherein the variable capacitance ranges of the first and second variable capacitors differ by at least 10 times or more.