JPH11233974A - Electronic circuit package and its erroneous mounting protecting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect an electronic circuit from artificial mistakes, by providing one or two or more electronic circuits which are connected between feeding terminals and the output signals of which are energized or de-energized, in accordance with control signal which copes with the propriety of the mounting state of its own package, by discriminating the mounting state of a substrate based on the level of a signal inputted through another prescribed terminal. SOLUTION: When a substrate 10 is inserted into a back plate 20 and the power supply to a device is raised, power supply +V and GND are supplied to a board 10 through terminals P1 and P21. Consequently, an electronic circuit section 13 is fed with the electric power, and electronic circuits are simultaneously activated. However, the output signal of a decoder 14 is inputted to the gate terminals G1-Gn of buffer circuits BF1-BFn. The outputs of the buffer circuit BF1-BFn are restricted by the propriety of the mounting state of the substrate 10. Each buffer circuit BF1-BFn will not also give damages to the output circuit of other boards. Therefore, the erroneous mounting state of the board 10 can be coped quickly, by having the state recognized based on the signal of the decoder 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an electronic circuit package and an erroneous mounting protection method thereof. For example, in a transmission device, a computer device, or the like, a large number of electronic circuit packages (substrates) having the same shape and different functions are mounted in slots having a frame structure. For this reason, at the time of installation or maintenance of the apparatus, it is not uncommon for the power to be turned on while the packages and the cables connecting the packages are erroneously mounted, and there is a high possibility that the packages will be broken if left unattended.

[0002]

2. Description of the Related Art Conventionally, a so-called erroneous insertion prevention key has been provided exclusively to mechanically prevent erroneous insertion of a substrate. However, providing a wrong insertion prevention key for each board or for each cable connector is complicated in manufacturing and management, and leads to an increase in the cost of the apparatus. For this reason, many devices are not provided with an erroneous insertion prevention key.

[0003]

As a result, during installation or maintenance of the apparatus, it is not uncommon for the power to be turned on while the packages and cables are incorrectly mounted. At that time, output signals between the packages collide, Often the signal output circuit was destroyed. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an electronic circuit package capable of effectively protecting an electronic circuit from human error, and an erroneous mounting protection method thereof.

[0004]

The above-mentioned problem is solved, for example, by referring to FIG.
Is solved. That is, the electronic circuit package 10 of the present invention (1) is adapted to determine whether or not the mounting state of the package itself is based on a power supply terminal and a signal level connected between the power supply terminals and input via another predetermined terminal. It comprises a mounting state discriminating unit for discriminating the absence and outputting a corresponding control signal, and one or more electronic circuits for energizing / deactivating a circuit output signal in accordance with the control signal.

According to the present invention (1), when the package 10 is erroneously mounted on, for example, the backplane 20, the output signal of the electronic circuit is deactivated by the control signal of the output of the mounting state discriminator detecting this. Therefore, it does not collide with the output signal of the electronic circuit of another package. Alternatively, although not shown, in the case where a signal cable from another package is erroneously mounted on the package 10, for example, the output signal of the electronic circuit is deactivated by the control signal of the output of the mounting state determination unit which has detected the signal cable. There is no collision with the output signal of the electronic circuit of another package. Therefore, the electronic circuit can be effectively protected from human error.

Further, the electronic circuit package 10 of the present invention (2) has a mounting state related to its own package based on a power supply terminal and a signal level connected between the power supply terminals and input through another predetermined terminal. Mounting state determining unit that determines whether or not the power supply is appropriate and outputs a corresponding control signal; switch means for turning on / off power supply in accordance with the control signal; and one or more electronic devices supplied via the switch means And a circuit.

According to the present invention (2), even if there is a human error in mounting the package or the signal cable, power is not supplied to the electronic circuit of the package, so that the electronic circuit can be effectively protected. Preferably, in the present invention (3), in the present invention (2), the electronic circuit is a circuit that outputs a signal to a signal output terminal of the package.

According to the third aspect of the present invention, the power supply to the electronic circuit that outputs a signal to at least the signal output terminal of the package is limited, so that the power supply switch with a small capacity can effectively use the electronic circuit from human error. Can be protected. Also preferably, in the present invention (4), in the above present inventions (1) to (3), the mounting state judging section detects the mounting state of the own package based on each signal level inputted through a plurality of terminals. It is composed of a decoder circuit for judging suitability or not and outputting a corresponding control signal. Therefore, many mounting states can be identified by a simple decoder circuit.

[0009] Preferably, in the present invention (5), in the above inventions (1) to (3), the mounting state judging section is configured to mount on the own package based on a signal level inputted through one terminal. It comprises a level detection circuit for judging the suitability of the state and outputting a corresponding control signal. Therefore, the number of signals (the number of board terminals) for determining the suitability of the mounting state can be reduced, and the remaining board terminals can be used effectively.

Further, according to the present invention (6), the erroneous mounting protection method for an electronic circuit package is the same as the erroneous mounting protection method for an electronic circuit package of an apparatus in which a plurality of electronic circuit packages are mounted in a slot having a frame structure. ID of
A plurality of monitored packages that hold information, and a table that associates respective identification ID information and slot position information to be implemented with respect to each of the monitored packages is held, and between the monitored packages. And a monitoring package for performing data communication, wherein the monitoring package includes:
Collecting respective identification ID information from the monitored package at each mounting position, comparing these with the information in the table, and controlling to activate the output signal of the monitored package for which a comparison match is obtained. It is.

In the present invention (6), the monitoring package holds a table in which the identification ID information and the slot position information to be mounted are associated with each monitored package. Assuming that a monitored package is mounted in a certain slot, the identification ID information is obtained from the monitored package in the slot and compared with the information in the table. In this case, if a comparison match is obtained, an appropriate monitored package is mounted in the slot, and the output signal of the monitored package is energized (or power is supplied to the electronic circuit unit). Remote control to do so. If no match is found,
Another monitored package is erroneously mounted in the slot, so that the output signal of the monitored package is not activated. Therefore, the electronic circuit can be effectively protected from human error.

In this case, according to the present invention (6), it is possible to flexibly cope with an apparatus having any board configuration only by changing the information in the table, so that a very versatile mis-mounting protection system is constructed. it can.

[0013]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 2 is a view for explaining an electronic circuit package (substrate) according to the first embodiment. FIG. 2A shows the relationship between the structure of the substrate and the backplane on which the substrate is mounted.

In the drawing, 10 is a board, 11 is its connector terminal, 12 is an electronic circuit, 13 is an output circuit, and BF
Is a buffer circuit, 14 is a decoder (DEC), 20 is a backplane, and 21 is its connector terminal. In the backplane 20, + V is supplied to the terminal P1, and GND is supplied to the terminal P21 from a device power supply (not shown). The terminals P17 to P19 are connected to the backplane 20.
In this example, they are connected to terminals P17 and P19 = 1 (high level H) and terminal P18 = 0 (low level L) in the backplane.

This connection corresponds to the slot address SAD = 5, as shown in FIG. The coding of each slot address SAD of the backplane 20 is different for each slot. In this example, each terminal P1 is a binary code corresponding to the slot address SAD = 0 to 7.
The signal levels of H and L (+ V, GND) are added to 7 to P19. If necessary, the slot address SAD
After = 8, the binary codes are sorted in the same or reverse order as described above. This saves the number of address terminals and
This is an example of an arrangement in consideration of the fact that erroneous mounting of a board is unlikely to occur between distant slots.

Returning to FIG. 2A, this substrate 10 shows the circuit configuration of a substrate to be inserted at slot address SAD = 5. Here, the electronic circuit section 12 includes electronic circuits having various functions of an analog system and a digital system. The output circuit unit 13 is included in a part of the electronic circuit unit 12, and includes a plurality of electronic circuits (for example, buffer circuits BF1 to BF) that output signals to output terminals of the substrate 10.
n). The buffer circuits BF1 to BFn
It has a 3-state output mode, and the gate terminal G =
When it is 1 (high level), its output is kept at high impedance. When the gate terminal G = 0 (low level), its output signal is high / low according to the high / low level of the input signal. Driven to low level. The decoder 14 is composed of, for example, a three-input NAND gate circuit. In this example, when the upper and lower two input terminals are at a high level and the central one input terminal is at a low level, the output thereof is at a low level. For other inputs, the output goes high. Needless to say, a decoder 14 having a different decoding method is used for each substrate.

With this configuration, when the substrate 10 is inserted into the back plane 20 and the power of the device is increased, the terminals P1 and P
Power supply + V, GND is supplied to the substrate 10 via 21. As a result, power is simultaneously supplied to the electronic circuit unit 12 and the output circuit unit 13, and each electronic circuit is activated. However, the output signals of the decoder 14 are input to the gate terminals G1 to Gn of each of the buffer circuits BF1 to BFn, whereby the output of each of the buffer circuits BF1 to BFn is limited by the appropriateness of the mounting state of the substrate 10. Will be.

That is, as shown in FIG.
The board 10 to be inserted at D = 5 is the slot address S
When AD = 5, the output signal of the decoder 14 becomes 0, and each of the buffer circuits BF1 to BFn outputs an output signal corresponding to the input signal. This is because the output signal of the board 10 properly inserted does not collide with the output signals of other boards. However, if the board 10 to be inserted at the slot address SAD = 5 is erroneously inserted at the adjacent slot address SAD = 6, for example, the decoder 1
4 becomes 1 and each of the buffer circuits BF1 to BF
The outputs of n simultaneously become high impedance. Therefore,
In this case, each of the buffer circuits BF1 to BFn does not damage the output circuit of another substrate, nor does its own output circuit be damaged. Therefore, damage to the output circuit due to erroneous mounting of the board can be effectively prevented.

Although not shown, the circuit may be configured so that, for example, a red photodiode is turned on based on the output signal of the decoder 14 = 1. In this way, the maintenance person can easily recognize that the board 10 is in an erroneous mounting state,
We can deal with it promptly. Further, instead of providing the decoder 14, a self-address setting holding unit such as a dip switch or a jumper circuit and a comparator are provided. When the slot address SAD of the external input matches the self address, an output signal from the comparator is output. The circuit may be configured to output 0 and output the output signal = 1 from the comparator for other inputs. The above is also true for the following embodiments.

FIG. 3 is a view for explaining an electronic circuit package according to the second embodiment, and shows a case where power is not supplied to the output circuit section 13 of the board 10 which has been incorrectly mounted. FIG. 3 (A)
In the figure, 15 is a power supply switch section, and GA1 to GAn are gate circuits. The gate circuit 13 is AND, OR, EX
-It is composed of various gate circuits such as an OR, a buffer, and an inverter. Further, other flip-flop circuits, LSI elements, analog circuits, and the like may be included in the output circuit unit 13. In short, the output circuit section 13 can include all electronic circuits that output signals from the terminals of the substrate 10.

Various switch elements can be used for the power supply switch unit 15. FIG. 3B shows a relay circuit comprising a coil L and a relay contact, FIG. 3C shows a photocoupler comprising a photodiode PD and a phototransistor Q, and FIG.
(D) shows a power supply switch unit composed of a pMOSFET. In such a configuration, when the substrate 10 is inserted into the back plane 20 and the power of the device is increased, the power + V and GND are supplied to the substrate 10 via the terminals P1 and P21. Thereby, power is supplied to the electronic circuit unit 12 all at once, and each electronic circuit is activated. On the other hand, the output circuit unit 13
Is supplied via the power supply switch unit 15, whereby power supply to the output circuit unit 13 is restricted by the appropriateness of the mounting state of the substrate 10.

That is, as shown in FIG.
The board 10 to be inserted at D = 5 is the slot address S
When AD = 5, the power supply switch unit 15 is turned on by the output signal = 0 of the decoder 14, and power is also supplied to the output circuit unit 13 at the same time. However, when the substrate 10 to be inserted at the slot address SAD = 5 is erroneously inserted at the adjacent slot address SAD = 6, for example, the power supply switch unit 15 is turned off by the output signal = 1 of the decoder 14. The output circuit 13 is not supplied with power. Therefore, in this case, each of the gate circuits GA1 to GA1
GAn does not damage the output circuit of another substrate, nor does its own output circuit be damaged.

FIG. 4 is a view for explaining an electronic circuit package according to the third embodiment, and shows a case where power is not supplied to all electronic circuits except for the decoder 14 of the erroneously mounted substrate 10. In the figure, power is supplied to an electronic circuit unit 12 except a decoder 14 via a power supply switch 15, and the output circuit unit 1 which is a part of the electronic circuit unit 12 is provided.
3 includes various output circuits such as a gate circuit GA, a comparator CMP, and an operational amplifier OPA.

In such a configuration, when the substrate 10 is inserted into the backplane 20 and the power of the device is raised, the terminals P1 and P2
1 is supplied to the decoder 14 first.
Is activated. On the other hand, power is supplied to the electronic circuit unit 12 via the power supply switch unit 15, so that the power supply to the electronic circuit unit 12 is restricted by the appropriateness of the mounting state of the substrate 10.

That is, as shown in FIG.
The board 10 to be inserted at D = 5 is the slot address S
When AD = 5, the power supply switch unit 15 is turned on by the output signal = 0 of the decoder 14, and power is also supplied to the electronic circuit unit 12 at the same time. However, when the substrate 10 to be inserted at the slot address SAD = 5 is erroneously inserted at the adjacent slot address SAD = 6, for example, the power supply switch unit 15 is turned off by the output signal = 1 of the decoder 14. As a result, power is not supplied to the electronic circuit unit 12. Therefore, each output circuit in this case does not damage the output circuit of the other substrate, nor does its own output circuit be damaged.

FIGS. 5 and 6 are views (1) and (2) for explaining an electronic circuit package according to a fourth embodiment, showing a case where the slot address SAD is identified based on the signal level of a single terminal. I have. In FIG. 5A, a low level (GND) is applied to the terminal P5 of the backplane 20 from the terminal P21. As shown in FIG.
This indicates that the slot address SAD = 3. Which terminal of the backplane 20 is applied with the low level differs for each slot. In this example, the terminals P2 to P2 correspond to the slot addresses SAD = 0 to 4.
The low level is added to 6 in turn. If necessary, after the slot address SAD = 5, a low level is sequentially applied to each terminal in the same or reverse order. In this case, in order to avoid a low signal level output from another board from being mistakenly recognized as a slot address signal in the present board 10, preferably, the terminals P2 to P2 of each board 10 are used.
P6 is not used for signal input / output.

Returning to FIG. 5A, this substrate 10 shows the circuit configuration of a substrate to be inserted at slot address SAD = 3. Here, the terminal P5 and each buffer circuit BF1-
BFn are connected to gate terminals G1 to Gn, and this terminal P5 is connected to a terminal P1 (+ V
Side). This pull-up resistor R is a type of level detection circuit.

With this configuration, when the substrate 10 is inserted into the back plane 20 and the power supply of the device is raised, the electronic circuit unit 1
2 and the output circuit unit 13 are simultaneously supplied with power, and each electronic circuit is activated. However, each of the buffer circuits BF1 to BFn
The signal levels from the terminal P5 are input to the gate terminals G1 to Gn of the buffer circuits BF1 to Gn.
The signal output of BFn is restricted by the appropriateness of the mounting state of the board 10.

That is, as shown in FIG.
The substrate 10 to be inserted at D = 3 is the slot address S
When AD = 3 is inserted, the signal level from the terminal P5 becomes low, and each of the buffer circuits BF1 to BFn
Output an output signal corresponding to the input signal. However, when the substrate 10 to be inserted into the slot address SAD = 3 is erroneously inserted into the adjacent slot address SAD = 4, for example, the signal level from the terminal P5 becomes high due to the function of the pull-up resistor R. And the outputs of the buffer circuits BF1 to BFn all become high impedance at the same time.

Therefore, each buffer circuit BF1 in this case
BFn does not damage the output circuit of another substrate, nor does its own output circuit be damaged.
FIG. 6 shows a case where the wiring method of the slot address is different. That is, in this example, a low-level supply terminal P17 and its receiving terminal P5 are provided on the substrate 10 side,
On the other hand, on the back plane 20 side, wiring is provided so as to short-circuit the supply terminal P17 and the reception terminal P5. Also in this case, preferably, the terminals P2 to P6 and P16 to P20 of each substrate are connected to the low signal level output from another substrate in order to prevent the substrate 10 from being mistakenly recognized as a slot address signal. Not used for I / O.

According to the method shown in FIG. 6, various wiring patterns (slot addresses) can be realized by combining low-level supply terminals and their reception terminals. For example, if there are five low level supply terminals and five low level supply terminals as shown in the figure, a total of 25 types of slot addresses can be generated and identified. Although the case where the outputs of the buffer circuits BF1 to BFn are limited has been described above, it is apparent that the circuit may be configured to limit the power supply to the electronic circuit unit 12 or the output circuit unit 13.

FIG. 7 is a view for explaining an electronic circuit package according to the fifth embodiment, and shows an example of application to a case where a plurality of boards are connected not with the backplane 20 but with a flat cable or the like. . In the figure, 10 is a substrate,
12 is an electronic circuit unit, 16 is a connector provided on a board, 22
Is a flat cable, 23 is a connector provided on the flat cable, D is a driver circuit, and R is a receiver circuit.

Here, the flat cable 23 is connected to the substrate 1
The connection between the signals 0A and 10B can be considered in the same way as the backplane 20. However, since it is difficult to provide a signal source serving as a slot address on the flat cable 23 itself, a signal (connector address) corresponding to the slot address SAD is supplied from the connector 16 on the opposite substrate. Thus, in this example, the electronic circuit is protected from incorrect insertion of the cable, rather than incorrect insertion of the board.

Referring to FIG.
b and connector 23b and connector 16d and connector 23
and d are connected to each other. In this state, the connector 16d
Is applied to the gate terminal of the driver circuit D1 via the cable 22B via a specific terminal, whereby the driver circuit D1 can output an output signal. The same applies to the side of the cable 22A.

However, if the connector 23a of the cable 22A is erroneously connected to the connector 16b of the board 10A, the output lines of the driver circuits D1 and D2 collide, and the driver circuits D1 and D2 may be destroyed. Occurs. However, according to the fifth embodiment, even when such an erroneous connection is made, the low level is not provided from the connector 16c to the gate terminal of the driver circuit D1, and the gate terminal of the driver circuit D2 is not supplied from the connector 16b. Is not provided with a low level. Therefore, no output signal is output from both driver circuits D1 and D2, and both driver circuits D1 and D2 are not damaged.

The connector address can be displayed by a coding method using a plurality of signal lines. The connector address can be displayed bidirectionally from both boards for one cable. Further, the circuit may be configured to limit the power supply to the electronic circuit unit 12 and the output circuit unit 13 based on the determination of the incorrect insertion of the connector. FIGS. 8 to 10 are diagrams (1) to (4) for explaining an erroneous mounting protection method for an electronic circuit package according to the embodiment, in which a monitoring board inserted into a specific slot of a frame structure is used for monitoring a plurality of other monitored boards. This figure shows a case where erroneous mounting protection control of a board is performed in a concentrated manner.

FIG. 8 shows a front view of the back plane 20. The monitoring board 30 is, for example, slot 0 of column # 0.
And the other plurality of monitored substrates 40 are inserted into the remaining slots of columns # 0 and # 1. Although not shown, columns # 2 and subsequent columns may be present. + V is supplied to the terminal P1 of the backplane 20, GND is supplied to the terminal P13, and the terminal P10 of each slot is supplied.
... P12 are each coded with a unique slot address SAD. A terminal P9 in each slot is used as a terminal for performing serial data communication between the monitoring board 30 and each monitored board 40.

FIG. 9 shows the circuit configuration of the monitoring board and the monitored board. In the figure, 30 is a monitoring board, 31 is an electronic circuit unit, 32 is a CPU that performs monitoring control, and 33 is a CPU.
32 and the monitoring control process of FIG.
Main memory (M
M) and 34 are communication interfaces (CIF) for performing data communication with the monitored board 40, 35 is a switch unit (SW) for switching communication lines, and 36 is a CPU 32.
40, a monitored board; 41, an electronic circuit unit for realizing the original functions of the monitored board (various functions of the transmission device, etc.); 42, a monitored control unit that is in charge of monitored control;
3 holds the identification ID information of the monitored board, and
A control unit 44 that implements one monitored control process is a communication interface (CIF) for communicating with the monitoring board 30.

The monitoring board 30 satisfies the decoder 14 when properly mounted, and is supplied with power by itself through the power supply switch unit 15. On the other hand, in each monitored board 40, only the monitored control unit 42 required for communication control is unconditionally supplied with power, and power is supplied to the electronic circuit unit 41 by remote control from the monitoring board 30 via the control unit 43. The controller 43 is supplied with the slot address S supplied from the terminals P10 to P12.
AD is input as data and is used as address information at the time of data communication with the monitoring board 30.

FIG. 10A shows the storage structure of the board mounting table. The board mounting table has a non-monitoring board 4 of any identification ID at a position specified by a column and a slot.
It is stored in advance whether 0 should be implemented. However, since the monitoring board 30 is mounted in the slot 0 of the column # 0, the information of this area is not known.
In the figure, for example, ID # is assigned to slot 3 of column # 0.
It is stored that the monitored board 07 should be mounted, the monitored board with ID # 10 should be mounted in slot 4, and the monitored board with ID # 03 should be mounted in slot 5. The same applies to other columns. The column in which the identification ID is not stored indicates that the monitored board 40 does not need to be mounted in this slot.

FIG. 10B shows the format of a communication frame exchanged between the monitoring board 30 and the monitored board 40. Here, the “start flag” is composed of specific bit information (for example, 8 bits) indicating the start of a frame. In the “slot address”, the slot address SAD of the slot in which the monitored board 40 is actually mounted is mounted. “Identifier” represents the function type of the frame. The function type of the frame includes polling, polling response, command, and the like. “Information” includes board ID information or power supply O
The content information of the command such as N / OFF is mounted. In the “frame check”, parity check information (or CRC check information or the like) having contents from a slot address column to an information column is mounted. The “end flag” is made up of specific bit information (for example, 8 bits) indicating the end of the frame.

FIG. 11 shows a flowchart of an electronic circuit protection process when a board is erroneously mounted. The figure shows column # 0
The processing for each monitored device 40 implemented in the column # 1 is shown, and the processing for the monitored devices 40 in column # 1 and subsequent columns is also considered. When the power is supplied to the monitoring board 30, the monitoring board 30 inputs the monitoring control processing. In step S1, necessary initial processing is performed. For example, the switch unit 35 is connected to the port PT0. In step S2, "1" is set in the counter I. In step S3, a polling frame is generated,
The data is transmitted to the line of the terminal P9 via the CIF 34 and the SW 35. At this time, the transmission destination “slot address” = 1 and “identifier” = polling are installed.

In step S4, the reception of a polling response frame from the monitored board 40 is waited. If the polling response frame has not been received, it is determined in step S5 whether a timeout has occurred. In this example, since the monitored board 40 is not mounted in the slot 1 of the column # 0, a timeout finally occurs. In this case, +1 is added to the counter I in step S9.
Then, in a succeeding step S10, it is determined whether or not I ≧ 7.
If I ≧ 7, the process returns to step S3 to process the next monitored substrate 40.

As described above, in step S3, the polling frame of the destination "slot address" = 3 is transmitted. In step S4, reception of a polling response frame is waited, and if received, the process proceeds to step S6.
At this time, the source “slot address” = 3, “identifier” = polling response, and “information” = identification ID # 07 of the monitored board 40 are mounted in the polling response frame.

In step S6, the registration ID of the slot 3 in the board mounting table and the reception ID of the polling response frame
Is determined in step S7.
At this time, when the correct monitored board 40 is mounted in the slot 3, the two ID information match, and when the wrong monitored board 40 is mounted, they do not match. If they match, a command frame is generated in step S8 and transmitted to the monitored board 40. At this time, the transmission destination “slot address” = 3, “identifier” = command, and “information” = power ON. If they do not match, the process of step S8 is skipped. That is, the power ON command is not transmitted.

In step S9, the value of the counter I is incremented by 1, and the process proceeds in the same manner. Then, when the processing for the monitored board 40 in the slot 7 is completed, the process goes to step S10.
Satisfies I ≧ 7, and the processing for column # 0 is exited. On the other hand, when the power to the monitored board 30 is turned on, the monitored board 30 inputs the monitored control processing. In step S31, necessary initial processing is performed. In step S32, a frame reception from the monitor board 30 is waited.
At 3, it is determined whether or not the destination “slot address” of the received frame matches its own slot address SAD. If they do not match, the process returns to step S32 and waits for reception of the next frame.

If they match, it is determined in step S34 whether or not a polling frame has been received. In the case of a polling frame, the identification ID information of the monitored board is obtained in step S35. In step S36, a polling response frame is generated and transmitted to the monitoring board 30. At this time, for example, the source “slot address” = 3, “identifier” = polling response, and “information” = ID # 07 are mounted.

If it is determined in step S34 that a polling frame has not been received, it is determined in step S37 whether a command frame has been received. If a command is received, it is further determined in step S38 whether or not the command is a power ON command.
At 9, the control signal S for the power supply switch unit 15 is set to 0. As a result, the power supply switch unit 15 is turned on, and power is supplied to the electronic circuit unit 41. Since the power ON command is not transmitted to the erroneously mounted monitored board 40, no power is supplied to the electronic circuit section 41.

Also, the power is turned on in the determination in step S38.
If it is not a command, it is determined in step S40 whether or not the command is a power-off command. In the case of the power off command, the power supply to the electronic circuit unit 41 is turned off in step S41. Note that this power-off command is not generated in the polling process but is started, for example, when a maintenance person inputs a maintenance terminal.

Thus, according to the present embodiment, only the normally mounted monitored board 40 is supplied with power.
The output circuit of each monitored board 40 normally mounted does not damage the output circuit of another board, nor does its own output circuit be damaged. Further, by simply changing the contents of the board mounting table, the electronic circuit can be effectively protected from erroneous mounting of the board in an apparatus having any board configuration.

Although a plurality of preferred embodiments of the present invention have been described, it is needless to say that various changes can be made in the configuration, control, and combination of these components without departing from the spirit of the present invention. Not even.

[0052]

As described above, according to the present invention, an electronic circuit can be effectively protected from human error by detecting erroneous mounting of a package or a cable and limiting power supply to an output circuit or limiting its signal output. it can.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an electronic circuit package according to the first embodiment.

FIG. 3 is a diagram illustrating an electronic circuit package according to a second embodiment.

FIG. 4 is a diagram illustrating an electronic circuit package according to a third embodiment.

FIG. 5 is a diagram (1) illustrating an electronic circuit package according to a fourth embodiment.

FIG. 6 is a diagram (2) illustrating an electronic circuit package according to a fourth embodiment.

FIG. 7 is a diagram illustrating an electronic circuit package according to a fifth embodiment.

FIG. 8 is a diagram (1) for explaining an erroneous mounting protection method for an electronic circuit package according to an embodiment;

FIG. 9 is a diagram (2) illustrating an erroneous mounting protection method for an electronic circuit package according to an embodiment.

FIG. 10 is a diagram (3) for explaining an erroneous mounting protection method of the electronic circuit package according to the embodiment;

FIG. 11 is a diagram (4) for explaining an erroneous mounting protection method of the electronic circuit package according to the embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Electronic circuit package (board) 11 Connector terminal 12 Electronic circuit unit 13 Output circuit unit 14 Decoder (DEC) 15 Power supply switch unit 20 Backplane 21 Connector terminal 22 Flat cable 30 Monitoring board 31 Electronic circuit unit 32 CPU 33 Main memory (MM) ) 34 Communication interface (CIF) 35 Switch unit (SW) 36 Common bus 40 Monitored board 41 Electronic circuit unit 42 Monitored control unit 43 Control unit 44 Communication interface (CIF) BF Buffer circuit CMP Comparator GA Gate circuit OPA Operational amplifier

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Nobuyuki Kobayashi 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture In-house Fujitsu Digital Technology Limited (72) Inventor Koji Suda 2-chome, Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa No.3-9 Fujitsu Digital Technology Stock Company In-house (72) Inventor Kazuhisa Murata 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited

Claims (6)

[Claims] 1. A power supply terminal, and a control signal connected between the power supply terminals and determined based on a signal level input via another predetermined terminal to determine whether or not the mounting state of the own package is appropriate or not, and a corresponding control signal. An electronic circuit package, comprising: a mounting state determining unit that outputs a signal; and one or more electronic circuits that activate / deactivate an output signal of the circuit in accordance with the control signal. 2. A control signal connected between a power supply terminal and a power supply terminal, the control signal being determined based on a signal level input through another predetermined terminal to determine whether or not the mounting state of the own package is appropriate. An electronic circuit package, comprising: a mounting state determining unit that outputs power, a switch unit that turns on / off power supply according to the control signal, and one or more electronic circuits that are supplied with power via the switch unit. . 3. The electronic circuit package according to claim 2, wherein the electronic circuit is a circuit that outputs a signal to a signal output terminal of the package. 4. The mounting state determining unit includes a decoder circuit that determines whether or not the mounting state of the package is appropriate based on each signal level input through a plurality of terminals and outputs a corresponding control signal. The electronic circuit package according to any one of claims 1 to 3, wherein: 5. A mounting state determining section comprising a level detecting circuit for determining whether or not the mounting state of the own package is appropriate based on a signal level input via one terminal and outputting a corresponding control signal. The electronic circuit package according to any one of claims 1 to 3, wherein: 6. An erroneous mounting protection method for an electronic circuit package of an apparatus in which a plurality of electronic circuit packages are mounted in a slot having a frame structure, wherein a plurality of monitored packages that hold identification ID information of the own package; A monitoring package for holding a table in which identification ID information of each monitored package is associated with slot position information to be mounted, and performing data communication with each of the monitored packages; Collects the identification ID information from the monitored package at each mounting position, compares the collected ID information with the information in the table, and activates the output signal of the monitored package for which a comparison match is obtained. Error protection method for electronic circuit packages.