JPH11224880A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a wiring and a connection hole from being misaligned with each other when the groove of a groove wiring and the connection hole are formed through a single embossing operation by a method wherein a projection for forming a groove wiring and another projection for forming a connection hole are provided in an embossing die. SOLUTION: A MOS transistor 202 is formed on a silicon layer 201, and a first and a second insulating film, 203 and 204, are formed in layers thereon through a CVD method. In succession, the second insulating film 204 is flattened, a first projection 206 provided to an embossing die 205 is made to bite into the second insulating film 204 to form a groove 207. At the same time, a second projection 208 is provided in a part of the first projection 206, and the second projection 208 is made to bite into the second insulating film 204 to form a connection hole 209. By this setup, a photolithography process and an etching process both carried out for the formation of wiring can be shortened, and the wiring is prevented from being misaligned with the connection hole 209 when the groove 207 and the connection hole 209 are formed through a single embossing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a process for forming a metal wiring and an interlayer insulating film.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor device will be described with reference to the sectional views of FIGS. A MOS transistor 102 is formed on the silicon layer 101 (FIG. 1A). First, a first insulating film 103 made of silicon oxide is formed thereon, and then a second insulating film 104 made of borophosphosilicate glass (BPSG) is deposited (FIG. 1B). Subsequently, the second insulating film 104 is flattened by a so-called reflow method of softening BPSG at a high temperature, and then the connection holes 10 are softened.
5 and the wiring 106 are formed (FIG. 1C). If necessary, the steps of forming an insulating film, flattening, forming a connection hole, and forming a wiring are repeated to complete a semiconductor device.

As a method for planarizing an insulating film (interlayer insulating film), in addition to the above, a method using chemical mechanical polishing (CMP),
Alternatively, there is a method using spin-on-glass (SOG), or a combination thereof. Alternatively, for example, there is a method of flattening an insulating film by pressing as described in Japanese Patent Application Laid-Open No. 8-250493. In any case, after the planarization of the insulating film, the formation of the connection hole and the formation of the wiring are continued, or in some cases, the formation of the groove for the groove wiring, the formation of the connection hole, and the formation of the wiring are continued.

[0004]

However, the conventional method of manufacturing a semiconductor device comprises at least the steps of forming and flattening an insulating film, forming a connection hole, and forming a wiring, and further forming at least a connection hole. The process and the wiring formation process include a photolithography process and an etching process, respectively. When multi-layer wiring is required, there is a problem that the process of manufacturing a semiconductor device becomes extremely long.

[0005]

Therefore, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film and embossing (pressing) the surface of the insulating film at a temperature at which the insulating film softens. And a projection for forming a groove wiring and a projection for forming a connection hole are provided in a mold used for embossing, so that the manufacturing process of the semiconductor device can be shortened. It is intended to provide a manufacturing method.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the cross-sectional views in FIGS.

A MOS transistor 202 is formed on the silicon layer 201 (FIG. 2A). After a first insulating film 203 made of silicon oxide is formed thereon using a CVD method, a boron-phosphorus silicate glass (B
2 (PSG) is formed.
b). Subsequently, the second insulating film 204 is planarized by reflow of BPSG at a high temperature of about 900 ° C.
05 at a high temperature of about 850 ° C.
Is embossed (FIG. 1c). In this example, the mold 205 is made of silicon oxide, but it is possible to make the mold with another material if it is not softened at the temperature at the time of stamping. For example, silicon carbide and alumina can be considered. The mold 205 is provided with a first projection 206.
Portion cuts into the second insulating film 204, and a groove 207 is formed. The groove 207 is a portion which is later buried with a metal and becomes a wiring (corresponding to a groove for forming a wiring by a so-called damascene method). In addition, a second projection 208 is provided on a part of the first projection 206, whereby a connection hole 209 is formed in the second insulating film 204. However, the connection hole 209 formed during the embossing does not open to the bottom. This is because the first insulating film 203 is provided, and the second insulating film 204 has a margin so as not to damage the lower layer. This is because it is necessary to make the depth such that the second projection 208 does not penetrate. Of course, when there is no such restriction, for example, when the first insulating film 203 is omitted, and when the base of the connection hole 209 is a soft base such as a malleable metal, or the embossing process is sufficiently accurate. If it is possible to control the distance, the connection hole 209 may be opened to the bottom.

Next, the entire surface of the second insulating film 204 is etched to open the connection hole 209 to the bottom. In this example, the second insulating film 204 is BPSG, and the first insulating film 20
Since silicon oxide 3 is used, when the entire surface of the second insulating film 204 is etched, the first insulating film 203 exposed at the bottom of the connection hole 209 is simultaneously etched, and the connection hole 209 can be opened to the bottom. It is. Furthermore, titanium nitride film 2
10 is formed by a sputtering method, a tungsten film 211 is formed on the entire surface by a CVD method, and the tungsten film 211 and the titanium nitride film 210 other than the connection hole 209 and the groove 207 are removed by a CMP method to form a wiring. The process according to the present invention is completed (FIG. 1d).

In this embodiment, the flattening of the second insulating film 204 is performed separately from the embossing. However, if the protrusions of the die 205 are flattened, the flattening of the second insulating film 204 and the grooves 207 and The connection holes 209 can be formed at the same time. In this example, silicon oxide or BPSG was used for the insulating film. However, other than these materials, any other material capable of forming a groove or a contact hole for the groove wiring by embossing and having a function as an interlayer insulating film. Any substance can be used. For example, an organic polymer film (resin film) can be used. The temperature during embossing needs to be changed depending on the material.
If a material that softens at a temperature of 00 ° C. or lower is used, the method of this example can be applied to the second and subsequent layers when wiring of two or more layers is performed using aluminum or an alloy thereof as a wiring material. In addition, in the present embodiment, the process of forming the wiring on the MOS transistor is described. However, the present invention is not limited to this. For example, a bipolar transistor may be used, and the method of the present embodiment may be applied to a compound semiconductor device. Further, although titanium nitride and tungsten are used as the wiring material, the wiring material is not limited to these, and for example, polycrystalline silicon, aluminum, an aluminum alloy, copper, or the like can be used.

Further, in this embodiment, the groove 207 is formed by embossing.
And the connection hole 209 are formed at the same time, but only the groove 207 may be formed by embossing, and the formation of the connection hole 209 may be performed using a photolithography method and an etching method as in the related art.

[0011] The range to be molded by embossing on the semiconductor device may be a chip unit, but if the entire wafer is processed collectively, the effect of the shortening of the process according to the present invention can be further remarkable.

[0012]

According to the method of manufacturing a semiconductor device of the present invention described above, at least a photolithography step and an etching step for forming a wiring and, in many cases, for forming a connection hole are required as compared with the conventional method for manufacturing a semiconductor device. The photolithography step and the etching step can be shortened. Further, when the groove and the connection hole of the grooved wiring are formed by a single embossing, there is also an effect that no deviation occurs between the wiring and the connection hole.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device of the present invention.

[Explanation of symbols]

 101, 201 ... silicon layer 102, 202 ... MOS transistor 103, 203 ... first insulating film 104, 204 ... second insulating film 105 ... connection hole 106 ... wiring 205 ... type 206 ... first projection 207 ... groove 208 ... second projection 209 ... connection hole 210 ... titanium nitride film 211 ... tungsten film

Claims (2)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: at least a step of forming an insulating film, a first protrusion for forming a groove serving as a groove wiring, and a second protrusion for forming a connection hole. Forming a groove and a connection hole as a groove wiring by embossing the surface of the insulating film at a temperature at which the insulating film is softened using a mold having the mold. Method. 2. A method for manufacturing a semiconductor device, comprising: using a mold having at least a step of forming an insulating film and a projection for forming a groove to be a groove wiring, at a temperature at which the insulating film is softened. Forming a groove serving as a groove wiring by embossing the surface of the insulating film.