JPH11215140A - Common buffer type asynchronous transfer mode switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM(asynchronous transfer mode) switch which can prevent the scale increase of a device as much as possible when the device handles large-capacity information. SOLUTION: The addresses of a common buffer 3 are managed in the unit of group and the address group numbers are held and queued by means of a vacant address pool 11 and an address queue 12. A write control section 13 assigns a vacant address to a newly inputted cell when the vacant address exists in the last address group of the address queue 12. When no vacant address exists in the address group, the control section 13 assigns one address in an address group number read out from the address pool 11 to the newly inputted cell and registers the address group number in the address queue 12 corresponding to the destination of the cell. A readout control section 14 returns the leading address group in the queue 12 to the address pool 11 when the addresses in the address group become vacant after the cells corresponding to the addresses in the address group are sent out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a common buffer type AT.
M (Asynchronous Transfer M)
mode: Asynchronous transfer mode).

[0002]

2. Description of the Related Art FIG. 15 shows a conventional common buffer type ATM.
FIG. 3 is a schematic block configuration diagram of a switch. This common buffer type ATM switch uses a multiplexer (MUX).
1, a demultiplexer (DMUX) 2, a common buffer 3, an address pool 4, an address queue 5, a write control unit 6, and a read control unit 7. The multiplexer 1 receives cells sent from a plurality of incoming lines and writes the cells to a predetermined address of the common buffer 3 according to an instruction from the write control unit 6. Each cell has a fixed length and includes a header including information for specifying a destination in addition to data to be transferred. The demultiplexer 2 includes a read control unit 7
The cell is read from a predetermined address of the common buffer 3 in accordance with the instruction from and output from a predetermined destination (outgoing line). The common buffer 3 temporarily stores cells input from an incoming line and output from an outgoing line provided for each destination. The address pool 4 holds addresses in the common buffer 3 for which cells have not yet been stored. In FIG. 15, circles indicate address information indicating the addresses themselves. The address queue 5 stores an address at which a cell is stored in the common buffer 3 for each destination on a FIFO basis.
(First in first out) operation. The writing control unit 6
The destination of the cell is analyzed from the cell header, and an empty address in the common buffer 3 for temporarily storing the destination is allocated.
The read control unit 7 issues an instruction to take out a cell from the common buffer 3 according to the address read from the address queue 5 and send it to a predetermined destination.

Next, the operation of the conventional common buffer type ATM switch when receiving cells and the operation when transmitting cells will be described. First, the operation when receiving a cell will be described. This operation is performed by the write control unit 6
The execution is controlled by

When a cell is input to the multiplexer 1 from one of the input lines, the write control unit 6 determines whether the cell is valid or invalid, and if valid, determines the destination from the cell header. In the case of a valid cell, an address for storing the cell is obtained from the free address pool 4 and the multiplexer 1 is instructed to write the input cell to that address in the common buffer 3. As a result, the cells are temporarily stored in the common buffer 3. In addition, the writing control unit 6
At the same time, it is queued at the back of the address queue 5 corresponding to the destination of the cell.

Next, an operation when transmitting a cell will be described. This operation is controlled by the read control unit 7.

The read control unit 7 reads an address at the head of the address queue 5 corresponding to an outgoing line (destination) to be read, and reads the common buffer 3 indicated by the address.
And read out the cell from the corresponding outgoing line. At this time, since the address from which the cell has been read becomes unused, the read control unit 7 returns the address to the free address pool 4.

A conventional common buffer type ATM switch is:
By operating as described above, cells can be exchanged by outputting cells to the destination (outgoing line) indicated in the cell header. However, in order to function reliably as an ATM switch, the following capacity is required. An empty address pool 4 and an address queue 5 are required.

First, the free address pool 4 needs a capacity capable of holding all addresses of the common buffer 3. Considering a case where the address queue 5 is concentrated on a specific outgoing line (destination), a capacity that can hold all addresses of the common buffer 3 per outgoing line is required. In other words, a total capacity of the number of output lines is required. For example, considering a common buffer type ATM switch in which the common buffer 3 can store 1K cells and the number of output lines is 8, the free address pool 4 has 1K addresses, and the address queue 5 has 1K ×
A capacity of 8 = 8K addresses is required.

[0009]

In the prior art, it has been considered to cope with communication at a constant rate to some extent, so that a design in which the buffer capacity of the ATM switch is relatively small is sufficient. Accompanied by,
Since it has become necessary to handle computer communication having a high burst property, the ATM switch is required to have a buffer capacity one or two digits larger than that of the conventional buffer capacity. Therefore, if the common buffer type ATM switch is to be realized by the conventional realization method as it is, the following problem occurs.

As described above, it is clear that the capacity (hardware capacity) of the free address pool and the address queue increases in proportion to the capacity of the common buffer. Therefore, a common buffer type A equipped with a large-capacity common buffer
The TM switch requires a large capacity free address pool and address queue. For this reason, the ATM switch may become a bottleneck in the implementation of an LSI and miniaturization. Here, how much required capacity increases will be described by taking, as an example, a case where the number of common buffers is increased from 1K cells to 1M cells, which is 1K times as large. Note that the number of outgoing lines is 32.

First, since 10 bits are required to represent one address in a 1K (cell) space, the free address pool and the address queue require the following capacities, respectively.

Free address pool: 10 bits × 1 K = 10 K bits Address queue: 10 bits × 1 K × 32 (outgoing lines) = 3
20 Kbits, that is, if the capacity of the common buffer is 1K cells, 3
A 30 Kbit capacity is required for the free address pool and the address queue.

Next, when the number of common buffers is increased to 1M cells, two addresses are required to represent one address in a 1M (cell) space.
Since 0 bits are required, the free address pool and the address queue at this time require the following capacities, respectively.

Free address pool: 20 bits × 1 M = 20 M bits Address queue: 20 bits × 1 M × 32 (outgoing lines) = 6
40 Mbits, that is, when the capacity of the common buffer is 1 M cells, 6
A capacity of 60 Mbits is required for the free address pool and the address queue. 1K common buffer capacity
The capacity required for the free address pool and the address queue becomes 2K times as much as the capacity. That is, in order to store such large-capacity information (address), a large number of large-capacity DRAMs are required, which causes problems in terms of LSI implementation, mounting, and speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a common buffer type capable of minimizing an increase in the size of a device when handling a large amount of information (address). It is to provide an asynchronous transfer mode switch.

[0016]

In order to achieve the above object, a common buffer type asynchronous transfer mode switch according to a first aspect of the present invention comprises a common buffer provided common to output lines provided for each destination. In the common buffer type asynchronous transfer mode switch for temporarily storing cells transmitted through any of a plurality of input lines to a vacant address area, address management in the common buffer is performed on a group basis.

A common buffer type asynchronous transfer mode switch according to a second aspect of the present invention includes a common buffer for temporarily storing cells input from an input line and output from an output line provided for each destination, and no cells stored therein. An address information pool for holding address information relating to the address of the common buffer; an address information queue for retaining address information relating to the address of the common buffer in which cells are stored for each line in a first-in first-out manner; The address information is obtained from the address information pool, and the cell is stored in the address of the common buffer specified by the address information, and the address information extracted from the address information pool corresponds to the destination of the cell. Write system for registering in the address information queue Means for outputting a cell taken out from the common buffer from the outgoing line based on the first address information registered in the address information queue corresponding to the outgoing line from which the cell can be transmitted, and managed by the address information. Read-out control means for returning the address information to the address information pool when all the available addresses become free addresses, wherein the write control means and the read-out control means perform one or more address management of the common buffer. Is performed for each group constituted by the addresses of the addresses, the information regarding each group is treated as the address information, and the cell accumulation status at each address managed by the address information registered in the address information queue is managed by the pointer information. Is what you do.

According to a third aspect of the present invention, in the common buffer type asynchronous transfer mode switch according to the second aspect, the write control means and the read control means manage the pointer information in association with each of the address information. It is.

According to a fourth aspect of the present invention, in the common buffer type asynchronous transfer mode switch according to the second aspect of the present invention, the write control means includes a step of storing a free address in which no cell is stored in each of the address information queues. If the cell exists in the address managed by the tail address information, the cell is stored in the free address managed by the address information, and the cell is stored in the tail address information. The end of the address is indicated by a write pointer.

According to a fifth aspect of the present invention, in the common buffer type asynchronous transfer mode switch according to the third aspect, the read control means includes an address managed by the first address information held in each of the address information queues. , And sequentially outputs the cells stored in the first address information, and indicates the end of the address from which the cell was read in the start address information by a read pointer.

According to a sixth aspect of the present invention, there is provided the common buffer type asynchronous transfer mode switch according to the second aspect, wherein the write control means comprises the address information which has become a vacant address when a cell is transmitted by the read control means. The newly input cell is stored at an address managed by only one piece of address information held in the queue.

A common buffer type asynchronous transfer mode switch according to a seventh aspect of the present invention, in the second aspect, further comprises queue monitoring means for monitoring the use status of each of the address information queues, and the write control means performs management. The address information to be registered in each of the address information queues is obtained from the address information pool holding the address information having a different number of addresses according to the use status of each of the address information queues.

In a common buffer type asynchronous transfer mode switch according to an eighth invention, in the seventh invention, the queue monitoring means monitors a queue length of each address information queue, and the write control means The address information to be registered in the address information queue corresponding to the queue length monitored by the queue monitoring means is determined.

According to a ninth aspect of the present invention, in the common buffer type asynchronous transfer mode switch according to the second aspect, the write control means and the read control means hold the pointer information for each destination, and the read control means In determining whether to return the first address information registered in the address information queue to the address information pool by transmitting the cell, the first address information indicates the end of the address from which the cell was read in the first address information. When the value of the read pointer is equal to the value of the write pointer indicating the end of the address where the cell is stored in the last address information registered in the address information queue, another address information is stored in the address information queue. The address information is stored only when the address information is not registered. It is obtained by adding a condition of returning to Lumpur.

According to a tenth aspect of the present invention, there is provided the common buffer type asynchronous transfer mode switch according to the second aspect, wherein the write control means is adapted to perform a single-address transmission when a cell input from the input line is a broadcast cell for a large number of destinations. Address information for which only one address is to be managed is extracted from the address information pool, registered in each of the address information queues corresponding to the destination of the cell, and the number of destinations of the broadcast cell is set in the broadcast cell counter. The read control means decrements the broadcast cell counter each time the broadcast cell is transmitted, and returns the address information to the address information pool when the broadcast cell counter becomes 0. .

According to an eleventh aspect of the present invention, in the common buffer type asynchronous transfer mode switch according to the third aspect, the write control means, when extracting address information from the address information pool, stores pointer information corresponding to the address information. It is to be inspected.

[0027]

Preferred embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a schematic block diagram showing a first embodiment of a common buffer type ATM switch according to the present invention. This common buffer ATM
The switches include a multiplexer (MUX) 1, a demultiplexer (DMUX) 2, a common buffer 3, a free address pool 11, an address queue 12, a write control unit 13,
It has a read control unit 14 and a write / read pointer table 15. With these configurations, a cell exchange process described later is realized. Before describing each component, a characteristic technical idea of the present embodiment will be described.

Basically, the write control unit and the read control unit queue the addresses of the common buffer in the address queue and then return the emptied (released) addresses to the free address pool. Is the same as In the present embodiment, a technical idea of collecting some queued and pooled target addresses into groups is introduced. That is, in the conventional common buffer type ATM switch, each address is held (queued) in the free address pool and the address queue, but in the present embodiment, the address group (number) is held. It is characterized by having. That is, it is characterized in that the address management in the common buffer is performed not on an individual address basis but on a group basis.

Here, each component in the present embodiment will be described with reference to FIG.

The multiplexer 1 receives cells sent from a plurality of incoming lines and writes the cells to a predetermined address of the common buffer 3 in accordance with an instruction from the write control unit 13. The demultiplexer 2 reads a cell from a predetermined address of the common buffer 3 according to an instruction from the read control unit 14 and outputs the cell from a predetermined destination (outgoing line). Common buffer 3
Temporarily stores cells input from an incoming line and output from an outgoing line provided for each destination. The above configuration may be the same as the conventional one. Next, the vacant address pool 11 is an address information pool for holding address information relating to addresses of the common buffer 3 in which no cells are stored, that is, address group numbers. The function itself is the same as the conventional one, but the held address information is not an address itself but an address group (number). Address queue 12
Is an address information queue for holding address information relating to the address of the common buffer 3 in which cells are stored, that is, an address group number, in a FIFO (first-in first-out) method for each output line. The function itself is the same as the conventional one, but the address information to be queued is not the address itself but an address group (number). The write controller 13 acquires the address group number from the free address pool 11 based on the header of the cell input from the incoming line, and accumulates the cell at the address of the common buffer 3 specified by the address group. Give instructions to Further, the address group number extracted from the free address pool 11 is registered in the address queue 12 corresponding to the destination of the cell. The read control unit 14 controls the demultiplexer 2 to output the cell extracted from the common buffer 3 from the output line based on the first address group number registered in the address queue 12 corresponding to the output line from which the cell can be transmitted. Give instructions to Further, when all the addresses included in the address group become empty, the address group number is returned to the empty address pool 11. The write / read pointer table 15 is a component newly provided in the present embodiment, and each of the write control unit 13 and the read control unit 14 manages the cell accumulation status of each address included in each address group. 4 is a pointer table for storing pointer information (write pointer and read pointer) for performing the operation. Each write pointer points to the end of the address where the cell in each address group is written, and the read pointer points to the end of the address where the cell in each address group is not written. The write / read pointer is provided corresponding to each address group. In the present embodiment, the number of addresses included in each address group is plural and equal. The write control unit 13 and the read control unit 14 recognize the number of addresses in advance.

A feature of this embodiment is that, as described above, the address management unit to be held or queued for cell exchange is not an individual address unit but an address group unit. As a result, the amount of data to be held or queued can be reduced.
1 and the address queue 12 do not have to be large. For example, if one address group has 100 addresses, the number of address information handled by the free address pool 11 and the address queue 12 is simply 1/100. As a result, even if a large amount of information is handled, an increase in the size of the ATM switch device can be suppressed as much as possible.

Next, the operation of the write control section 13 in the present embodiment when a cell is input at the time of cell write processing will be described with reference to the flowchart shown in FIG.

The write controller 13 determines the validity of the cell sent to the multiplexer 1 (step 10).
0). If the cell is valid, the destination is specified by referring to the cell header, and the address queue 1 corresponding to the destination is specified.
It is checked whether an address group has been queued in step 2 (step 110). If there is a queued address group, it is checked whether there is a free address in the last address group among the queued address groups (step 12).
0). This can be recognized by comparing the write pointer (WP) in the write / read pointer table 15 corresponding to the last address group with the number of addresses belonging to the address group. That is, when the values are not the same and the write pointer does not reach the number of addresses belonging to the address group minus 1, it can be determined that there is a free address in the address group. Therefore, at this time, the write control unit 1
3 increments the write pointer corresponding to the address group by +1 (step 130), and adds the write pointer value after the count up to the number of the address group.
Is given to the multiplexer 1 as the write address of the received cell (step 140). It is needless to say that the cell has a fixed length and is not stored at an address determined by a simple addition value of the address group number and the write pointer value. For the address conversion processing for obtaining the physical address, a conventional technique may be used. However, in order to simplify the address conversion process, it is desirable that each address group and each address included in the address group be continuous. An example of address conversion will be described. There are four address groups (address group numbers: 0 to 3), and 102 in one address group.
Assuming that four addresses (addresses: 0 to 1023) are included, an address represented by 12 bits can be obtained by the formula (address group number × 1024 + write pointer value).

On the other hand, when the write pointer (WP) and the number of addresses belonging to the address group minus one have the same value,
In the address queue 12 already queued in the address queue 12, there is no free address in the common buffer 13 in which no cells are stored. Therefore, the write control unit 13 reads a new address group from the free address pool 11 and adds the address of the common buffer 3 specified by the value obtained by adding the write pointer value to the read address group number to the received cell. An instruction is given to the multiplexer 1 as a write address, and the address group is queued in the address queue 12 corresponding to the destination of the cell (steps 150 and 160). Note that the write pointer corresponding to the address group newly read from the free address pool 11 has an initial value of 0. If there is no readable address group in the free address pool 11 (step 150), a predetermined error process is executed in the same manner as when an invalid cell is received. The description is omitted because the processing is not characteristic. The cells sent to the multiplexer 1 by the above processing are temporarily stored at the address specified by the write control unit 13.

As described above, when there is no free address in the already queued address group, a process of queuing the address information is executed as in the conventional case. If there is a free address, the address group is used for storing cells that have received the free address without newly queuing the address group. Therefore, the process of registering the address information (address group number) in the address queue 12 can be omitted.

Next, the operation of the read control unit 14 in the present embodiment when a cell is transmitted from the outgoing line at the time of cell read processing will be described with reference to the flowchart shown in FIG.

If an address group exists in the address queue 12 corresponding to a certain destination (outgoing line) (step 200), the read control unit 14
The address of the common buffer 3 specified by a value obtained by adding the value of the read pointer (RP) in the write / read pointer table 15 for managing the address of the address group to the number of the first address group registered in An instruction is issued to the demultiplexer 2 as the read address of the cell to be transmitted (step 210). As a result,
The demultiplexer 2 reads a cell from the address specified by the read control unit 14 and outputs the cell from a predetermined output line.

Thereafter, the read control unit 14 compares the read pointer corresponding to the head address group with the number of addresses belonging to the address group (step 220). If the values are not the same and the read pointer does not reach the number of addresses belonging to the address group minus 1, the read pointer is counted up by +1 (step 230). If the read pointer value after the count-up is not the same as the write pointer value corresponding to the head address group, it is determined that there is still an address in which cells are stored in the address group, and the address group is left as it is. End the processing (step 2
40). On the other hand, when the read pointer value and the write pointer value are the same (step 240) and when the read pointer value before the count-up is equal to the number of addresses belonging to the address group minus one (step 22).
0) resets the read pointer and the write pointer corresponding to the address group (that is, to 0), judging that there are no remaining addresses in which cells are stored in the address group, that is, all are empty addresses. Then, the queued address group is returned to the free address pool (step 260).

As described above, when there is no free address in the already queued address group, the address information is transferred to the free address pool 1 as in the prior art.
The process of returning to 1 is executed. If there is a free address in the address group, the address group is left in the address queue 12 as it is, so that the address information moved after transmitting the cell is transferred. The processing can be omitted.

According to the present embodiment, since queuing and holding are performed in address group units as described above, the amount of information registered in the free address pool 11 and the address queue 12 can be greatly reduced. To what extent the hardware capacity of the free address pool 11 and the address queue 12 can actually be reduced is shown by the same numerical example as above, where the capacity of the common buffer 3 is 1M cells and the number of output lines is 32. Become. Assuming 128 addresses per address group, the number of address groups: 1M ： １128 = 8K Since 13 bits are required to represent 8K cells, an empty address pool: 13 bits × 8K = 104Kbi
t Address queue: 13 bits × 8K × 32 (outgoing line) =
3.328 Mbit write / read pointer: 7-bit counter × 2 (write / read) × 8 K = 112 Kbit As a result, in the present embodiment, when the capacity of the common buffer is 1 M cells, the capacity of 3.554 Mbit is set to the free address pool. 11 and the address queue 12. Therefore, according to the present embodiment, 3.554 / 660 compared to the conventional 660 Mbit.
The free address pool 11 and the address queue 12 can be configured on a scale of = 0.0054 (= about 5%). Actually, since the address management is performed on a group basis, the amount of hardware for the control circuit will increase as compared with the past, but if this is taken into account, the hardware scale must be significantly reduced. Can be.

In this embodiment, the write control unit 1
Although the pointer information used by the read control unit 3 and the read control unit 14 are set in the write / read pointer table 15, the pointer information may be held in the control units 13 and 14.

Embodiment 2 This embodiment is applicable when only one address group is registered in the destination-specific address queue 12. Note that the block configuration in the present embodiment is the same as that in the first embodiment, and the processing performed by the write control unit 13 and the read control unit 14 is slightly different.

In the first embodiment, when all the addresses included in the queued address group are used, the address group becomes the free address pool 1 when cells are read from all the addresses.
It will be returned to 1. That is, in the first embodiment, when all of the addresses included in the address group are used for a newly input valid cell, even if a vacant address exists in the address group due to transmission of the cell, the new cell is transmitted. An appropriate address group is read from the free address pool 11 and used.
As a result, even if a free address is included in the queued address group, the address cannot be reused.

Therefore, in the present embodiment, if a vacant address is included in the queued address group, a new address group is assigned to a newly input valid cell in the vacant address pool. 11
It is characterized in that a vacant address of an already queued address group can be used instead of reading from an address group. The following is an example of the difference between the processing of the first embodiment and the processing of the present embodiment.

For example, only the address group A is queued in the address queue 12 of a certain destination, and the addresses A0, A1, A2,
It is assumed that the address is composed of four addresses A3. In each embodiment, addresses A0, A
Data is written in the order of 1, A2, and A3. On the other hand, cell reading is also performed in the order of addresses A0, A1, A2, A3.
Here, in the first embodiment, once the address A3
Is used, a new address group is read from the free address pool 11 for a new valid cell even if the address A2 has already been read (that is, the addresses A0, A1, and A2 are empty). Will be. On the other hand, in the present embodiment, even if the address A3 is used once, if the address A0, A1, A2 read out to the address A2 is empty, the addresses A0, A1, A2 are re-ordered. , So that a new address group is not read from the free address pool 11. As a result, the process of moving the address group can be omitted.

Next, the operation of the write control unit 13 in the present embodiment at the time of cell write processing when a cell is input will be described with reference to the flowchart shown in FIG. Note that the same processes as those in the flowchart shown in FIG.

The write control unit 13 specifies a destination by referring to the header of a valid cell sent to the multiplexer 1, and checks whether an address group is queued in the address queue 12 corresponding to the destination (see FIG. 4). Step 110). The processing when there is no queued address group is the same as that in the first embodiment. A new address group is read from the free address pool 11, and the address group corresponding to the read address group number and the address group are read. The cell storage instruction is issued to the address of the common buffer 3 specified from the write pointer value and the address group is queued in the address queue 12 corresponding to the destination of the cell (steps 150 and 160). In the case where there is an address group queued in the address queue 12 corresponding to the destination of the valid cell, if the write pointer (WP) of the address group is equal to the number of addresses belonging to the address group minus 1, then The write pointer value is returned to 0 (step 121). By returning to 0, an address that has become vacant due to transmission of cells in the address group can be used again. On the other hand, if the values are different, the write pointer is counted up by +1 (step 130). When the updated write pointer value becomes the same as the read pointer value, it can be determined that there is no free address included in the address group. Therefore, in this case, a new address group is read from the free address pool 11, and a cell accumulation instruction and registration of the address group in the address queue 12 are performed (steps 131 and 15).
0,160). If the updated write pointer value is different from the read pointer value, the address pointed to by the write pointer can be determined to be a free address, and the multiplexer 1 is instructed to store cells at the free address (steps 131 and 140). In this way, the free addresses of the queued address group can be used effectively.

Next, the operation of the read control unit 14 in the present embodiment when a cell is transmitted from the outgoing line at the time of cell read processing will be described with reference to the flowchart shown in FIG.

The read control unit 14 sends out the address of the common buffer 3 specified by the number of the address group registered in the address queue 12 corresponding to a certain destination (outgoing line) and the value of the read pointer (RP). An instruction is issued to the demultiplexer 2 as the read address of the cell to be read (steps 200 and 210). Then, the read control unit 1
4 compares the read pointer corresponding to the address group with the number of addresses belonging to the address group minus one (step 220). As a result of comparison, when the read pointer value is the same, the read pointer value is returned to 0 (step 22).
1). By returning the value to 0, the cell can be read from the reused address. On the other hand, when the values are not the same, the read pointer is incremented by +1 (step 230). When the read pointer value after the count-up becomes the same as the write pointer value corresponding to the address group, each write / read pointer is reset and the queued address group is replaced with a free address pool. (Steps 240 to 260). In this way, the cells stored in the reused free addresses can be transmitted.

According to the present embodiment, when a free address exists in the queued address group, the free address can be used any number of times. As described above, since the free address can be reused, the number of executions of the process of registering the address information (address group number) in the address queue 12 can be further reduced.

Embodiment 3 FIG. FIG. 6 is a schematic block diagram showing Embodiment 3 of a common buffer type ATM switch according to the present invention. In the first embodiment, the number of addresses included in each address group is a plurality and the same number. However, the present embodiment is characterized in that a plurality of types of address groups having different addresses are prepared. And in this embodiment,
A queue monitoring unit 16 for monitoring the queue length of each address queue 12 is provided. When the write control unit 13 registers an address group in the address queue 12, the write control unit 13 has an appropriate size according to the queue length of the address queue 12. It is characterized in that an address group is obtained from the free address pool 11. "Size" here
That is, the number of addresses included in the address group. Therefore, a large address group means that the number of addresses contained in the address group is larger than others, and a small address group means that the number of addresses contained in the address group is larger than others. It means less.

Normally, the ATM switch operates in a state where only a few cells are stored for each outgoing line.
Cells destined for a certain outgoing line are input in burst traffic, and at that time, a large number of cells are accumulated in the corresponding address queue 12. At this time, a large number of cells destined for all the outgoing lines do not accumulate, but only a few outgoing lines. Since the ATM switch has such a feature, cells are not accumulated in the address queue 12 having a short queue length, and the address queue 1 having a long queue length is in the state.
It is considered that cell 2 is in a state where cells are accumulated. Therefore, in the present embodiment, the corresponding address queue 12
In the state where no cells are stored, a small address group (relatively small number of addresses) is allocated, and in the state where cells are stored, a large address group (relatively large number of addresses) is allocated. I decided to use it.

Next, the operation of the write control section 13 in the present embodiment at the time of cell input processing when a cell is input will be described with reference to the flowchart shown in FIG. Note that the same processes as those in the flowchart shown in FIG. 2 of the first embodiment are denoted by the same reference numerals, and description will be appropriately omitted.

The operation of the present embodiment is basically the same as that of the first embodiment. When acquiring an address group from the free address pool 11, it is determined whether to select a large address group or a small address group. Only different. That is, the write controller 13 newly reads an address group from the free address pool 11 when there is no free address in the last address group in the queue (steps 110 and 12).
0) At this time, if both the relatively large and small address groups are held in the free address pool 11, the queue length of the corresponding address queue 12 monitored by the queue monitoring unit 16 is referred to. If the queue length exceeds the threshold value held in advance, it is determined that cells are accumulated, and a relatively large address group is read from the free address pool 11 (steps 122 and 123). Then, a cell storage instruction and registration of the address group in the address queue 12 are performed (step 161). On the other hand, when the queue length does not exceed the threshold value held in advance, it is determined that no cells are accumulated, and a relatively small address group is read from the free address pool 11 (steps 122 and 123). Then, a cell storage instruction and registration of the address group in the address queue 12 are performed (step 162). When an address group of a different size is not held in the free address pool 11, there is no room for selection, so the address group of the held size is read out, and a cell storage instruction is sent to the address queue 12 of the address group. Are registered (steps 161 and 162).

On the other hand, the cell reading process in the reading control unit 14 is the same as that in the first embodiment shown in FIG. 3 except that the size of the address group to be handled is different, and the description is omitted.

According to this embodiment, address groups having different sizes are prepared, and an address group having an appropriate length is read from the free address pool 11 according to the queue length. Can be performed efficiently. In other words, a shorter queue length means that fewer cells are exchanged,
If a large address group (for example, 1024 addresses) is allocated to such an address queue 12, the addresses occupied by the address groups will remain empty, which is not efficient, but in the present embodiment, A relatively small address group is assigned to the address queue 12 as described above.
The common buffer 3 can be used efficiently. As a result, it is possible to prevent a problem that may occur when the addresses of the common buffer 3 are occupied in advance in groups.

In the above description, two types of address groups, large and small, exist. However, address groups of a larger size may be prepared. Then, for the address queue 12 having a long queue length, the address queue 12 may be assigned in order from the one having the largest queue length. At this time, a plurality of thresholds for determining the length of the queue length can be handled.

Also, the queue monitoring unit 16 in the above example
Monitors the queue length of the address queue 12. However, based on other usage conditions of the address queue 12, for example, the increasing / decreasing tendency of the queue length and the speed of increasing / decreasing, the future growth of the queue length (decreasing method) ) Can be applied to monitor prediction.

Further, in the present embodiment, the queue monitoring means is configured separately from the write control unit 13, but the queue monitoring means may be incorporated in the write control unit 13.

Embodiment 4 FIG. 8 is a schematic block diagram showing a fourth embodiment of a common buffer type ATM switch according to the present invention. In the first embodiment, the pointer information used by the write control unit 13 and the read control unit 14 is written /
Although management is performed in the read pointer table, this embodiment is characterized in that the number of pointers to be maintained is reduced by storing pointer information for each destination (outgoing line). That is, as is apparent from FIG. 8, the write pointer 17 and the read pointer 18 for each destination (outgoing line) are used instead of the write / read pointer table provided in the above-described embodiment.
And are assigned. Further, each address queue 12
Is provided with an address group number monitoring unit 19 for monitoring the number of address groups registered in.

Next, the operation in the present embodiment will be described. The cell read / write processing in the write control unit 13 is different from that in FIG. 2 is the same as the first embodiment shown in FIG. Each write pointer 17 manages the last address group in each address queue 12.

Next, the operation of the read control unit 14 in the present embodiment when a cell is transmitted from the outgoing line at the time of cell read processing will be described with reference to the flowchart shown in FIG. Note that the same processes as those in the flowchart shown in FIG. 3 of the first embodiment are denoted by the same reference numerals, and description will be appropriately omitted.

The operation of this embodiment is basically the same as that of the first embodiment, except for the following processing. That is, when the release of the address group is determined, in the first embodiment, the read pointer corresponding to the first address group matches the number of addresses belonging to the address group minus one (step 220) or the read pointer value does not match. The write pointer value matches (step 24)
However, in the present embodiment, it is not sufficient that the read pointer value matches the write pointer value (step 240), and the addresses indicated by the pointers are included in the same address group. There must be. This is because the write pointer 17 manages the last address group and the read pointer 18 manages the first address group, so that they do not always indicate addresses in the same address group. In other words, the case where the same address group is to be managed is only when only the (first) address group to be processed in a certain address queue 12 is registered and the other address groups are not registered. is there. Therefore, in the present embodiment, before the process of comparing the read pointer value with the write pointer value (step 240), there is one address group registered in the address queue 12 corresponding to the transmitted cell. Is determined (step 231). The read control unit 14 controls the address queue 12 that the address group number monitoring unit 19 knows.
The above determination can be made easily by referring to the number of address groups registered in the.

According to the present embodiment, the same effect as in the first embodiment can be obtained while the number of write / read pointers is reduced by the above configuration.

Embodiment 5 There is a method in which an address is copied at the time of writing in order to realize a broadcast in which an input cell is copied to a designated plurality of outgoing lines and output by a common buffer type ATM switch. In this method, in the case of broadcast communication, the address information read from the free address pool is copied and each is queued in an address queue of a designated destination. At this time, the cells themselves are not copied but are stored in one address of the common buffer 3, and the number of copies of the cells is loaded into the broadcast cell counter instead. The broadcast cell counter is decremented each time a cell is transmitted, and the address storing the cell is released for the first time when the value reaches 0.

The present embodiment is characterized in that it can be applied to the above-mentioned broadcast communication. FIG. 10 is a schematic block diagram of a common buffer type ATM switch according to the present embodiment. This embodiment has a configuration in which a broadcast cell counter 20 for setting the number of destinations of broadcast cells is added to the configuration of the first embodiment. Then, similarly to the third embodiment, address groups having different sizes are used. However, the present embodiment is characterized in that an address group including only one address is prepared for a broadcast cell.

The basic operation of the broadcast cell exchange in the present embodiment is the same as the above-described method, and the address (group) is released when the broadcast cell counter becomes 0. However, if an address group including a plurality of addresses is used, each address group including an address corresponding to a broadcast cell most likely includes a different address. Is complicated. Therefore, in the present embodiment, when a broadcast cell is input, an address group including only one address is allocated for the broadcast cell.

Next, the operation of the write control unit 13 at the time of cell write processing in this embodiment when a broadcast cell is input will be described with reference to the flowchart shown in FIG. Note that the same processes as those in the above embodiments are denoted by the same reference numerals, and will be appropriately omitted.

The operation of the present embodiment is basically the same as that of the third embodiment, except that a process in the case where the input cell is for broadcast communication is added. Then, the address group with one address used in the broadcast communication is handled in the same manner as the small address group.

If the input cell is a broadcast cell (step 201), the write control unit 13 checks whether or not there is an address group with one address in the free address pool 11 (step 154). If the address group exists, the corresponding address group is read, and a cell accumulation instruction and registration of the address group in the address queue 12 are performed (step 163). Then, the number of destinations of the cell is set in the broadcast cell counter 20 (step 16).
4). The broadcast address group is an address group having one address, and the address group having one address can be used as one form of a small address group other than the broadcast communication.

Next, the operation of the read control unit 14 in the present embodiment when a cell is transmitted from the outgoing line at the time of cell read processing will be described with reference to the flowchart shown in FIG. Note that the same processes as those in the above embodiments are denoted by the same reference numerals, and will be appropriately omitted.

The operation of the present embodiment is basically the same as the first and third embodiments shown in FIG.
Processing for the case where the address group read from the address queue 12 is broadcast communication is added. That is, when the address group read from the address queue 12 is for broadcast communication, the read control unit 14 sets the address of the common buffer 3 specified by the address as the read address of the cell to be transmitted to the demultiplexer 2.
(Step 202). Then, the corresponding broadcast cell counter 20 is decremented by 1 (step 203).
Here, if the result of the subtraction indicates that the broadcast cell counter 20 becomes 0, it is determined that all the address groups for transmitting the same cell registered in the other address queues 12 have been processed, and that address is determined. Release the group (step 260).

As described above, the configuration according to the present embodiment can be easily applied to the broadcast cell exchange.

When the address group is composed of only a single address, the address itself can be used as the address information without using the address group number. Which one to use, and the method of identifying the address group number and the address itself are within the scope of the design matter.

Embodiment 6 FIG. If the address group number changes due to noise or the like, the same address group circulates twice, and cell exchange cannot be performed normally permanently. Therefore, the present embodiment is characterized in that a function for detecting such an abnormality is provided.

FIG. 13 shows a common buffer type A according to the present invention.
FIG. 14 is a schematic block diagram showing a sixth embodiment of a TM switch. This embodiment has a configuration in which a pointer reading unit 21 that reads both pointer values from the write / read pointer table 15 is added to the first embodiment.

Next, the operation of the write control unit 13 in the present embodiment at the time of cell write processing when a cell is input will be described with reference to the flowchart shown in FIG. Note that the same processes as those in the flowchart shown in FIG.

The operation of the present embodiment is basically the same as that of the first embodiment. When reading an address group from the free address pool 11, a process of checking a write / read pointer value corresponding to the address group is performed. Is added. That is, the write control unit 13
Indicates that there is no free address in the last address group registered in the corresponding address queue 12, so that a new address group is to be read from the free address pool 11 (steps 110, 120, 1).
50), the values of both the write pointer and the read pointer corresponding to the address group read by the pointer reading unit 21 are checked, and if both are 0, it means that the cell storage is instructed and the address queue 1 of that address group is normal.
2 is registered (step 160). On the other hand, if any of the pointer values is not 0, the address group is discarded without using the read address group because it is determined that there is a possibility that the address group is actually registered in any of the address queues 12. Then, an error notification is issued (step 170).

On the other hand, the cell read processing in the read control unit 14 is the same as that of the first embodiment shown in FIG. 3, except for the size of the address group to be handled.

According to the present embodiment,
Since an abnormality when the information of the address group changes due to noise or the like can be immediately detected, double rotation of the address group can be prevented.

In the present embodiment, the pointer reading unit 21 is separately provided as a means for reading both pointer values from the write / read pointer table 15, but may be incorporated as one function of the writing control unit 13. .

As described above, in each of the above embodiments,
It is characterized in that the addresses of the common buffer 3 are managed on a group basis. For this reason, the address information for holding or registering in the free address pool 11 and the address queue 12 may be the identification information of the address group. In the above embodiments, the address group number is used as the address information, and the address of the common buffer 3 can be obtained by a simple method. However, the address information need not be a number, but may be any information that can identify the address information.

[0084]

According to the present invention, the address of the common buffer for temporarily storing cells is managed not in individual addresses but in groups, and information on each group is held and queued in a free address pool and an address queue. As a result, the amount of data held or queued in the free address pool and the address queue can be reduced. That is, the capacity of each of the free address pool and the address queue increases in proportion to the capacity of the common buffer. However, even if the capacity of the common buffer increases, the rate of increase of each capacity of the free address pool and the address queue can be reduced. it can. As a result, even if a large amount of information is handled, it is possible to minimize an increase in the device size of the common buffer type asynchronous transfer mode switch.

When only one piece of address information is registered in the address queue for each destination, and there is a free address among the addresses managed by the queued address information, the free address is deleted. Can be used any number of times.

Also, address groups having different sizes are prepared, and an appropriate address group is newly assigned according to the use status of each address information queue, so that the common buffer can be used efficiently. it can.

Further, since the pointer information is allocated for each address information queue, the number of pointer information can be reduced as compared with the case where the pointer information is allocated for each address information.

Further, by preparing address information for managing only a single address, it can be easily applied to broadcast cell exchange.

Further, since an abnormality when the address information is changed due to noise or the like can be detected immediately, double rotation of the address group can be prevented.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a first embodiment of a common buffer type ATM switch according to the present invention.

FIG. 2 is a flowchart showing an operation at the time of a cell write process according to the first embodiment;

FIG. 3 is a flowchart showing an operation at the time of a cell read process according to the first embodiment;

FIG. 4 is a flowchart showing an operation during a cell write process according to the second embodiment;

FIG. 5 is a flowchart showing an operation at the time of a cell read process in the second embodiment.

FIG. 6 is a schematic block diagram showing Embodiment 3 of a common buffer type ATM switch according to the present invention.

FIG. 7 is a flowchart showing an operation at the time of a cell write process according to a third embodiment;

FIG. 8 is a schematic block diagram showing a fourth embodiment of a common buffer type ATM switch according to the present invention.

FIG. 9 is a flowchart showing an operation at the time of a cell read process in the fourth embodiment.

FIG. 10 is a schematic block diagram showing a fifth embodiment of a common buffer type ATM switch according to the present invention.

FIG. 11 is a flowchart showing an operation at the time of a cell write process in the fifth embodiment.

FIG. 12 is a flowchart showing an operation at the time of a cell read process in the fifth embodiment.

FIG. 13 is a schematic block diagram showing Embodiment 6 of a common buffer type ATM switch according to the present invention.

FIG. 14 is a flowchart showing an operation during a cell write process according to the sixth embodiment.

FIG. 15 is a schematic block diagram showing a conventional common buffer type ATM switch.

[Explanation of symbols]

1 multiplexer (MUX), 2 demultiplexer (DMUX), 3 common buffers, 11 free address pool, 12 address queue, 13 write controller,
14 read control unit, 15 write / read pointer table, 16 queue monitoring unit, 17 write pointer, 1
8 read pointer, 19 address group number monitoring unit, 20 broadcast cell counter, 21 pointer reading unit.

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[Procedure amendment]

[Submission date] January 11, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

1. A common buffer for temporarily storing cells input from an incoming line and output from an outgoing line provided for each destination, and address information for holding address information on addresses of the common buffer in which no cells are stored. A pool, an address information queue for holding the address information on the address of the common buffer in which cells are stored in a first-in first-out manner for each outgoing line, and acquiring address information from the address information pool based on cells input from the incoming line. Write control means for accumulating the cell at the address of the common buffer specified by the address information and registering the address information extracted from the address information pool in the address information queue corresponding to the destination of the cell; Address information corresponding to outgoing lines that can be transmitted Based on the head address information registered in the queue, the cell extracted from the common buffer is output from the outgoing line, and when all the addresses managed by the address information become free addresses, the address information is replaced with the address. Read control means for returning to the address information pool, wherein the write control means and the read control means perform address management of the common buffer in units of a group composed of one or a plurality of addresses, and obtain information on each group. A common buffer type asynchronous transfer mode switch, wherein the cell information stored in each address managed by the address information registered in the address information queue is managed by pointer information.

Wherein said write control means and said read control means, shared buffer asynchronous transfer mode switch according to claim 1, wherein the managing the pointer information so as to correspond to each of the address information.

3. The write control means according to claim 1, wherein when an empty address in which no cell is stored exists in an address managed by the last address information held in each of said address information queues, it intends to accumulate cells in the empty address managed by the address information, according to claim 1, wherein the point to the end of the address cell is accumulated in the end of the address information by the write pointer Common buffer type asynchronous transfer mode switch.

Wherein said reading control means, the causes are sequentially output cells stored in the address managed by the head address information held in the address information queue, the cell in the first address information 3. The common buffer type asynchronous transfer mode switch according to claim 2 , wherein the end of the read address is indicated by a read pointer.

Wherein said write control means is newly address managed by the single address information held in the address information queue vacant address by the cell is delivered by the read control means shared buffer asynchronous transfer mode switch according to claim 1, wherein the storing the input cell.

6. have a queue monitoring means for monitoring usage of said each address information queue, the write control means, from among the address information pool number of addresses managed holds said different address information shared buffer asynchronous transfer mode switch according to claim 1, wherein the obtaining the address information to be registered in the respective address information queue according to the usage status of each address information queue.

7. The queue monitoring unit monitors a queue length of each of the address information queues, and the write control unit controls the address information corresponding to the queue length monitored by the queue monitoring unit. 7. The common buffer type asynchronous transfer mode switch according to claim 6, wherein address information to be registered in the queue is determined.

Wherein said write control means and said read control unit holds the pointer information by the destination, the read control means, the first address information registered in the address information queue by that dispatched the cell In the determination as to whether or not to return to the address information pool, a read pointer indicating the end of the address from which the cell was read in the head address information,
If the value of the write pointer indicating the end of the address where the cell is stored is equal in the last address information registered in the address information queue, other address information is registered in the address information queue. shared buffer asynchronous transfer mode switch according to claim 1, wherein the added condition of returning to the address information pool only the address information of the absence.

Wherein said write control means takes out the address information to be managed only a single address when the cell inputted from the incoming line were broadcast cell for multiple destination from the address information Pool Registering in the address information queue corresponding to the destination of the cell and setting the number of destinations of the broadcast cell in the broadcast cell counter, the read control means sets the broadcast cell every time the broadcast cell is transmitted. subtracting the cell counter, the shared buffer asynchronous transfer mode switch according to claim 1, wherein the returning the address information in the address information pool when the multicast cell counter becomes zero.

Wherein said write control means, shared buffer asynchronous transfer mode switch according to claim 2, wherein examining the pointer information corresponding to the address information when retrieving address information from the address information Pool .

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Deleted

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction contents]

[0017]

Means for Solving the Problems Achieving the above objects
To achieve this, the common buffer type asynchronous transfer mode switch according to the first invention has a common buffer for temporarily storing cells input from an input line and output from an output line provided for each destination, and cells stored therein. An address information pool that holds address information about the address of the common buffer, an address information queue that holds address information about the address of the common buffer in which cells are stored for each line in a first-in first-out manner, and an address information queue that is input from an incoming line. Address information is obtained from the address information pool based on the cell, the cell is stored in the address of the common buffer specified by the address information, and the address information extracted from the address information pool corresponds to the destination of the cell. Write system for registering in the address information queue Means for outputting a cell taken out from the common buffer from the outgoing line based on the first address information registered in the address information queue corresponding to the outgoing line from which the cell can be transmitted, and managed by the address information. Read-out control means for returning the address information to the address information pool when all the available addresses become free addresses, wherein the write control means and the read-out control means perform one or more address management of the common buffer. Is performed for each group constituted by the addresses of the addresses, the information regarding each group is treated as the address information, and the cell accumulation status at each address managed by the address information registered in the address information queue is managed by the pointer information. Is what you do.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

According to a second aspect of the present invention, there is provided a common buffer type asynchronous transfer mode switch according to the first aspect , wherein the write control means and the read control means manage the pointer information in association with each of the address information. It is.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction contents]

According to a third aspect of the present invention, in the common buffer type asynchronous transfer mode switch according to the first aspect , the write control means is arranged so that a free address in which no cell is stored is held in each of the address information queues. If the cell exists in the address managed by the tail address information, the cell is stored in the free address managed by the address information, and the cell is stored in the tail address information. The end of the address is indicated by a write pointer.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction contents]

According to a fourth aspect of the present invention, there is provided a common buffer type asynchronous transfer mode switch according to the second aspect , wherein the read control means comprises an address managed by the first address information held in each address information queue. , And sequentially outputs the cells stored in the first address information, and indicates the end of the address from which the cell was read in the start address information by a read pointer.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction contents]

According to a fifth aspect of the present invention, there is provided the common buffer type asynchronous transfer mode switch according to the first aspect , wherein the write control means comprises: The newly input cell is stored at an address managed by only one piece of address information held in the queue.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

The shared buffer asynchronous transfer mode switch according to the sixth invention, in the first aspect, has a queue monitoring means for monitoring usage of said each address information queue, the write control unit manages The address information to be registered in each of the address information queues is obtained from the address information pool holding the address information having a different number of addresses according to the use status of each of the address information queues.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0023

[Correction method] Change

[Correction contents]

[0023] The seventh shared buffer asynchronous transfer mode switch according to the present invention, in the sixth invention, the queue monitoring means, said monitors the queue length of each address information queue, the write control means, The address information to be registered in the address information queue corresponding to the queue length monitored by the queue monitoring means is determined.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction contents]

According to an eighth aspect of the present invention, in the common buffer type asynchronous transfer mode switch according to the first aspect , the write control means and the read control means hold the pointer information for each destination, and the read control means, In determining whether or not to return the first address information registered in the address information queue to the address information pool by transmitting the cell, the first address information indicates the end of the address from which the cell was read in the first address information. If the value of the read pointer is equal to the value of the write pointer indicating the end of the address where the cell is stored in the last address information registered in the address information queue, another address information is stored in the address information queue. The address information is stored only when the address information is not registered. It is obtained by adding a condition of returning to Lumpur.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0025

[Correction method] Change

[Correction contents]

According to a ninth aspect of the present invention, there is provided a common buffer type asynchronous transfer mode switch according to the first aspect , wherein the write control means is configured to perform a single transfer operation when a cell input from an incoming line is a broadcast cell for a large number of destinations. Address information for which only one address is to be managed is extracted from the address information pool, registered in each of the address information queues corresponding to the destination of the cell, and the number of destinations of the broadcast cell is set in the broadcast cell counter. The read control means decrements the broadcast cell counter each time the broadcast cell is transmitted, and returns the address information to the address information pool when the broadcast cell counter becomes 0. .

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction contents]

According to a tenth aspect of the present invention, in the common buffer type asynchronous transfer mode switch according to the second aspect , the write control means, when extracting address information from the address information pool, stores pointer information corresponding to the address information. It is to be inspected.

Claims (11)

[Claims] 1. A common buffer type asynchronous transfer mode for temporarily storing cells transmitted via any one of a plurality of input lines in a free address area of a common buffer provided commonly to output lines provided for each destination. In the switch, the common buffer type asynchronous transfer mode switch is characterized in that address management in the common buffer is performed on a group basis. 2. A common buffer for temporarily storing cells input from an incoming line and output from an outgoing line provided for each destination, and address information for holding address information relating to an address of the common buffer in which no cells are stored. A pool, an address information queue for holding the address information on the address of the common buffer in which cells are stored in a first-in first-out manner for each outgoing line, and acquiring address information from the address information pool based on cells input from the incoming line. Write control means for accumulating the cell at the address of the common buffer specified by the address information and registering the address information extracted from the address information pool in the address information queue corresponding to the destination of the cell; Address information corresponding to outgoing lines that can be transmitted Based on the head address information registered in the queue, the cell extracted from the common buffer is output from the outgoing line, and when all the addresses managed by the address information become free addresses, the address information is replaced with the address. Read control means for returning to the address information pool, wherein the write control means and the read control means perform address management of the common buffer for each group composed of one or a plurality of addresses, and obtain information on each group. A common buffer type asynchronous transfer mode switch, wherein the cell information stored in each address managed by the address information registered in the address information queue is managed by pointer information. 3. The common buffer type asynchronous transfer mode switch according to claim 2, wherein said write control means and said read control means manage said pointer information in correspondence with each of said address information. 4. The write control unit according to claim 1, wherein when an empty address in which no cell is stored exists in an address managed by the last address information held in each of said address information queues, 3. The method according to claim 2, further comprising accumulating cells at a vacant address managed by the address information, and pointing to the end of the address at which the cells are stored in the last address information by a write pointer. Common buffer type asynchronous transfer mode switch. 5. The read control means sequentially outputs cells stored at an address managed by the first address information held in each of the address information queues, and outputs the cells in the first address information. 4. The common buffer type asynchronous transfer mode switch according to claim 3, wherein the end of the read address is indicated by a read pointer. 6. The write control means according to claim 1, wherein said write control means newly adds an address managed by only one address information held in said address information queue to a vacant address when a cell is transmitted by said read control means. 3. The common buffer type asynchronous transfer mode switch according to claim 2, wherein the cells input to the switch are stored. 7. A queue monitoring unit for monitoring a use status of each of the address information queues, wherein the write control unit selects one of the address information pools holding the address information having a different number of addresses to be managed. 3. The common buffer type asynchronous transfer mode switch according to claim 2, wherein the address information to be registered in each of the address information queues is acquired according to the use status of each of the address information queues. 8. The queue monitoring means monitors a queue length of each of the address information queues, and the write control means controls the address information corresponding to the queue length monitored by the queue monitoring means. 8. The common buffer type asynchronous transfer mode switch according to claim 7, wherein address information to be registered in the queue is determined. 9. The write control unit and the read control unit hold the pointer information for each destination, and the read control unit stores the first address information registered in the address information queue by transmitting a cell. In the determination as to whether or not to return to the address information pool, a read pointer indicating the end of the address from which the cell was read in the head address information,
When the value of the write pointer indicating the end of the address where the cell is stored is equal in the last address information registered in the address information queue, other address information is registered in the address information queue. 3. The common buffer type asynchronous transfer mode switch according to claim 2, wherein a condition is added that the address information is returned to the address information pool only when there is no address information. 10. The write control unit, when a cell input from an incoming line is a broadcast cell for a large number of destinations, extracts address information for which only a single address is to be managed from the address information pool. Registering in the address information queue corresponding to the destination of the cell and setting the number of destinations of the broadcast cell in the broadcast cell counter, the read control means sets the broadcast cell every time the broadcast cell is transmitted. 3. The common buffer type asynchronous transfer mode switch according to claim 2, wherein a cell counter is decremented and said address information is returned to said address information pool when said broadcast cell counter becomes zero. 11. The common buffer type asynchronous transfer mode switch according to claim 3, wherein said write control means checks the pointer information corresponding to the address information when extracting the address information from the address information pool. .