JPH11213697A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently lay out a synchronous DRAM(dynamic random access memory), etc., which is adapted to be switchable optionally in bit constitution and has a degeneration test function. SOLUTION: In this storage device, for instance, 8 bits of 16-bit write data buses WBOB-WBFB and read data buses RBOB-RBFB set between a write amplifier WA and a main amplifier MA of banks BNK0-BNK3, and a data input buffer DIB and a data output buffer DOB are fixedly formed irrespective of a bit constitution and shared for constituting ×4 bits and ×8 bits. The remaining 8 bits are selectively formed only at the time of ×16 bits for metal option. These data buses are used also as test data buses for a degeneration test. Moreover, a data selection circuit for switching a data transmission path through selective bonding, namely, an output mutiplexer MXO, an input multiplexer MXI and an input data selection circuit IS are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a synchronous DRAM (dynamic random access memory) having a bit configuration that can be selectively switched and having a reduction test function, and a layout of the DRAM. The present invention relates to a technique that is particularly effective for improving efficiency and reducing the chip size.

[0002]

2. Description of the Related Art There is a so-called synchronous DRAM in which a memory array in which dynamic memory cells are arranged in a lattice is used as a basic component thereof and operates synchronously in accordance with a predetermined clock signal. These synchronous DRAMs
In many cases, a multi-bit configuration is used to simultaneously input or output a plurality of bits of storage data, and a plurality of external terminals and a data bus are provided corresponding to each bit of the storage data. Further, the synchronous DRAM has a bit configuration of, for example, × 4 bits, × 4 bits according to user specifications.
In many cases, the configuration can be optionally switched to 8 bits or × 16 bits, etc., thereby increasing the efficiency of product development.

[0003] On the other hand, with the recent advances in the technology for miniaturization and high integration of integrated circuits, synchronous DRAMs and the like have been increasing in scale and capacity, and this has been realized without impairing the high-speed performance. As one means for achieving this, a memory mat including a memory array and a direct peripheral circuit is divided into multiple sections. In addition, as one means for efficiently performing a functional test of a synchronous DRAM or the like having a large scale, a large capacity, and a multiplicity of memory mats, test data is simultaneously written to and read from a plurality of memory mats. There is a so-called contraction test (multi-bit test) method for comparison and collation.

[0004]

Prior to the present invention, the inventors of the present invention have developed a synchronous DRAM having a configuration in which the bit configuration can be selectively switched and having a reduction test function. I noticed the following problems. That is, this synchronous DRAM
Has, for example, four banks, and each bank has 16 memory mats, each of which is divided into a total of 64 memory mats. In addition, the synchronous DRAM can have an optional bit configuration of × 4 bits, × 8 bits or × 16 bits according to user specifications, and simultaneously writes test data to a total of 64 memory mats. It has a reduction test function that can be read out and compared. Each bank of the synchronous DRAM has 16 write amplifiers and main amplifiers provided corresponding to each memory mat, and two reduction amplifiers for comparing and collating reduction test data output from eight main amplifiers. Test circuit.

However, in the synchronous DRAM, data buses required for normal operation, that is, a write data bus and a read data bus for connecting between a write amplifier and a main amplifier of each bank and a data input buffer and a data output buffer are provided. Since the data bus required for the reduction test, that is, the test data bus for connecting the reduction test circuit of each bank and the data output buffer is separately provided, the required area of the bus layout is increased, thereby increasing the synchronization. The chip size of the eggplant DRAM increases. Further, in this synchronous DRAM, the switching of the bit configuration is all performed by selectively forming a metal option, that is, a predetermined metal wiring layer, so that the number of steps for layout design and verification thereof increases.

SUMMARY OF THE INVENTION An object of the present invention is to make layout design and verification of a synchronous DRAM or the like having a configuration in which a bit configuration can be selectively switched and have a reduction test function efficient, and to reduce its chip size. .

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, for example, in a synchronous DRAM or the like having a configuration in which the bit configuration can be switched as an option and having a reduction test function, for example, provided between a write amplifier and a main amplifier of each bank and a data input buffer and a data output buffer. Eight bits of the 16-bit data bus are fixedly formed irrespective of the bit configuration and shared for the × 4 bit and × 8 bit configuration, and the remaining 8 bits are selectively available only when the metal option is × 16 bit. Formed. In addition, these data buses are used together as test data buses for reduction tests, and bonding options, that is, bonding between predetermined pads, is selectively performed on the external terminal side, the write amplifier side, and the main amplifier side. A data selection circuit for switching the data transmission path.

According to the above means, the required number of data buses can be reduced, the required area of the layout can be reduced, the chip size of the synchronous DRAM can be reduced, and the layout design man-hour for switching the bit configuration and its layout can be reduced. The number of verification steps can be reduced, and the layout of the synchronous DRAM can be made more efficient.

[0010]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM (semiconductor memory device) to which the present invention is applied. First, an outline of the configuration and operation of the synchronous DRAM of this embodiment will be described with reference to FIG. Although the circuit elements constituting each block in FIG. 1 are not particularly limited, a well-known MOSFET (metal oxide semiconductor type field effect transistor. In this specification, a MOSFET is a generic name of an insulated gate type field effect transistor). Is formed on one semiconductor substrate surface, such as single crystal silicon, by an integrated circuit manufacturing technique.
Further, the synchronous DRAM of this embodiment has an optional bit configuration of × 4 bits, as will be described later.
It is possible to switch to the × 8 bit or × 16 bit configuration. FIG. 1 shows the external terminal and bus configuration in the × 16 bit configuration.

In FIG. 1, the synchronous DRAM of this embodiment is not particularly limited, but includes four banks BNK.
0 to BNK3. Each of these banks includes a memory array MARY arranged to occupy most of the layout area, and a row address decoder RD, a sense amplifier SA, and a column address decoder C which are directly peripheral circuits.
D, a write amplifier WA, a main amplifier MA, an input data selection circuit IS (second data selection circuit), and a reduction test circuit TC.

In this embodiment, banks BNK0-BNKB
The memory array MARY constituting NK3 and its direct peripheral circuits are actually divided into 16 memory mats. The write amplifier WA, the main amplifier MA, and the input data selection circuit IS are divided into 16 unit circuits corresponding to the respective memory mats. Correspondingly, two are provided for each bank. This will be described later in detail.

The memory array MARY forming the banks BNK0 to BNK3 includes a predetermined number of word lines arranged in parallel in the vertical direction in the drawing and a predetermined number of complementary bit lines arranged in parallel in the horizontal direction. Respectively. At the intersections of these word lines and complementary bit lines, a number of dynamic memory cells each composed of an information storage capacitor and an address selection MOSFET are arranged in a lattice.

The word lines constituting the memory array MARY of the banks BNK0 to BNK3 are coupled to the corresponding row address decoders RD, and each of them is selectively selected. Although not particularly limited, these row address decoders RD are commonly supplied with 12-bit internal address signals X0 to X11 from a row address register RA, and commonly supplied with an internal control signal RG (not shown) from a timing generation circuit TG. You. The row address register RA has address signals A0 to A1 that become X address signals AX0 to AX11 via an address buffer AB.
1 is supplied, and the internal control signal RL is supplied from the timing generation circuit TG. To the address buffer AB, a 12-bit X address signal AX0 to AX11 and a 10-bit Y address signal AY0 to AY9 are supplied in time division from an external access device via address input terminals A0 to A11. Two-bit bank address signals BA0 to BA1 are supplied through A12 to A13.

The address buffer AB includes a 12-bit X address signal AX0-AX11 input via address input terminals A0-A13, a 10-bit Y address signal AY0-AY9, and a 2-bit bank address signal BA0-BA1. And transmits it to the row address register RA, the column address counter CC, and the bank address register BA. In addition, synchronous DR
When AM is set to a mode register set cycle, a 14-bit mode control signal is supplied to the address input terminals A0 to A13, and these mode control signals are transmitted to the mode register MR via the address buffer AB. You. An internal control signal BL is further supplied to the bank address register BA from the timing generation circuit TG,
An internal control signal MS not shown in the mode register MR
Is supplied.

When a mode register set command is executed, the mode register MR sets an address input terminal A0.
The mode control signal input through .about.A13 is fetched and held in accordance with the internal control signal MS. Further, these mode control signals are decoded to determine the operation mode of the synchronous DRAM, and a mode control signal including the test control signal TP is selectively formed and supplied to each section of the synchronous DRAM.

The bank address register BA takes in and holds bank address signals BA0 to BA1 transmitted as address signals A12 to A13 from the address buffer AB according to the internal control signal BL, and selects a bank as the internal bank address signals B0 to B1. Circuit BS
To communicate. The bank selection circuit BS receives internal control signals WAE, MAE and MO from the timing generation circuit TG.
E is supplied, a test control signal TP is supplied from the mode register MR, and an internal signal BPX4 is supplied from a bit configuration switching circuit BC described later. Among them, the internal control signals WAE and MAE are control signals for setting operation timings of the write amplifier WA and the main amplifier MA, respectively, and the internal control signal MOE is
Read data bus RB0B of main amplifier MA, which will be described later.
To RBFB to set the output timing. The test control signal TP is synchronous D
A mode control signal which is selectively set to a high level when the RAM is set to the contraction test mode.
Is a bit configuration switching control signal which is selectively set to a high level when the synchronous DRAM has a × 4 bit configuration.

Based on the decoding results of the internal bank address signals B0 to B1 and the logical levels of the test control signal TP and the internal control signal BPX4, the bank selection circuit BS writes a write amplifier drive signal WAEn (where n is 0). Or 15
That is, it is an integer between F), the main amplifier drive signal MA
En and the main amplifier output control signal MOEn (first
Corresponding to a predetermined number of bits selectively and in synchronization with the internal control signals WAE, MAE or MOE, respectively, and a bank selection signal B (not shown).
Bits corresponding to S0 to BS3 are selectively set to a high level in a predetermined combination. Among them, the write amplifier drive signal WAEn is supplied to the corresponding unit write amplifiers UWA0 to UWAF of the write amplifier WA described later, and the main amplifier drive signal MAEn and the main amplifier output control signal MOEn are output to the corresponding unit main amplifier MA of the main amplifier MA. It is supplied to amplifiers UMA0-UMAF. The bank selection signals BS0 to BS3 correspond to the corresponding banks BNK0 to BNK.
3 are supplied to the row address decoder RD, the column address decoder CD, and the sense amplifier SA.

Row address register RA receives X address signals AX0-AX11 transmitted as address signals A0-A11 from address buffer AB to internal control signal R.
In accordance with L, the data is held and held, and based on these X address signals, internal address signals X0 to X11 are formed and supplied to the row address decoders RD of the banks BNK0 to BNK3. Row address decoder R of each bank
D is selectively activated when the internal control signal RG is set to the high level and the corresponding bank selection signals BS0 to BS3 are set to the high level, and the internal address signal X0 supplied from the row address register RA is set. ~ X
11 is decoded, and the designated word line of the corresponding memory array MARY is alternatively selected.

The test control signal TP is supplied from the mode register MR to the bit configuration switching circuit BC, and the internal control signal TO is supplied from the timing generation circuit TG.
E (second output control signal) is supplied. The bit configuration switching circuit BC is further coupled to a predetermined pad PB, and this pad PB is selectively coupled to another predetermined pad, that is, a ground potential supply pad PVEE via a bonding wire BW. The bonding wire BW is used for optionally switching the bit configuration of the synchronous DRAM.
When the RAM is desired to have a × 4 bit configuration, the combining process is selectively performed.

The bit configuration switching circuit BC includes a pad P
When bonding between B and PVEE is performed and the synchronous DRAM has a × 4 bit configuration, an output signal thereof, that is, an internal signal TBX4 is selectively set to a high level on condition that the test control signal TP is at a low level. Further, when the synchronous DRAM has a × 4 bit configuration or the test control signal TP is set to the high level by setting the synchronous DRAM to the reduced test mode, the internal signal BPX4 is selectively set to the high level, When the internal signal BPX4 is set to the high level or the internal control signal TOE is set to the high level, the internal signal TPX is selectively turned on.
X4 is set to a high level. The specific configuration of the bit configuration switching circuit BC will be described later in detail.

Next, the complementary bit lines constituting the memory array MARY of the banks BNK0 to BNK3 are respectively coupled to the corresponding sense amplifiers SA. The sense amplifier SA of each bank has a corresponding column address decoder C
D supplies a predetermined number of bit line selection signals, and an internal control signal P from a timing generation circuit TG.
C and PA are supplied in common. Internal address signals Y0 to Y9 are commonly supplied from a column address counter CC to a column address decoder CD of each bank, and internal control signals YS and CG (not shown) are supplied from a timing generation circuit TG. The column address counter CC has an address signal A from the address buffer AB.
The Y address signals AY0 to AY9 are supplied as 0 to A9, and the internal control signal CL is supplied from the timing generation circuit TG.
Is supplied.

The column address counter CC includes a binary counter that performs a stepping operation according to an internal control signal CC (not shown). This binary counter includes Y address signals AY0 to AY0 supplied from an address buffer AB.
AY9 is fetched and held according to the internal control signal CL. A stepping operation is performed using these Y address signals AY0 to AY9 as initial values, and internal address signals Y0 to YY9 are used.
9 are sequentially formed and supplied to the column address decoders CD of the banks BNK0 to BNK3.

The column address decoders CD of the banks BNK0 to BNK3 are selectively activated when the internal control signal CG is at a high level and the corresponding bank selection signals BS0 to BS3 are at a high level.
The internal address signals Y0 to Y9 are decoded, and the designated bit of the bit line selection signal for the sense amplifier SA is set to a high level alternatively and in synchronization with the internal control signal YS.

The sense amplifiers SA of the banks BNK0 to BNK3 include a predetermined number of unit circuits provided corresponding to respective complementary bit lines of the corresponding memory array MARY. Each of these unit circuits is an N-channel type And a pair of CMOS (complementary MOS)
S) a unit amplifier circuit in which inverters are cross-coupled;
A pair of N-channel switch MOSFETs. Among these, the precharge MOSFETs constituting the bit line precharge circuit of each unit circuit are selectively turned on in response to the high level of the internal control signal PC, and the non-inversion of each complementary bit line of the corresponding memory array MARY is performed. And the inversion signal line is precharged to an intermediate voltage.

On the other hand, the unit amplifier circuit of each unit circuit of the sense amplifier SA selectively and simultaneously operates when the internal control signal PA is at a high level and the corresponding bank selection signals BS0 to BS3 are at a high level. In the operating state, a small read signal output from a predetermined number of memory cells coupled to a selected word line of the corresponding memory array MARY via the corresponding complementary bit line is amplified to produce a high-level or low-level binary signal. This is a read signal. The switch MOSFET of each unit circuit is set to 1 by selectively setting the corresponding bit of the bit line selection signal to a high level.
6 sets are selectively turned on, and the memory array MAR is turned on.
The 16 sets of complementary bit lines corresponding to Y and the complementary common data lines CD0 * to CDF * (here, for example, the non-inverted common data line CD0T and the inverted common data line CD0B are combined like the complementary common data line CD0 *) In addition, a so-called non-inverted signal which is selectively set to a high level when it is made valid is indicated by a T suffix.
The inverted signal which is selectively set to low level when it is valid is denoted by a B suffix at the end of its name.
And is represented by The same applies to the following).

The complementary common data lines CD0 * to CDF * are
It is coupled to the output terminal of each unit write amplifier of the corresponding write amplifier WA, and is also coupled to the input terminal of each unit main amplifier of the corresponding main amplifier MA.

Write amplifier WA and main amplifier MA
Correspond to the complementary common data lines CD0 * to CD0
There are 16 unit write amplifiers and unit main amplifiers provided corresponding to F *. Of these, the input terminals of each unit write amplifier of the write amplifier WA are commonly coupled to the write data buses WB0B to WBFB via the corresponding input data selection circuit IS, and the main amplifier MA
The output terminal of each unit main amplifier is directly coupled to read data buses RB0B to RBFB, and is also coupled to the input terminal of corresponding reduction test circuit TC. The output terminal of each reduction test circuit TC is connected to the read data bus RB0B to
It is coupled to a predetermined bit of RBFB. The test control signal TP is supplied from the mode register MR to the input data selection circuit IS, and the corresponding write amplifier drive signal WAEn is supplied from the bank selection circuit BS to each unit write amplifier of the write amplifier WA. Each unit main amplifier of the main amplifier MA includes a bank selection circuit BS.
Supplies the corresponding main amplifier drive signal MAEn and the main amplifier output control signal MOEn from the mode register MR.
P is supplied, and the internal control signal TOE is supplied from the timing generation circuit TG.

On the other hand, write data buses WB0B-WBF
B are respectively coupled to the output terminals of the corresponding unit input multiplexers of the input multiplexer MXI (first data selection circuit), and read data buses RB0B to RBFB
Are coupled to the input terminals of the corresponding unit output multiplexer of the output multiplexer MXO (third data selection circuit). The input terminal of each unit input multiplexer of the input multiplexer MXI is connected to the data input buffer D.
The output terminal of each unit output multiplexer of output multiplexer MXO is coupled to the input terminal of the corresponding unit data output buffer of data output buffer DOB. An input terminal of each unit data input buffer of the data input buffer DIB and an output terminal of each unit data output buffer of the data output buffer DOB are external terminals for inputting or outputting storage data, that is, data input / output terminals D0.
To DF. The internal signals BPX4 and TBX4 are supplied to each unit input multiplexer of the input multiplexer MXI, and the internal signal TXX is supplied to each unit output multiplexer of the output multiplexer MXO.
4 are commonly supplied. Also, the data output buffer DO
The internal control signal DOC is commonly supplied from the timing generation circuit TG to each of the B unit data output buffers.

Each unit data input buffer of the data input buffer DIB stores data input / output terminals D0-D when the synchronous DRAM is selected in the write mode.
F, and receives and holds a total of 16 bits of write data input through the input multiplexer M.
The data is transmitted to write data buses WB0B to WBFB via XI. At this time, the input multiplexer MXI converts the write data transmitted from the corresponding unit data input buffer of the data input buffer DIB into the internal signal BPX4.
And TBX4, that is, the write data bus WB0 in a predetermined combination according to the bit configuration of the synchronous DRAM.
B to WBFB, and the input data selection circuit IS of each bank further transmits these write data to the write amplifier WA in a predetermined combination according to the test control signal TP.

Each of the unit write amplifiers of the write amplifier WA selectively receives the high level of the corresponding write amplifier drive signal WAEn, and selectively operates, and is transmitted from the corresponding unit data input selection circuit of the input data selection circuit IS. After converting the write data into a predetermined complementary write signal, the write data is written to the selected 16 memory cells of the corresponding memory array MARY via the complementary common data lines CD0 * to CDF *. The combination of the input / output terminals D0 to DF and the write data in each bit configuration, the input multiplexer MXI, and the input data selection circuit I
About the specific configuration of S and the light amplifier WA,
Details will be described later.

Next, each unit main amplifier of the main amplifier MA of each bank receives a corresponding main amplifier drive signal MA
In response to the high level of En, the memory cells are selectively activated to amplify the read signals output from the selected 16 memory cells of the corresponding memory array MARY via the complementary common data lines CD0 * to CDF *. . These read data are transmitted from the main amplifier MA to the corresponding read data buses RB0B to RBFB by setting the corresponding main amplifier output control signal MOEn to a high level.
And to the reduction test circuit TC.

The contraction test circuit TC compares and compares 8-bit data output from the corresponding eight unit main amplifiers of the main amplifier MA, and places the result in designated bits of the read data buses RB0B to RBFB. Output. The output signal of the contraction test circuit TC is selectively set to a low level when the corresponding 8-bit test data matches all bits of logic "0" or "1". About the combination of the reduction test circuit TC and the unit main amplifier of the main amplifier MA to be tested, the combination of the output signal of the reduction test circuit TC and the read data buses RB0B to RBFB, and the specific configuration of the reduction test circuit TC Will be described later in detail.

Each unit output multiplexer of the output multiplexer MXO is connected to each unit main amplifier or the reduction test circuit T of the main amplifier MA of the banks BNK0 to BNK3.
C outputs the read data output from the read data buses RB0B to RBFB or the reduction test result to the internal signal TX.
4, that is, selectively combined according to the bit configuration of the synchronous DRAM and transmitted to the corresponding unit data output buffer of the data output buffer DOB. Each unit data output buffer of the data output buffer DOB is selectively operated in response to the high level of the internal control signal DOC, and the read data or reduction test result transmitted from the corresponding unit output multiplexer of the output multiplexer MXO. Is output from the corresponding data input / output terminals D0 to DF to an external access device or test device. The specific configuration of each unit output multiplexer of the output multiplexer MXO will be described later in detail.

The timing generation circuit TG includes a chip selection signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and an input / output mask signal DQM supplied as a start control signal from an external access device. The various internal control signals are selectively formed based on the clock signal CLK and the clock enable signal CKE, and are supplied to each unit.

FIG. 2 is a block diagram showing one embodiment of the bank BNK0 included in the synchronous DRAM of FIG. Based on the figure, the synchronous DRAM of FIG.
Will be described with reference to the mat configuration of the banks BNK0 to BNK3 and the bit allocation in each bit configuration. In the following description, the banks BNK0 to BNK3 will be described using the bank BNK0 in FIG.
〜BNK3 have the same or symmetric configuration as the bank BNK0, and should be analogized.

In FIG. 2, the memory array MARY forming the bank BNK0 is divided into 16 memory mats MAT0 to MATF including a row address decoder RD, a column address decoder CD and a sense amplifier SA, which are direct peripheral circuits. Is done. Of these, eight memory mats MAT0 to MAT7 are sequentially arranged from the right side to the left side in the drawing, and every other memory mats MAT0 to MAT7 are arranged between these memory mats.
TFs are arranged in reverse order. As will be described later, the reduction test of the synchronous DRAM is performed on eight memory mats MAT0.
ＭＡMAT7 or MAT8ＭＡMATF, the same test data is written. By arranging these memory mats alternately, data between adjacent memory mats is converted into a mosaic pattern, that is, a logic “0” or It can be set to “1”, which can enhance the abnormality detection effect of the reduction test.

When the synchronous DRAM has a × 4 bit configuration, the first bit D0 of the input / output data is not particularly limited, but is not limited to four memory mats MAT0 and MAT.
1, MATE and MATF are assigned, and the second bit D1 has four memory mats MAT4 and MATF.
T5, MATA and MATB are assigned. Four memory mats MAT6 to MAT9 are allocated to the third bit D2 of the input / output data, and four memory mats MAT2 and MAT are allocated to the fourth bit D3.
3, MATC and MATD are assigned.

On the other hand, when the synchronous DRAM has a × 8-bit configuration, two memory mats MAT0 and MAT1 are allocated to the first bit D0 of the input / output data, and the second to eighth bits D1 to D7 are assigned. Have two memory mats MAT2 and MAT3 and MAT4, respectively.
And MAT5, MAT6 and MAT7, MAT8 and M
AT9, MATA and MATB, MATC and MATD
MATE and MATF are sequentially assigned.
Further, when the synchronous DRAM has a × 16 bit configuration, the first bit D0 of the input / output data is allocated to one memory mat MAT0,
Bits D1 to DF are assigned to corresponding one memory mats MAT1 to MATF, respectively.

As described above, the memory mats MAT0 to MATF, that is, the sense amplifiers SA are coupled to the output terminals of the corresponding unit write amplifiers UWA0 to UWAF of the write amplifier WA0 via the complementary common data lines CD0 * to CDF *. At the same time, they are coupled to the input terminals of the corresponding unit main amplifiers UMA0 to UMAF of the main amplifier MA0. Unit of write amplifier WA0 Write amplifier UW
The input terminals of A0 to UWAF have input data selection circuits I
S0 (here, the input data selection circuit I of the bank BNK0)
S is indicated by adding an additional number 0 of the bank BNK0 corresponding to the end of the name. The same applies to the following) inverted output signals WD0B to WDFB of the corresponding unit data input selection circuits, and input terminals of these unit data input selection circuits are respectively coupled to corresponding write data buses WB0B to WBFB.

On the other hand, one output terminal of unit main amplifiers UMA0 to UMAF of main amplifier MA0 is connected to corresponding read data buses RB0B to RBFB. In addition, eight unit main amplifiers UM of the main amplifier MA0
The inverted output signals TO0B to TO7B at the other output terminals of A0 to UMA7 are supplied to a contraction test circuit TC00, and the inverted test output signals TO8B to T8 at the other output terminals of the remaining eight unit main amplifiers UMA8 to UMAF.
OFB is supplied to the contraction test circuit TC01. As described above, two reduction test circuits TC are provided for each bank, and the numbers thereof are TC0 corresponding to the additional numbers of the banks.
0 and TC01, TC10 and TC11, TC20 and TC21, and TC30 and TC31.

In this embodiment, the contraction test circuit TC0
0, that is, the output signal TD00,
The data is output to the read data bus RB4B and the reduction test circuit T
The output signal TD01 of C01 is the read data bus RBB
B. The output signals TD10 and TD11 of the reduction test circuits TC10 and TC11 constituting the bank BNK1 (not shown)
Output to B6B and RB9B. Furthermore, bank BN
The output signals TD20 and TD21 of the reduction test circuits TC20 and TC21 forming K2 are output to the read data buses RB0B and RBFB, respectively, and are output from the bank BNK3
Are output to the read data buses RB2B and RBDB, respectively. The output signal of each such reduction test circuit and the read data buses RB0B to RB0
The combination with the FB is that the synchronous DRAM
It has the same combination as the storage data transmission path in the case of the 4-bit configuration and the normal operation mode, whereby the circuit configuration of each unit output multiplexer of the output multiplexer MXO described later can be simplified.

Unit of write amplifier WA0 Write amplifier U
WA0 to UWAF have corresponding write amplifier drive signals WAEn from the bank selection circuit BS, that is, WAE0 to WAE.
EF are supplied to the unit main amplifiers UMA0 to UMAF of the main amplifier MA0, and the corresponding main amplifier drive signals MAEn, that is, MAE0 to MAEF, and the main amplifier output control signals MOEn, that is, MOE0 to MOE0.
MOEF is supplied respectively. Further, the reduction test circuit T
The test control signal TP and the internal control signal TOE are commonly supplied from the timing generation circuit TG to C00 and TC01, and the test control signal TP is supplied to the input data selection circuit IS0.
Is supplied. The operation of these control signals and the specific configurations and operations of the unit write amplifiers UWA0 to UWAF of the write amplifier WA0, the unit main amplifiers UMA0 to UMAF of the main amplifier MA0, and the reduction test circuits TC00 and TC01 will be described later in detail. explain.

FIG. 3 is a circuit diagram showing one embodiment of the bit configuration switching circuit BC included in the synchronous DRAM of FIG. FIG. 4 shows a circuit diagram of an embodiment of the input multiplexer MXI included in the synchronous DRAM of FIG. 1, and FIGS. 5 (a) to 5 (c)
The unit input multiplexers UMXI0, UMXI1, and UMXI included in the input multiplexer MXI of FIG.
2, respectively. FIG. 6 is a circuit diagram showing one embodiment of the input data selection circuits IS0 to IS3 included in the synchronous DRAM of FIG.
FIG. 7 is a circuit diagram of an embodiment of the unit data input selection circuit UIS0 included in the input data selection circuit IS0 of FIG. In addition, FIG. 8 shows a write amplifier WA0 and a main amplifier MA0 of the synchronous DRAM of FIG.
FIG. 9 shows a circuit diagram of an embodiment of the unit write amplifier UWA0 and the unit main amplifier UMA0 included in the first embodiment.
A circuit diagram of one embodiment of the contraction test circuit TC00 is shown. FIG. 10 is a circuit diagram of one embodiment of the output multiplexer MXO included in the synchronous DRAM of FIG. 1, and FIG. 11 is a circuit diagram of the output multiplexer MX of FIG.
A circuit diagram of one embodiment of the unit output multiplexer UMXO2 included in the XO is shown.

On the other hand, FIG. 12, FIG. 13 and FIG. 14 show connection diagrams of one embodiment of a data input related circuit included in the synchronous DRAM of FIG. Are shown respectively.
FIG. 15 is a correspondence diagram of an embodiment for explaining the relationship between the write data bus of the synchronous DRAM of FIG. 1 and the unit data input buffer, and FIG. A correspondence diagram of one embodiment for explaining a relationship between an amplifier and a write data bus is shown. Further, FIG. 17, FIG. 18 and FIG.
Connection diagrams of one embodiment of the data output related circuits included in the synchronous DRAM of the .times.4 bit, .times.8 bit and .times.16 bit configurations. FIG. 20 is a corresponding diagram of one embodiment for explaining the relationship between the unit main amplifier of the synchronous DRAM of FIG. 1 and the read data bus, and FIG. FIG. 3 is a correspondence diagram of one embodiment for explaining a relationship between the unit main amplifier and the reduction test circuit. Based on the above figures, the synchronous DR of this embodiment
A specific configuration and operation of each unit of the AM, and a bus configuration and a connection configuration in each bit configuration of the data input related circuit and the data output related circuit will be described.

In the following circuit diagrams, MOSFETs having an arrow at the channel (back gate) portion are of the P-channel type, and are distinguished from N-channel MOSFETs without the arrow. In FIG. 5,
The unit input multiplexers UMXI4, UMXIB and UMXI have the unit input multiplexer UMXI0.
F will be described, and the unit input multiplexers UMXI3, UMXI5, U
MXI7 to UMXIA and UMXIC to UMXIE
And the unit input multiplexer UMXI6 with the unit data input selection circuit UMXI2. Further, FIG. 7 illustrates the unit data input selection circuits UIS0 to UISF of the data input selection circuits IS0 to IS3 with the unit data input selection circuit UIS0, and FIG. 8 illustrates the write amplifier WA0 with the unit write amplifier UWA0 and the unit main amplifier UMA0. To WA3 Unit Write Amplifiers UWA0 to UWAF and Main Amplifiers MA0 to MA
3, the unit main amplifiers UMA0 to UMAF will be described. In FIG.
C01 and TC10 to TC31 will be described with reference to FIG.
1, the unit output multiplexers UMXO2, UMXO9, and UMXOD will be described using the unit output multiplexer UMXO2. Hereinafter, the configuration and operation of each block of the synchronous DRAM and the characteristics thereof will be specifically described with reference to the circuit diagrams of FIGS. 3 to 11, and in the process, FIGS. The connection diagrams and the corresponding diagrams in FIGS. 15 to 16 and FIGS.

In the connection diagrams of FIGS. 12 to 14 and FIGS. 17 to 19, the unit write amplifiers UWA0 to UWAF of the write amplifiers WA0 to WA3 and the main amplifier M
As for the unit main amplifiers UMA0 to UMAF of A0 to MA3, only the additional numbers are shown. FIG. 1 is a connection diagram corresponding to a × 4 bit and × 8 bit configuration.
2 and FIG. 13 and FIG. 17 and FIG. 18, the bits where the write data buses WB0B to WBFB and the read data buses RB0B to RBFB are not formed, that is, the bits that are selectively formed only in the × 16 bit configuration by the metal option are indicated by dotted lines. In the connection diagram shown in FIG. 14 and corresponding to the × 16 bit configuration, that is, in FIG. 14 and FIG.
A cut portion selectively cut off only at the time of the bit configuration is indicated by a cross, and a connection portion selectively connected only at the time of x16 bits is indicated by a double circle.

First, in FIG. 3, the bit configuration switching circuit BC includes, but is not limited to, a CMOS inverter V2 whose input terminal is coupled to the pad PB. The input terminal of the inverter V2 is coupled to the power supply voltage of the circuit via two P-channel MOSFETs P3 and P4 arranged in series, and a P-channel MOS
It is coupled to the supply voltage of the circuit via FET P5. MO
The gates of SFETs P3 and P4 are coupled to the circuit ground potential, and the gate of MOSFET P5 is connected to inverter V2.
Output terminal. The gate of the MOSFET P3 has an inverter V of the inverted internal signal PUPB.
P-channel MOSFETP receiving inverted signal by 1
1 and a P-channel MOSFET P2 whose gate receives the internal signal IDLT are provided in parallel. The MOSFETs P3 and P4 are designed to have a relatively small conductance.

The output terminal of the inverter V2 is connected to the NOR (NO
R) It is coupled to one input terminal of the gate NO1. The test control signal TP is supplied from the mode register MR to the other input terminal of the NOR gate NO1, and its output signal becomes the internal signal BPX4 via the inverter V3. The output signal of the inverter V3 further includes a NAND (NAN).
D) It is supplied to one input terminal of the gate NA1 and the NOR gate NO2. Among them, the inverted signal of the test control signal TP by the inverter V4 is supplied to the other input terminal of the NAND gate NA1, and the internal control signal TOE is supplied from the timing generation circuit TG to the other input terminal of the NOR gate NO2. . The output signal of NAND gate NA1 becomes internal signal TBX4 via inverter V5, and the output signal of NOR gate NO2 becomes internal signal TX4 via inverter V6.

In this embodiment, the pad PB is not particularly limited, but is selectively coupled to the ground potential supply pad PVEE via the bonding wire BW when the synchronous DRAM has a × 4 bit configuration. When the synchronous DRAM has the × 8-bit or × 16-bit configuration, the pad PB is opened and the pad PV
No bonding process with the EE is performed.

When the synchronous DRAM has a .times.4 bit configuration, and pad PB and PVEE are connected via bonding wire BW, the input potential of inverter V2 is set to the ground potential of the circuit, that is, low level, and its output signal is set to the low level. It is set to a high level like the power supply voltage of the circuit. Further, when the synchronous DRAM has a × 8-bit or × 16-bit configuration and the bonding process for the pad PB is not performed, the input terminals of the inverter V2 are connected to the MOSFETs P3 and P4 having relatively small conductance.
, And the output signal is at a low level such as the ground potential of the circuit. Note that the test control signal TP is, as described above, a synchronous DRAM.
Are selectively set to a high level during the reduced test mode, and the internal control signal TOE is selectively set to the high level at a predetermined timing when the synchronous DRAM is set to the reduced test mode.

From these, the internal signal BPX4 is
When either the output signal of the inverter V2 or the test control signal TP is set to a high level, in other words, when the synchronous DRAM has a × 4 bit configuration, or is set to the reduced test mode, it is selectively set to high. Level, and when the synchronous DRAM has a × 8-bit or × 16-bit configuration, or
Is set to the low level when the normal operation mode is set. The internal signal TBX4 is output when the internal signal BPX4 is at a high level and the test control signal TP is at a low level.
The internal signal TX4 has a 4-bit configuration and is selectively set to a high level when the normal operation mode is set. When either the internal signal BPX4 or the internal control signal TOE is set to a high level, in other words, the internal signal TX4 is synchronous. DRA
When M has a × 4 bit configuration, or when the synchronous DRAM is set to the reduction test mode and the internal control signal T
When OE is set to the high level, it is selectively set to the high level.

As described above, the bit configuration switching circuit B
Internal signals BPX4, TBX4, and TX4 formed by C are supplied to predetermined blocks of a synchronous DRAM whose operation changes according to the bit configuration, that is, a bank selection circuit BS, an input multiplexer MXI, an output multiplexer MXO, and the like.

Next, in FIG. 4, the input multiplexer MXI includes 16 unit input multiplexers UMX provided corresponding to the write data buses WB0B to WBFB.
I0 to UMXIF are provided. An internal control signal DIE for data input control is commonly supplied to these unit input multiplexers from the timing generation circuit TG, and inverted output signals DI0B to DI0B to corresponding unit data input buffers UIB0 to UIBF of the data input buffer DIB.
DIFB is supplied respectively.

Unit input multiplexers UMXI0, UM
XI2, UMXI4, UMXI6, UMXIB and the other input terminal of UMXIF are connected to unit data input buffers UIB2, UIBD,
The inverted output signals DI2B, DIDB, DI6B, DI9 from UIB6, UIB9, UIB6 and UIB2.
B, DI6B and DI2B are supplied, respectively.
Also, the unit input multiplexers UMXI0 and UMXI
4, the internal signal BPX4 and its inverted signal by the inverter V7, that is, the inverted internal signal BPX4B are commonly supplied to the UMXIB and the UMXIF from the bit configuration switching circuit BC, and the internal signal TBX4 and its inverter are supplied to the unit input multiplexers UMXI2 and UMXI6. An inverted signal by V8, that is, an inverted internal signal TBX4B is commonly supplied.

Unit input multiplexers UMXI0, UMXI2, UMXI constituting input multiplexer MXI
4, UMXI6, UMXI9, UMXIB, UMXID
The output terminals of the UMXIF are directly connected to the write data buses WB0B, WB2B, WB4B, WB6B,
WB9B, WBBB, WBDB and WBFB, respectively, and other unit input multiplexers UMX
I1, UMXI3, UMXI5, UMXI7, UMXI
8, UMXIA, UMXIC and UMXIE output terminals are connected to corresponding first connection switching circuits CSI1, CSI1,
SI3, CSI5, CSI7, CSI8, CSIA, C
Via the SIC and CSIE, the corresponding write data buses WB1B, WB3B, WB5B, WB7B, WB
8B, WBAB, WBCB and WBEB, respectively.

Note that the synchronous DRAM of this embodiment is
12 has four data input / output terminals D0 to D3 as shown in FIG. 12 when it has a × 4 bit configuration, and FIG. 13 and FIG. 13 when it has a × 8 and × 16 bit configuration. As shown in FIG. 14, eight data input / output terminals D0 to D7 and sixteen data input / output terminals D0 to DF are provided, respectively. Although not particularly limited,
When the synchronous DRAM has a × 4 bit configuration,
The data input / output terminals D0 to D3 are connected to the data input buffer D
IB unit data input buffers UIB2, UIB6, U
IB9 and UIBD respectively. Also,
When the synchronous DRAM has a × 8-bit configuration,
The data input / output terminals D0 to D7 are connected to the data input buffer D
IB unit data input buffers UIB0, UIB2, U
IB4, UIB6, UIB9, UIBB, UIBD, and UIBF, respectively, and have a × 16-bit configuration, the data input / output terminals D0 to DF are connected to the unit data input buffer UIB0 of the data input buffer DIB.
Each corresponds to a UIBF.

Here, the unit input multiplexers UMXI0, UMXI4, UMXI of the input multiplexer MXI are used.
B and UMXIF are not particularly limited.
As represented by the unit input multiplexer UMXI0 in (a), the right side terminal includes a pair of transfer gates G1 and G2 commonly coupled to one input terminal of the NAND gate NA2. The left input terminals of these transfer gates are supplied with the inverted signals of the unit data input buffers UIB0 and UIB2 of the data input buffer DIB and the inverted output signals DI0B and DI2B of the data input buffer DIB by the inverter V9 or VA. The gates of the P-channel MOSFET of the transfer gate G1 and the N-channel MOSFET of the transfer gate G2 are:
The internal signal BPX4 is commonly supplied, and the inverted signal, that is, the inverted internal signal BPX4B is commonly supplied to the gates of the N-channel MOSFET of the transfer gate G1 and the P-channel MOSFET of the transfer gate G2.

The internal control signal DIE is supplied to the other input terminal of the NAND gate NA2 constituting the unit input multiplexer UMXI0, and its output terminal is connected to the write data bus WB0 via two inverters VB and VC.
B.

As a result, when the internal signal BPX4 is at the low level and the inverted internal signal BPX4B is at the high level, that is, when the synchronous DRAM has a × 8-bit or × 16-bit configuration, the write data bus WB0B has As shown on the left side of FIG. 15, on the condition that the internal control signal DIE is at the high level, the inverted output signal DI0B (write data D) of the corresponding unit data input buffer UIB0 of the data input buffer DIB is provided.
0) is transmitted. When the internal signal BPX4 is at a high level and the inverted internal signal BPX4B is at a low level, that is, when the synchronous DRAM has a × 4 bit configuration, the unit is controlled on the condition that the internal control signal DIE is at a high level. Inverted output signal DI2B (write data D0) of input multiplexer UIB2 is transmitted.

Similarly, write data buses WB4B, WB
For BB and WBFB, a synchronous DRAM is used.
In the case of an 8-bit or × 16-bit configuration, the corresponding unit data input buffer U of the data input buffer DIB is provided on condition that the internal control signal DIE is at a high level.
IB4, UIBB and inverted output signal DI of UIBF
When 4B (write data D2 or D4), DIBB (write data D6 or DD) and DIFB (write data D7 or DF) are transmitted, respectively, the internal control signal DIE is also at a high level when it has a × 4 bit configuration. On the condition that the unit input multiplexers UIB6, UIB6 and UIB2 have inverted output signals D
I6B (write data D1), DI6B (write data D1) and DI2B (write data D0) are transmitted.

Next, the unit input multiplexers UMXI1, UMXI3, UMXI of the input multiplexer MXI
5, UMXI7-UMXIA and UMXIC-UM
XIE is the unit input multiplexer UMX shown in FIG.
As represented by I1, one input terminal includes a NAND gate NA3 for receiving an inverted signal of the inverted output signal DI1B of the corresponding unit data input buffer UIB1 of the data input buffer DIB by the inverter VD. An internal control signal DIE is supplied to the other input terminal of the NAND gate NA3, and the output terminal of the NAND gate NA3 passes through two inverters VE and VF, and then receives the corresponding write data bus WB.
1B.

As a result, on the write data bus WB1B, the synchronous DRAM has a × 16-bit configuration and the internal control signal DIE is at a high level, as shown on the left side of FIG. , The inverted output signal DI1B of the corresponding unit data input buffer UIB1 of the data input buffer DIB is selectively transmitted, and the write data buses WB3B, WB5B, WB7B to WBA are transmitted.
B and WBCB to WBEB are also selectively provided with a unit data input buffer UIB3 corresponding to the data input buffer DIB, provided that the synchronous DRAM has a × 16 bit configuration and the internal control signal DIE is at a high level. UIB5, UIB7 to UIBB and U
Inverted output signals DI3B, DI5B of IBC to UIBE,
DI7B to DIAB and DICB to DIEB are transmitted, respectively.

The unit input multiplexer UMXI
1, UMXI3, UMXI5, UMXI7, UMXI
8, connection switching circuits CSI1 and CSI provided on the output terminal side of UMXIA, UMXIC and UMXIE
3, CSI5, CSI7, CSI8, CSIA, CSI
For C and CSIE, the synchronous DRAM is × 16
When the bit configuration is adopted, a corresponding metal wiring layer is selectively formed and brought into a transmission state. Further, the write data bus WB1 corresponding to these unit input multiplexers
B, WB3B, WB5B, WB7B, WB8B, WBA
As described above, B, WBCB and WBEB are formed when the corresponding metal wiring layer is selectively formed when the synchronous DRAM has the × 16 bit configuration and when the synchronous DRAM has the × 4 bit or × 8 bit configuration. Not done. When these eight write data buses are not formed, the connection switching circuits CSI1, CSI3, CSI5, CSI7, CSI
SI8, CSIA, CSIC, and CSIE are in a non-transmission state because the corresponding metal wiring layer is not formed, whereby the corresponding unit input multiplexer UM
XI1, UMXI3, UMXI5, UMXI7, UMX
The output terminals of I8, UMXIA, UMXIC and UMXIE are opened.

On the other hand, the unit input multiplexers UMXI2 and UMXI6 of the input multiplexer MXI are
The circuit configuration is similar to that of the unit input multiplexer UMXI0 as represented by the unit input multiplexer UMXI2 of (c), and a pair of transfer gates G3 and G4 whose right terminals are commonly connected to one input terminal of the NAND gate NA4. including. The left input terminals of these transfer gates are supplied with inverted signals of the unit data input buffers UIB2 and UIBD of the data input buffer DIB and the inverted output signals DI2B and DIDB of the DIDB by the inverter VG or VH, respectively. An internal signal TBX4 is commonly supplied to the gates of the P-channel MOSFET of the transfer gate G3 and the N-channel MOSFET of the transfer gate G4, and the gates of the N-channel MOSFET of the transfer gate G3 and the P-channel MOSFET of the transfer gate G4 are connected to the gates. , An inverted internal signal TBX4B is commonly supplied.

An internal control signal DIE is supplied to the other input terminal of the NAND gate NA4 constituting the unit input multiplexer UMXI2, and its output terminal is coupled to the write data bus WB2B via two inverters VI and VJ. .

As a result, when the internal signal TBX4 is at the low level and the inverted internal signal TBX4B is at the high level, the write data bus WB2B has the × 8-bit or × 16-bit configuration of the synchronous DRAM. 15, on the condition that the internal control signal DIE is at a high level, the inverted output signal DI2B of the corresponding unit data input buffer UIB2 of the data input buffer DIB, that is, the write data D1 or D2 is transmitted. Also, the internal signal TBX
4 is at a high level and the inverted internal signal TBX4B is at a low level, ie, when the synchronous DRAM
When the bit configuration is set and the normal operation mode is set, on the condition that internal control signal DIE is at the high level, inverted output signal DIDB of unit input multiplexer UIBD of data input buffer DIB, that is, write data D3 is transmitted. .

For the same reason, the write data bus WB6
In B, a synchronous DRAM is × 8 bits or × 16 bits.
When the bit configuration is adopted, the inverted output signal DI6B of the corresponding unit data input buffer UIB6 of the data input buffer DIB, that is, the write data D3 or D6 is transmitted on the condition that the internal control signal DIE is at a high level, and the synchronous When the DRAM has a × 4 bit configuration and is set to the normal operation mode, the inverted output signal DI9B of the unit input multiplexer UIB9 of the data input buffer DIB, that is, the write data D2 is also provided on condition that the internal control signal DIE is at a high level. Is transmitted.

From the above, when the synchronous DRAM has a × 4 bit configuration, the data input / output terminals D0 to D0
From D3, the unit data input buffers UIB2, UIB6, UIB9 and UIBD of the data input buffer DIB
4-bit write data D0-D input through
3 is a 2-bit write data bus WB0B and WBFB, WB4B and WBBB, WB6B and WB, respectively.
9B and WB2B and WBDB. Also, when the synchronous DRAM has a × 8-bit configuration, the data input / output terminals D0 to D7, that is, the unit data input buffers UIB0 and UIB of the data input buffer DIB.
2, UIB4, UIB6, UIB9, UIBB, UIB
D and 8-bit write data D0 to D7 input via the UIBF correspond to the corresponding write data bus W.
B0B, WB2B, WB4B, WB6B, WB9B, W
BBB, WBDB and WBFB, respectively, and when the synchronous DRAM has a × 16-bit configuration, data input / output terminals D0 to DF, that is, unit data input buffers UIB0 to UIB0 of data input buffer DIB.
The 16-bit write data D0 to DF transmitted through the UIBF correspond to the corresponding write data buses WB0B to WB0B to WB.
Each is transmitted to the BFB.

When the synchronous DRAM is set to the reduced test mode with a × 4 bit configuration, the corresponding reduced data I / O terminals D0 to D3 are used as shown in FIG. Respectively. When the synchronous DRAM is set to the reduced test mode in the × 8-bit configuration, as shown in FIG. 13, the synchronous DRAM is inputted through data input / output terminals D1, D3, D4 and D6, respectively. When the reduced test mode is set in the × 16 bit configuration, as shown in FIG. 14, data is input via data input / output terminals D2, D6, D9 and DD, respectively. That is, in the case of this embodiment, the contraction test data T0 to T3 are the synchronous D
Data input buffer DI regardless of the bit configuration of RAM
B unit data input buffers UIB2, UIB6, UI
B9 and input via UIBD,
As shown on the right side of FIG. 15, these contracted test data T0 to T3 are directly sent from the corresponding unit data input selection circuits to the corresponding write data buses WB2B, WB6B, WB.
9B and WBDB.

Next, input data selection circuits IS0 and IS0
6, 16 unit data input selection circuits UIS0 provided corresponding to the unit write amplifiers UWA0 to UWAF of the write amplifiers WA0 and WA1 as shown in FIG.
To UISF, respectively, and the input data selection circuit IS2
And IS3 are provided corresponding to the unit write amplifiers UWA0 to UWAF of the write amplifiers WA2 and WA3.
It includes six unit data input selection circuits UIS0 to UISF, respectively. A test control signal TP is commonly supplied to these unit data input selection circuits from the mode register MR.

One input terminal of unit data input selection circuits UIS0 to UISF constituting input data selection circuits IS0 to IS3 has corresponding write data buses WB0B to WB0B to X16 bit configuration when the synchronous DRAM has a × 16 bit configuration.
When the synchronous DRAM is coupled to the WBFB and has a × 4 bit or × 8 bit configuration, the unit data input selection circuits UIS0 and UIS1, UIS2 and UIS
3, UIS4 and UIS5, UIS6 and UIS7, U
IS8 and UIS9, UISA and UISB, UISC
Write data buses WB0B, WB2B, WB4
B, WB6B, WB9B, WBBB, WBDB, and WBFB are each commonly coupled two each.

On the other hand, input data selection circuits IS0 and IS0
8 unit data input selection circuits UIS0 to UIS0
The other input terminal of UIS7 is connected to write data bus WB6.
B and the other input terminals of the remaining eight unit data input selection circuits UIS8 to UISF are commonly connected to a write data bus WB9B. The other input terminals of the eight unit data input selection circuits UIS0 to UIS7 constituting the input data selection circuits IS2 and IS3 are commonly coupled to the write data bus WB2B, and the remaining eight unit data input selection circuits UIS8 to UIS8 to The other input terminal of UISF is commonly coupled to write data bus WBDB. The output signals of the unit data input selection circuits UIS0 to UISF of the input data selection circuits IS0 to IS3 are written as inverted internal write data WD0B to WDFB as the write amplifier WA.
0-WA3 corresponding unit write amplifiers UWA0-UW
Each is supplied to the AF.

Here, input data selection circuits IS0 to IS
The unit data input selection circuits UIS0 to UISF of No. 3 have their lower terminals commonly connected to the input terminal of the inverter VM, as represented by the unit data input selection circuit UIS0 of the input data selection circuit IS0 in FIG. It includes a pair of transfer gates G5 and G6. The upper terminals of these transfer gates are coupled to write data buses WB6B and WB0B via inverters VK and VL, respectively. The test control signal TP is commonly supplied to the gates of the N-channel MOSFET of the transfer gate G5 and the P-channel MOSFET of the transfer gate G6. The test control signal TP is supplied to the gates of the P-channel MOSFET of the transfer gate G5 and the N-channel MOSFET of the transfer gate G6. Are commonly supplied with the inverted signal, that is, the inverted test control signal TPB. Inverter V
The M output signal is supplied to the unit write amplifier UWA0 of the write amplifier WA0 as inverted internal write data WD0B.

As a result, when the test control signal TP is set to the low level, that is, when the synchronous DRAM is set to the normal operation mode, the unit write amplifier UWA0 of the write amplifier WA0 is set as shown on the left side of FIG. When the write data D0 transmitted via the write data bus WB0B is supplied as the inverted internal write data WD0B and the test control signal TP is set to the high level, that is, when the synchronous DRAM is set to the reduced test mode, 16, reduced test data T transmitted via write data bus WB6B.
1 is supplied. Further, when the synchronous DRAM is set to the normal operation mode with a × 16 bit configuration, the write data D1 transmitted via the write data bus WB1B is supplied to the unit write amplifier UWA1 as inverted internal write data WD1B. When the normal operation mode is set in the 4-bit or × 8-bit configuration, write data D transmitted through write data bus WB0B
0 is transmitted. When the synchronous DRAM is set to the reduction test mode, the reduction test data T0 transmitted via the write data bus WB6B is supplied to the unit write amplifier UWA1 of the write amplifier WA0 as inverted internal write data WD1B.

On the other hand, when the synchronous DRAM is set in the normal operation mode, the write data D0, D7 or DF transmitted via the write data bus WBFB is added to the unit write amplifier UWAF of the write amplifier WA0. It is supplied as a WDFB, and when the reduced test mode is set, the write data bus WB9B
Is supplied as inverted internal write data WDFB. The unit write amplifier UWAE has a synchronous DRAM of × 16.
When the normal operation mode is set in the bit configuration, write data DE transmitted via write data bus WBEB
Are supplied as inverted internal write data WDEB,
When the normal operation mode is set in the 4-bit or x8-bit configuration, the write data D0 or D7 transmitted through the write data bus WBFB is supplied. When the synchronous DRAM is set to the reduction test mode, the reduction test data T2 transmitted via the write data bus WB9B is supplied to the unit write amplifier UWAE as inverted internal write data WDEB.

Similarly, when the synchronous DRAM is set to the normal operation mode, the write data D3, D1 or D2 transmitted via the write data bus WB2B is written to the unit write amplifier UWA2 of the write amplifier WA0 by the inverted internal write. When the data is supplied as data WD2B and the reduced test mode is set, the write data bus WB6
Reduction test data T1 transmitted via B is supplied. When the synchronous DRAM is set to the normal operation mode with a × 16-bit configuration, the write data D3 transmitted via the write data bus WB3B is supplied to the unit write amplifier UWA3 with the inverted internal write data WD3B.
When the normal operation mode is set in the × 4 bit or × 8 bit configuration, the write data bus WB2B
Is supplied via the write data D3 or D1. When the synchronous DRAM is set to the contraction test mode, the unit write amplifier UWA3 is supplied with the contraction test data T1 transmitted via the write data bus WB6B.

On the other hand, when the synchronous DRAM is set in the normal operation mode, the write data D3, D6 or DD transmitted via the write data bus WBDB is supplied to the unit write amplifier UWAD of the write amplifier WA0. When the mode is supplied as WDDB and the reduced test mode is set, the write data bus WB9B
Is supplied.
The unit write amplifier UWAC has a synchronous D
When the RAM is set to the normal operation mode in the × 16 bit configuration, the write data DC transmitted via the write data bus WBCB is supplied as inverted internal write data WDCB, and the normal operation mode is set in the × 4 bit or × 8 bit configuration. , The write data D3 or D6 transmitted via the write data bus WBDB is supplied. When the synchronous DRAM is set to the reduction test mode, the reduction write test data T2 transmitted via the write data bus WB9B is supplied to the unit write amplifier UWAC.

Next, when the synchronous DRAM is set in the normal operation mode, the write data D1, D2 or D4 transmitted via the write data bus WB4B is written into the unit write amplifier UWA4 of the write amplifier WA0. When the data is supplied as data WD4B and the reduced test mode is set, the write data bus WB6B
Is supplied.
The unit write amplifier UWA5 has a synchronous D
When the RAM is set to the normal operation mode in the × 16 bit configuration, the write data D5 transmitted via the write data bus WB5B is supplied as inverted internal write data WD5B, and the normal operation mode is set in the × 4 bit or × 8 bit configuration. , The write data D1 or D2 transmitted through the write data bus WB4B is supplied. When the synchronous DRAM is set to the reduction test mode, the reduction test data T1 transmitted via the write data bus WB6B is supplied to the unit write amplifier UWA5.

On the other hand, when the synchronous DRAM is set to the normal operation mode, the write data D1, D5 or DB transmitted via the write data bus WBBB is applied to the unit write amplifier UWAB of the write amplifier WA0. When the data is supplied as WDBB and the reduced test mode is set, the write data bus WB9B
Is supplied.
The unit write amplifier UWAA is a synchronous DR.
When the AM is set to the normal operation mode in the × 16 bit configuration, the write data DA transmitted via the write data bus WBAB is supplied as the inverted internal write data WDAB, and the normal operation mode is set in the × 4 bit or × 8 bit configuration. , The write data D1 or D5 transmitted through the write data bus WBBB is supplied. When the synchronous DRAM is set to the reduction test mode, the reduction test data T2 transmitted via the write data bus WB9B is supplied to the unit write amplifier UWAB.

Similarly, when the synchronous DRAM is set to the normal operation mode, the write data D2, D3 or D6 transmitted via the write data bus WB6B is inverted in the unit write amplifier UWA6 of the write amplifier WA0. When the data is supplied as data WD6B and the reduced test mode is set, the write data bus WB6
Reduction test data T1 transmitted via B is supplied. When the synchronous DRAM is set to the normal operation mode with a × 16-bit configuration, the write data D7 transmitted via the write data bus WB7B is supplied to the unit write amplifier UWA7 with the inverted internal write data WD7B.
When the normal operation mode is set in the × 4 bit or × 8 bit configuration, the write data bus WB6
Write data D2 or D3 transmitted via B is supplied. When the synchronous DRAM is set to the reduction test mode, the unit write amplifier UWA7 receives the reduction test data T1 transmitted via the write data bus WB6B.
Is supplied.

On the other hand, when the synchronous DRAM is set in the normal operation mode, the write data D2, D4 or D9 transmitted via the write data bus WB9B is added to the unit write amplifier UWA9 of the write amplifier WA0. WD9B is supplied as write data bus WB9B when the reduced test mode is set.
Is supplied.
The unit write amplifier UWA8 has a synchronous D
When the RAM is set to the normal operation mode in the × 16 bit configuration, the write data D8 transmitted via the write data bus WB8B is supplied as inverted internal write data WD8B, and the normal operation mode is set in the × 4 bit or × 8 bit configuration. , The write data D2 or D4 transmitted via the write data bus WB9B is supplied. When the synchronous DRAM is set to the contraction test mode, the contraction test data T2 transmitted via the write data bus WB9B is supplied to the unit write amplifier UWA8.

The inverted internal write data WD0B to WDFB for the unit write amplifiers UWA0 to UWAF of the write amplifier WA1 are processed under the same logical condition as the inverted internal write data WD0B to WDFB for the unit write amplifiers UWA0 to UWAF of the write amplifier WA0. Generated. However, the inverted internal write data WD0B to WDFB in the normal operation mode for the unit write amplifiers UWA0 to UWAF of the write amplifiers WA2 and WA3.
Are generated under the same logical conditions as the inverted internal write data WD0B to WDFB for the unit write amplifiers UWA0 to UWAF of the write amplifiers WA0 and WA1, but when the synchronous DRAM is set to the reduction test mode, Internal write data WD0B ~
WD7B is generated based on test data transmitted via write data bus WB2B, and inverted 8-bit lower internal write data WD8B to WDFB are generated based on test data transmitted via write data bus WBDB. Is generated.

The unit write amplifiers UWA0 to UWAF of the write amplifiers WA0 to WA3 correspond to the write amplifiers WA of FIG.
0, as represented by the unit write amplifier UWA0, an input data selection circuit IS0
Corresponding to the output signal of the corresponding unit data input selection circuit UIS0, that is, the flip-flop FF1 receiving the inverted internal write data WD0B, and the flip-flop FF1 provided between the power supply voltage of the circuit and the non-inverted common data line CD0T and inverted common data line CD0B. Channel type write MOSFET
N-channel write MOSFETs respectively provided between TP6 and P7, the non-inverted common data line CD0T and the inverted common data line CDDB, and the ground potential of the circuit.
N1 and N2.

The inverted write input terminal CKB of the flip-flop FF1 has a corresponding write amplifier drive signal WA
En, that is, an inverted signal from the inverter VO of WAE0 is supplied. Also, a P-channel type writing MOSF
The gates of ETP6 and P7 have two inverters VP
And NQ via VQ and VT and VU
The output signals of A6 and NA7 are supplied, respectively, and the output signals of NAND gates NA7 and NA6 are supplied to the gates of N-channel type write MOSFETs N1 and N2 via one inverter VR and VS, respectively. One input terminal of the NAND gates NA6 and NA7 is supplied with the inverted output signal QB and the non-inverted output signal Q of the flip-flop FF1, respectively, and the other input terminal is supplied with the write amplifier drive signal WAE0 in common. .

When the corresponding write amplifier drive signal WAEn is at a low level, flip-flop FF1 enters a so-called through state, and inverts internal write data WD0B supplied from corresponding unit data input selection circuit UIS0 of input data selection circuit IS0. NAND gate NA
6 and NA7. At this time, since the write amplifier drive signal WAE0 is at low level, the output signals of the NAND gates NA6 and NA7 are both fixed at high level, the gate potentials of the write MOSFETs P6 and P7 are both at high level, and the write MOSFETs N1 and N
The gate potentials of the gates 2 are both at the low level. As a result,
All of these write MOSFETs are turned off, and writing to the selected memory cell connected to the complementary common data line CD0 * via the sense amplifier SA (not shown) is not performed.

Next, the corresponding write amplifier drive signal WA
When E0 is set to the high level, the flip-flop FF1
Is in a so-called latch state, and holds the logic level immediately before the inverted internal write data WD0B. At this time, the output signal of the NAND gate NA6 selectively becomes low level on the condition that the inverted output signal QB of the flip-flop FF1 is at the high level, that is, the write data held by the flip-flop FF1 is logic "1". Conversely, the output signal of NA7 selectively becomes low level on the condition that the non-inverted output signal Q of flip-flop FF1 is at high level, that is, the write data held by flip-flop FF1 is logic "0". When the output signal of the NAND gate NA6 is at a low level and the output signal of the NAND gate NA7 is at a high level, the write MOSFETs P6 and N2 are turned on, and the write MOSFETs P7 and N1 are turned off. Therefore, the selected memory cell connected to the complementary common data line CD0 * receives a high-level write signal via the non-inverted common data line CD0T and a low-level write signal via the inverted common data line CD0B. Then, the storage data of logic "1" is written.

On the other hand, when the output signal of the NAND gate NA6 is at the high level and the output signal of the NAND gate NA7 is at the low level, the write MOSFETs P6 and N2 are turned off in the unit write amplifier UWA0, and the write MOSFETs P7 and N1 are turned on instead. Becomes Therefore, a low-level write signal via the non-inverted common data line CD0T and a high-level write signal via the inverted common data line CD0B are applied to the selected memory cell connected to the complementary common data line CD0 *. Then, the storage data of logic “0” is written.

The unit main amplifiers UMA0 to UMAF of the main amplifiers MA0 to MA3 are
0, as represented by the main amplifier UMA0, a P-channel MOSFET PD and an N-channel M
OSFETN3 and P-channel MOSFETPE
And a pair of CMs comprising an N-channel MOSFET N4
An OS inverter includes a differential amplifier circuit DA cross-coupled. The drains of MOSFET PD and N3, which constitute the differential amplifier circuit DA, are commonly connected, that is, MOSFETP
The commonly coupled gates of E and N4 form a differential amplifier circuit D
A becomes the non-inverting input / output node DAT of MOSFET A
The common coupled drain of E and N4, ie, MOSF
The commonly coupled gate of ETPD and N3 is its inverting input / output node DAB. MOSFET N3 and N4
Are connected to each other, an N-channel drive MOSFET N5 receiving a main amplifier drive signal MAEn, that is, MAE0, corresponding to the gate thereof is provided. As a result, the differential amplifier circuit DA sets the corresponding main amplifier drive signal MAE0 to the high level and sets the drive MOSFET
When N5 is turned on, it is selectively activated.

Non-inverting input / output node D of differential amplifier circuit DA
AT has a P-channel type switch M
A P-channel MOSFET PF and an N-channel M coupled to a non-inverting common data line CDT via an OSFET P8 and constituting a clocked inverter thereabove.
It is coupled to the gate of OSFET N6. The inverting input / output node DAB of the differential amplifier circuit DA is coupled to the inverting common data line CDB via a P-channel type switch MOSFET P9 below the P-channel switching MOSFET P9, and a P-channel inverter constituting another clocked inverter above the inverting input / output node DAB. MOSFET PG and N-channel MOSFET N8
To the gate. Between the non-inverting input / output node DAT and the inverting input / output node DAB of the differential amplifier circuit DA, three more precharge MOSFETs PA to PC are provided in a parallel-series configuration. These precharge MOSFE
The inverted internal control signal MAPC is applied to the gates of TPA to PC.
B are supplied in common, and a common internal source of the precharge MOSFETs PA and PB has a predetermined internal voltage V
DL is supplied.

As a result, the non-inverting input / output node DAT and the inverting input / output node DAB of the differential amplifier circuit DA of the unit main amplifier UMA0 are connected to the inverted internal control signal M when the synchronous DRAM is selected in the read mode.
ATRB is set to low level and switch MOSFETP8
And P9 is turned on to selectively connect to the corresponding complementary common data line CD0 *, that is, the selected memory cell of the corresponding memory mat MAT0 of bank BNK0. The precharge MOSFETs PA to PC are selectively and simultaneously turned on by the inverted internal control signal MAPCB being set to the low level, and the differential amplifier circuit DA
Non-inverting input / output node DAT and inverting input / output node DA
B is precharged to the internal voltage VDL.

MOSF forming clocked inverter
The source of ETN6 has an internal control signal
E is coupled to the ground potential of the circuit via an N-channel MOSFET N7 receiving E, and the source of MOSFET N8 is
An N-channel MOSFET N9 whose gate receives the internal control signal MAQUE, and a test control signal TP
And N-channel MOSFET NA receiving the same to ground potential of the circuit. The commonly coupled drains of MOSFETs PF and N6 are coupled to the input node of data latch LT, which is a cross-coupled inverter VV and VW, and the commonly coupled drains of MOSFETs PG and N8 are cross-coupled with inverters VX and VY. Of the data latch LB.

As a result, the potential at the non-inverting input / output node DAT of the differential amplifier circuit DA becomes synchronous DRA.
When M is in the normal read mode, the data latch L is selectively turned on in response to the high level of the internal control signal MAQUE.
T, and the potential at the inverting input / output node DAB is selectively changed to data by the synchronous DRAM being selected in the reduction test mode and the internal control signal MAQE and the test control signal TP being both at a high level. This is transmitted to the latch LB.

The output node of data latch LT is connected to one input terminal of NAND gate NA8, and the potential at the output node of data latch LB is supplied to reduction test circuit TC00 as inverted test output signal TO0B of unit main amplifier UMA0. Is done. The other input terminal of the NAND gate NA8 is supplied with an output signal LO10T of a similar data latch LT of the unit main amplifier UMA0 of the main amplifier MA1 of the bank BNK1, and the output signal is supplied to one input terminal of the NAND gate NA9 and the NOR gate NO3. Supplied to The other input terminal of the NAND gate NA9 is supplied with a corresponding main amplifier output control signal MOEn, that is, MOE0, and the other input terminal of the NOR gate NO3 is supplied with an inverted signal by the inverter VZ.

The output signal of the NAND gate NA9 is coupled to the gate of a P-channel type output MOSFET PH.
The output signal of NOR gate NO3 is coupled to the gate of N-channel type output MOSFET NB. Output MOSF
The source of ETPH is coupled to the power supply voltage of the circuit, and the source of output MOSFET NB is coupled to the ground potential of the circuit. The commonly coupled drains of the output MOSFETs PH and NB are output to the read data bus RB0B as a read output signal of the unit main amplifier UMA0.
Read data bus RB0B includes inverters Va and V
Non-inverting input / output nodes of the latch circuit in which b is cross-coupled are coupled. The part surrounded by the dotted line in FIG.
A first bus output circuit for selectively performing an output operation in accordance with a first bus output control signal, that is, a main amplifier output control signal MOEn, comprising two main amplifiers MA0 and MA
1 or shared by the corresponding unit main amplifiers UMA0 of MA2 and MA3. A latch circuit composed of inverters Va and Vb is a unit main amplifier UM corresponding to four main amplifiers MA0 to MA3.
Each is shared by A0.

As a result, the amplified read signal established at the non-inverted input / output node DAT and the inverted input / output node DAB of the differential amplifier circuit DA receives the high level of the internal control signal MAQE and receives data latches LT and LB. And is held by the corresponding unit main amplifier UM of the main amplifier MA1 by the NAND gate NA8.
After the logical sum with the output signal LO10T of A0 is obtained, the signal is output to the read data bus RB0B in response to the high level of the main amplifier output control signal MOE0. At this time, the latch circuit composed of the inverters Va and Vb acts to hold the logical level of the read signal output from the read signal output terminal of the unit main amplifier UMA0 of the main amplifiers MA0 to MA3.

When the synchronous DRAM has a × 4 bit configuration, as shown in FIG. 17, the bank BNK0 is connected to the read data bus RB0B.
And BNK2, that is, the read signal output terminals of the corresponding unit main amplifiers UMA0 and UMA1 of the main amplifiers MA0 and MA2 are commonly coupled, and the logical sum of the NAND gate NA8 in FIG. The read signal output terminals of the unit main amplifiers UMA0 and UMA1 of the amplifiers MA1 and MA3 are commonly coupled. Further, the read signal output terminals of the unit main amplifiers UMAE and UMAF of the main amplifiers MA0 and MA2 are commonly coupled to the read data bus RBFB, and the logical sum of the NAND gate NA8 in FIG. The read signal output terminals of the unit main amplifiers UMAE and UMAF of MA1 and MA3 are commonly coupled.

As described above, the synchronous DRAM has ×
When the normal operation mode is set in the 4-bit configuration, the read signal output terminals are connected to the read data buses RB0B and RB0.
Unit main amplifiers UMA0-UMA1 and UMAE- of main amplifiers MA0-MA3 commonly coupled to FB
The UMAFs are both associated with the data input / output terminal D0 as shown on the left side of FIG. 20, and are selectively activated in response to the high level of the corresponding main amplifier drive signal MAEn. The read data buses RB0B and RBFB are OR-coupled by an output multiplexer MXO as shown by a dotted line in FIG. 17, and are coupled to a data input / output terminal D0.

Similarly, when the synchronous DRAM has a × 4 bit configuration, the read data bus RB2B
Unit of main amplifier MA0-MA3 Main amplifier UMA
The read signal output terminals of the unit main amplifiers UMAC and UMAD are commonly connected to the read data bus RBDB. In addition, read signal output terminals of unit main amplifiers UMA4 and UMA5 of main amplifiers MA0 to MA3 are commonly coupled to read data bus RB4B, and unit main amplifier UMA is connected to read data bus RBBB.
The read signal output terminals of A and UMAB are commonly coupled. Further, read data bus RB6B includes unit main amplifiers UMA6 and UMA of main amplifiers MA0 to MA3.
The read signal output terminals of MA7 are commonly coupled, and the read data output terminals of unit main amplifiers UMA8 and UMA9 are commonly coupled to read data bus RB9B.

When the synchronous DRAM is in the normal operation mode with a × 4 bit configuration, the unit main amplifiers UMA2 and UMA3 of main amplifiers MA0 to MA3 whose read signal output terminals are commonly coupled to read data buses RB2B and RBDB, and UMAC and UMAD
20 are both associated with the data input / output terminal D3, as shown on the left side of FIG. 20, and are selectively activated when the corresponding main amplifier drive signal MAEn is at a high level. Unit main amplifiers UMA4 to UM of main amplifiers MA0 to MA3 whose read signal output terminals are commonly coupled to read data buses RB4B and RBBB.
A5 and UMAA to UMAB are both associated with the data input / output terminal D1, and are put into an alternative operation state in response to the high level of the corresponding main amplifier drive signal MAEn. Further, the unit main amplifiers UMA6 to UMA of main amplifiers MA0 to MA3 whose read signal output terminals are commonly coupled to read data buses RB6B and RB9B.
MA7 and UMA8 to UMA9 are both associated with the data input / output terminal D2, and are selectively activated in response to the high level of the corresponding main amplifier drive signal MAEn.

Read data buses RB2B and R forming a pair
BDB, RB4B and RBBB and RB6B and R
B9B is OR-coupled by the output multiplexer MXO as shown by the dotted line in FIG. 17, and then the unit data output buffer UO of the data output buffer DOB.
B2, UOB6, UOB9 and UOBD are coupled to corresponding data output terminals D3, D1 and D2, respectively. When the synchronous DRAM has a × 4 bit or × 8 bit configuration, the read data buses RB1B, RB3B, RB5B, RB7B,
RB8B, RBAB, RBCB and RBEB are not formed or bound. The specific configuration and the like of the output multiplexer MXO will be described later in detail.

On the other hand, when the synchronous DRAM has a × 8 bit configuration, read data buses RB0B, RB2
B, RB4B, RB6B, RB9B, RBBB, RBD
B and RBFB are × 4 as shown in FIG.
As in the case of the bit configuration, each of the main amplifiers MA0
8 unit main amplifiers UMA0 and U3
MA1, UMA2 and UMA3, UMA4 and UMA
5, UMA6 and UMA7, UMA8 and UMA9, U
MAA and UMAB, UMAC and UMAD and U
Commonly coupled to MAE and UMAF read signal output terminals. Also, each pair of unit main amplifiers UMA0 and UMA0
MA1, UMA2 and UMA3, UMA4 and UMA
5, UMA6 and UMA7, UMA8 and UMA9, U
MAA and UMAB, UMAC and UMAD and U
When the synchronous DRAM is set to the normal operation mode, MAE and UMAF are respectively associated with data input / output terminals D0 to D7 as shown on the left side of FIG. In response, one of them is set to an operation state alternatively.

Read data buses RB0B, RB2B, R
B4B, RB6B, RB9B, RBBB, RBDB, and RBFB are, as shown by the dotted lines in FIG.
OB4, UOB6, UOB9, UOBB, UOBD and UOBF are coupled to data output terminals D0 to DF.

Further, when the synchronous DRAM has a × 16 bit configuration, 16 bits including an additional 8 bits are included.
The bit read data buses RB0B to RBFB are shown in FIG.
As shown in FIG. 9, a total of four unit main amplifiers UMA0 to UMAF corresponding to the main amplifiers MA0 to MA3
Are commonly coupled to the respective read signal output terminals. When the synchronous DRAM is set to the normal operation mode, each of the unit main amplifiers UMA0 to UMAF operates as shown in FIG.
As shown in FIG. 5, the main amplifier drive signals MA are respectively associated with the data input / output terminals D0 to DF.
In response to the high level of En, they are selectively and simultaneously brought into an operating state. Read data buses RB0B to RBFB are connected to output multiplexers MX as shown by the dotted lines in FIG.
O and data output buffers DOB are coupled to corresponding data output terminals D0 to DF via corresponding unit data output buffers UOB0 to UOBF, respectively.

Reduction test circuits TC00 and TC01, TC
10 and TC11, TC20 and TC21 and TC
30 and TC31 include two 8-input NAND gates NAA and NAB as represented by the reduction test circuit TC00 of FIG.

The first to eighth input terminals of the NAND gates NAA and NAB constituting the contraction test circuit TC00 are:
As shown in FIG. 2, the unit main amplifiers UMA0, UMAF, UM of the main amplifier MA0 are respectively associated with the first to eighth input terminals of the contraction test circuit TC00.
A1, UMAE, UMA2, UMAD, UMA3 and UMAC inverted test output signals TO0B, TOFB, T
O1B, TOEB, TO2B, TODB, TO3B and TOCB, or inverted signals of these inverted test output signals by inverters Vc to Vj are supplied, respectively.

The output signal of the NAND gate NAA is supplied to one input terminal of an AND gate AG1.
The output signal of the NAND gate NAB is supplied to the other input terminal. The output signal of the AND gate AG1 is supplied to one input terminal of the NAND gate NAD. The test control signal TP is connected to the other input terminal of the NAND gate NAD.
And the output signal is supplied to one input terminal of the NOR gate NO4. A test internal signal TRHIT0 is supplied to the other input terminal of the NOR gate NO4, and its output signal is supplied to the NAND gate NAE and the NOR gate NO4.
5 is supplied to one input terminal. NAND Gate NAE
Is supplied with the internal control signal TOE, and the other input terminal of the NOR gate NO5 is supplied with an inverted signal of the internal control signal TOE by the inverter Vk.

The output signal of the NAND gate NAE is supplied to the gate of a P-channel type output MOSFET PI.
The output signal of the NOR gate NO5 is supplied to the gate of an N-channel type output MOSFET NC. Output MOSF
The source of ETPI is coupled to the supply voltage of the circuit and the output M
The source of OSFET NC is coupled to the circuit ground potential. The potential at the common-connected drains of these output MOSFETs PI and NC, that is, at the output terminal of the reduction test circuit TC00, is equal to the output signal T00 of the reduction test circuit TC00.
D00 is output to the read data bus RB4B.
The portion surrounded by the dotted line in FIG. 9 corresponds to a second bus output control signal, that is, a second bus output circuit that selectively performs an output operation in accordance with the internal control signal TOE.

From these, the reduction test circuit TC00
Is output when the output signal of the NAND gate NAA or the NAND gate NAB is at a low level, in other words, the main amplifier MA1.
Unit of 0 Main amplifier UMA0 to UMA3 and UM
AC to UMAF inversion test output signals TO0B to TO3B
When TOCB to TOFB are all at low level or all at high level, that is, in the reduced test mode, eight memory mats MAT0 to MAT3 or MAT arranged adjacent to bank BNK0.
When the logic levels of the reduced test data read from the eight selected memory cells TC to MATF are all the same, the level is selectively set to the low level. Level.

The output signal of AND gate AG1 receives a test control signal T when the synchronous DRAM is set to the reduced test mode.
After P goes high, the signal passes through the NAND gate NAD and the NOR gate NO4, and then receives the high level of the internal control signal TOE and is output to the read data bus RB4B as an output signal TD00. Needless to say, the logical level of the output signal TD00 of the reduction test circuit TC00 in the read data bus RB4B is the same as that of the eight memory mats MAT0 to MAT3 and MATC to MTC3 of the bank BNK0.
When all the logic levels of the reduced test data read from the selected memory cell of the MATF match, the low level is set. When the logical levels of these reduced test data are different even by one bit, the high level is set.

Similarly, the logic level of test output signal TO01 of contraction test circuit TC01 is set to eight memory mats MAT4 to MAT7 and MAT8 to MAT of bank BNK0.
When all the logic levels of the reduced test data read from the selected memory cell of the ATB match, the low level is set, and when the logical levels of these reduced test data are different even by one bit, the high level is set. Further, the test output signals TO10 and TO10 of the reduction test circuits TC10 and TC11, TC20 and TC21, and TC30 and TC31.
11, TO20 and TO21 and TO30 and TO
The logic level of 31 corresponds to the corresponding bank BNK1 to BNK.
3, eight memory mats MAT0-MAT3 and M
ATC to MATF or memory mat MAT4 to MA
It is set to a low level when the logic levels of the reduced test data read from the selected memory cells of T7 and MAT8 to MATB all match, and set to a high level when the logical levels of these reduced test data differ even by one bit. .

Reduction test circuit T corresponding to bank BNK0
The output terminal of C00 is coupled to read data bus RB4B regardless of the bit configuration of the synchronous DRAM, as shown in FIGS.
One output terminal is coupled to read data bus RBBB. Further, the reduction test circuit TC corresponding to the bank BNK1
10 and TC11 are connected to the read data bus RB
6B and RB9B, respectively, and the bank BNK2
Test circuits TC20 and TC corresponding to BNK3 and BNK3
21 and output terminals of TC30 and TC31 are coupled to read data buses RB0B and RBFB and RB2B and RBDB.

A pair of read data buses RB4B and R
BBB, RB6B and RB9B, RB0B and RBFB
RB2B and RBDB are associated with contracted test data T1, T2, T0 and T3, respectively, as shown on the right side of FIG. These mappings
Data input / output terminals D1, D2, D shown on the left side of FIG.
Needless to say, it matches the association with 0 and D3. As a result, the normal operation mode and the reduction test when the circuit configuration of the unit output multiplexer of the output multiplexer MXO for combining read signals or reduction test data transmitted through each pair of read data buses is a × 4 bit configuration. The mode and the mode are shared, thereby simplifying the output multiplexer MXO.

As shown in FIG. 10, output multiplexer MXO includes a 4-bit read data bus RB2B,
Four unit output multiplexers UMXO2 and UMX provided corresponding to RB6B, RB9B and RBDB
O6, UMXO9 and UMXOD, and other 12-bit read data buses RB0B to RB1B and RB3B to
RB5B, RB7B to RB8B, RBAB to RBCB, and 12 inverters Vm to Vx provided corresponding to RBEB to RBFB.

Of these, input terminals of inverters Vm, Vp, Vu and Vx are directly coupled to corresponding read data buses RB0B, RB4B, RBBB and RBFB, respectively, and the potentials at the output terminals thereof are equal to internal read data DXO0, DXO4. , DXOB and D
XOF is transmitted to the corresponding unit data output buffers UOB0, UOB4, UOBB and UOBF of the data output buffer DOB, respectively. The other eight inverters Vn, Vo, Vq, Vr, Vs, Vt, V
The input terminals of v and Vw are connected to corresponding second connection switching circuits CSO1, CSO3, CSO5, CSO7, C
Read data buses RB1B, RB3B, RB5B, RB via SO8, CSOA, CSOC and CSOE
7B, RB8B, RBAB, RBCB and RBEB
, And the potentials at the output terminals thereof are equal to the internal read data DXO1, DXO3, DXO5, DX
O7, DXO8, DXOA, DXOC and DXOE
As the unit data output buffers UOB1, UOB3, UOB5, UOB7, UOB of the data output buffer DOB
8, transmitted to UOBA, UOBC and UOBE.

In this embodiment, the connection switching circuits CSO1 to CSOE of the output multiplexer MXO are
When the synchronous DRAM has a × 16 bit configuration, a connection path indicated by a thick solid line is selectively formed, and when the synchronous DRAM has a × 4 bit or × 8 bit configuration, a connection path indicated by a dotted line is formed. You. Therefore, the input terminals of the inverters Vm, Vp, Vu and Vx are
Read data buses RB0B, RB4B, RBB which constantly correspond regardless of the bit configuration of the synchronous DRAM
B and RBFB, but in a × 4 bit configuration, as shown in FIG. 17, unit data output buffers UOB0 to UOB of data output buffer DOB
1, UOB3 to UOB5, UOB7 to UOB8, UOB
Since A to UOBC and UOBE to UOBF are not used, the output signal becomes invalid, and × 8 bits and ×
It is valid only in a 16-bit configuration.

On the other hand, inverters Vn, Vo, Vq, V
The input terminals of r, Vs, Vt, Vv and Vw are connected to the corresponding read data buses RB1B, RB3B, RB5 when the synchronous DRAM has a × 16 bit configuration.
B, RB7B, RB8B, RBAB, RBCB and RBEB, and output signals thereof, that is, internal read data DXO1, DXO3, DXO5, DXO7, DX
O8, DXOA, DXOC and DXOE are also valid. However, when the synchronous DRAM has a × 4 bit or × 8 bit configuration, the read data bus R
B1B, RB3B, RB5B, RB7B, RB8B, R
Since BAB, RBCB and RBEB are not formed and their input terminals are also coupled to the ground potential of the circuit, their output signals, that is, internal read data DXO1, DXO3, D
XO5, DXO7, DXO8, DXOA, DXOC and DXOE are all fixed at a high level.

Unit output multiplexer UMXO2, UM
The first input terminals of XO6, UMXO9 and UMXOD are connected to corresponding read data buses RB2B, RB6B,
It is bound to RB9B and RBDB, respectively. The second input terminal is connected to a read data bus RB0.
B, RB4B, RB6B and RB2B, respectively, and has a third input terminal connected to the read data bus RB
FB, RBBB, RB9B and RBDB, respectively. Unit output multiplexer UMXO2, UM
The potentials at the output terminals of XO6, UMXO9 and UMXOD are equal to the internal read data DXO2, DXO6,
Unit data output buffers UOB2, UOB6, and DXO9 of the data output buffer DOB as DXO9 and DXOD.
It is transmitted to UOB9 and UOBD, respectively. Unit output multiplexer UMXO2, UMXO6, UMXO
9 and UMXOD include an internal signal TX4 and an inverted signal of the inverter VI, that is, an inverted internal signal TX4.
B is supplied.

Note that the internal signal TX4 is, as described above,
When the synchronous DRAM has a × 4 bit configuration,
Alternatively, when the synchronous DRAM is set to the contraction test mode and the internal control signal TOE is set to the high level, it is selectively set to the high level.

Here, the unit output multiplexers UMXO2, UMXO6, UMXO of the output multiplexer MXO are used.
9 and UMXOD include an inverter Vy whose input terminal is coupled to the first input terminal of unit output multiplexer UMXO2, ie, read data bus RB2B, as represented by unit output multiplexer UMXO2 in FIG. One and the other input terminals are second and third input terminals of the unit output multiplexer UMXO2,
That is, it includes a NOR gate NO6 coupled to read data buses RB0B and RBFB. The output terminal of the inverter Vy is coupled to the output terminal of the unit output multiplexer UMXO2 via the transfer gate G7, and the output terminal of the NOR gate NO6 is connected to the unit output multiplexer UMXO via the transfer gate G8.
2 are commonly coupled to two output terminals. Transfer gate G
The internal signal TX4 is commonly supplied to the gates of the P-channel MOSFET constituting the transfer gate G7 and the N-channel MOSFET constituting the transfer gate G8, and the N-channel MOSFET constituting the transfer gate G7 and the P-channel MO constituting the transfer gate G8.
The inverted internal signal TX4B is commonly supplied to the gate of the SFET.

As a result, the unit output multiplexer UM
The output terminal of XO2 is transmitted via read data bus RB2B when internal signal TX4 is at a low level, that is, when the synchronous DRAM has a × 8-bit or × 16-bit configuration and is in a normal operation mode. Is output as internal read data DXO2. When the internal signal TX4 is at a high level, that is, when the synchronous DRAM has a × 4 bit configuration, or when the synchronous DRAM is in a reduction test mode and the internal control signal TOE is at a high level, the NOR gate NO6 , That is, a read signal transmitted via read data buses RB0B and RBFB or a logical sum signal of the reduction test result.

As described above, when the synchronous DRAM is ×
When the normal operation mode is set in the 4-bit configuration, the read data bus RB0B coupled to the second input terminal of the unit output multiplexer UMXO2 has data input / output terminals as shown on the left side of FIG. Read output signals of unit main amplifiers UMA0 and UMA1 associated with D0 are selectively transmitted, and read data bus RBFB coupled to the third input terminal of unit output multiplexer UMXO2 also has data input / output terminal D0. Are selectively transmitted from the unit main amplifiers UMAE and UMAF. Four unit main amplifiers UM associated with the data input / output terminal D0
A0 and UMA1 and UMAE and UMAF are selectively activated in response to the high level of the corresponding main amplifier drive signal MAEn, and alternatively output read output signals to the read data bus RB0B or RBFB. At this time, the read output signals of the other three unit main amplifiers that are not in the operation state are fixed at the low level. As a result, only the read output signal of the unit main amplifier in the operating state is transmitted to the unit data output buffer UOB2 of the data output buffer DOB as the output signal of the unit output multiplexer UMXO2, that is, the internal read data DXO2, and output from the data input / output terminal D0. Is done.

Similarly, read data buses RB2B and R
In the BDB, 4 corresponding to the data input / output terminal D3 is stored.
Unit main amplifiers UMA2 and UMA3 and U
MAC and UMAD read output signals are selectively transmitted. Also, read data buses RB4B and RBBB
Has four unit main amplifiers UMA4 or UMA5 or UMAC associated with the data input / output terminal D1.
Alternatively, a read output signal of UMAD is selectively transmitted,
Read output signals of the four unit main amplifiers UMA4 or UMA5 and UMAC or UMAD associated with the data input / output terminal D1 are selectively transmitted to the read data buses RB4B and RBBB. The four unit main amplifiers forming each set are selectively operated in response to the high level of the corresponding main amplifier drive signal MAEn, and the read output of the other three unit main amplifiers that are not in the operation state is provided. All signals are fixed at low level. As a result, the output signals of the unit output multiplexers UMXO6, UMXO9 and UMXOD to which only the read output signal of the unit main amplifier in the operating state corresponds, that is, the corresponding unit data output buffers of the data output buffer DOB as the internal read data DXO6, DXO9 and DXOD. And output from the data input / output terminals D3, D1 and D2.

On the other hand, when the synchronous DRAM has a × 8-bit configuration, read data buses RB0B, RB2
B, RB4B, RB6B, RB9B, RBBB, RBD
B and RBFB have data input / output terminals D0 to D7
UMA0B and UMA1B, UMA2B and UMA3B, UMA4B
And UMA5B, UMA6B and UMA7B, UMA8
B and UMA9B, UMAAB and UMABB, UMA
CB and UMACD and UMAEB and UMAFB
Are selectively transmitted. Further, each of the two unit main amplifiers forming a pair receives the high level of the corresponding main amplifier drive signal MAEn, and one of them is selectively operated, and alternatively, the readout output signal is output. I do. At this time, the read output signal of the other unit main amplifier that is not operating is fixed at a low level. As a result, only the read output signal of one of the unit main amplifiers in the operation state is used as the internal read data DXO0, DXO2, DXO4, DXO6, DXO.
9, DXOB, DXOD and DXOF are transmitted to the corresponding unit data output buffer of the data output buffer DOB, and output to the outside via the data input / output terminals D0 to D7.

Further, when the synchronous DRAM has a × 16-bit configuration, read data buses RB0B to RBFB including the added 8 bits are provided with unit main amplifier UMA corresponding to data input / output terminals D0 to DF.
0 to UMAF read output signals are transmitted, respectively. The unit main amplifiers UMA0 to UMAF are selectively and simultaneously activated in response to the high level of the corresponding main amplifier drive signal MAEn, and simultaneously output readout signals. These read output signals are
The data is directly transmitted to the corresponding unit data output buffer of the data output buffer DOB, and output to the outside from the corresponding data input / output terminals D0 to DF.

Next, when the synchronous DRAM is set to the reduction test mode, the read data buses RB0B and RB
FB includes reduction test circuit TC of bank BNK2 regardless of the bit configuration, as shown on the right side of FIG.
Output signals TD20 and TD21 of TC20 and TC21 are transmitted, respectively. These output signals TD20 and TD
21 is transmitted to the unit output multiplexer UMXO2 of the output multiplexer MXO as described above, and its NOR gate NO6 performs a logical sum of positive logic, that is, a logical product of negative logic. Therefore, in the reduction test mode, the internal read data DXO2 output from the unit output multiplexer UMXO2 to the unit data output buffer UOB2 of the data output buffer DOB, ie, the reduction test output from the data input / output terminal D0 to an external test device. The data T0 is output when the output signals TD20 and TD21 of the reduction test circuits TC20 and TC21 transmitted via the read data buses RB0B and RBFB are both at a low level, in other words, the sum of the memory mats MAT0 to MATF of the bank BNK2. When the read signals output from the 16 selected memory cells are all at the same logical level, they are selectively set to a high level, and when even one bit is different, they are set to a low level.

Similarly, read data buses RB2B and R
BDB, RB4B and RBBB and RB6B and R
B9B includes reduction test circuits TC30 and TC31, TC00 and TC01 of banks BNK3, BNK0 and BNK1 regardless of the bit configuration of the synchronous DRAM.
And output signals TD30 and TD31, TD00 and TD01, and TD10 and TD11 of TC10 and TC11, respectively. These output signals TD
30 and TD31, TD00 and TD01 and TD
10 and TD11 are unit output multiplexers UMXOD, UMXO6 and U of the output multiplexer MXO.
The signal is transmitted to the MXO 9 and the logical product of the negative logic is obtained by the NOR gate NO6.

Therefore, in the synchronous DRAM reduction test mode, unit output multiplexers UMXOD and UMXOD
Data output buffer D from MXO6 and UMXO9
Internal read data DXO output to OB unit data output buffers UOBD, UOB6 and UOB9
D, DXO6, and DXO9, that is, reduced test data T3, T1, and T2 output from data input / output terminals D3, D1, and D2 to an external test device are read data buses RB2B and RBDB, RB4B, and RB.
Reduction test circuits TC30 and TC31, TC00 and TC transmitted via BB and RB6B and RB9B
01 and output signals TD30 of TC10 and TC11
And TD31, TD00 and TD01 and TD10
And TD11 are both at a low level, that is, when the read signals output from a total of 16 selected memory cells of memory mats MAT0 to MATF of banks BNK3, BNK0 and BNK1 are all at the same logic level, respectively. To a high level, and if even one bit is different, it is set to a low level.

The functions and effects obtained from the above embodiments are as follows. (1) Synchronous DR having a configuration in which the bit configuration can be switched optionally and having a reduction test function
In an AM or the like, for example, 8 bits of a 16-bit data bus provided between a write amplifier and a main amplifier of each bank and a data input buffer and a data output buffer are fixedly formed irrespective of the bit configuration. The bit configuration switching process is simplified by sharing the bit and the × 8-bit configuration and selectively forming the remaining 8 bits only at the time of the × 16 bit as a metal option, thereby simplifying the bit configuration switching process and designing the layout for the bit configuration switching. The effect that the man-hour and the verification man-hour can be reduced can be obtained. (2) According to the above item (1), the effect is obtained that the layout of the synchronous DRAM can be made more efficient.

(3) In the above items (1) and (2), the predetermined bits of the data bus are used together as a test data bus for a reduction test, and the external terminals, the write amplifier and the main amplifier are used. Further, by providing a bonding option, that is, a data selection circuit for switching the data transmission path by selectively performing bonding between predetermined pads, the required number of data buses can be reduced, and the layout required area can be reduced. can get. (4) According to the above item (3), the synchronous D
The effect is obtained that the chip size of the RAM can be reduced and its cost can be reduced.

(5) In the above items (1) to (4), the reduction test by the reduction test circuit is performed for each byte of the stored data, and the test result of each byte is stored in the predetermined bit of the data bus. By transmitting the signals in parallel via the interface, an effect is obtained that a reduction test of a synchronous DRAM or the like can be efficiently realized. (6) In the above item (5), for example, 16 memory mats provided in each bank of a synchronous DRAM or the like are alternately made to correspond to two bytes of storage data, so that different logic levels between adjacent memory mats are provided. Is written, and the effect of detecting anomalies in the reduction test can be enhanced. (7) In the above items (5) and (6), the test result obtained by the reduction test circuit is transmitted through a predetermined bit of a data bus through which normal storage data is transmitted in a × 4 bit configuration, and the bit configuration is changed. By transmitting the same combination irrespective of the above, there is an effect that the circuit configuration of the output multiplexer can be simplified.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIGS. 1 and 2, the synchronous DRAM
An arbitrary bit configuration can be adopted, and an arbitrary number of banks can be provided. Also, banks BNK0 to BN
K3 can have any number of memory mats, and the number of reduction test circuits provided in each bank is also arbitrary. Memory mats MAT0-MATF of each bank and data input / output terminals D0-D3, D0-D7 and D0-D
The association with F is not restricted by the embodiment of FIG. Furthermore, the block configuration of the synchronous DRAM can take various embodiments, including the number and combination of the address signals, the names and combinations of the start control signal and the internal control signal, and the types, polarities and absolute values of the power supply voltage and the internal voltage. And the like are not restricted by this embodiment.

In FIG. 3, bit configuration switching circuit B
The specific configuration of C can take various embodiments. Also,
The bonding between the pads PB and PVEE may be connected in a × 8 bit and × 16 bit configuration and disconnected in a × 4 bit configuration. Internal signal T
The generation conditions of X4, TBX4 and BPX4 and their effective levels do not affect the gist of the present invention.

Referring to FIGS. 4 and 5 and FIGS. 6 and 7, the input multiplexer MXI and the input data selection circuit IS0 and the unit input multiplexers UMXI0 to UMXI0 to
MXIF and unit data input selection circuits UIS0 to UIS0
The specific configuration of the ISF can take various embodiments as long as the logical conditions are the same. 8 and 9, unit write amplifiers UWA0 to UWAF, unit main amplifiers UMA0 to UMAF, and reduction test circuit TC
The specific configuration of 00 to TC21 can take various embodiments. 10 and 11, an output multiplexer MXO and a unit output multiplexer UMXO
2, UMXO6, UMXO9, and the specific configuration of UMXOD can similarly adopt various embodiments.

In FIGS. 12 to 15 and FIGS. 17 to 19, output multiplexer MXO, input multiplexer MXI and input data selection circuits IS0 to IS3 provided as data selection circuits have a positional relationship with a data bus, an arrangement combination, and the like. Various embodiments can be adopted in.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronous DRAM which is the field of application as the background has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuit devices such as a normal dynamic RAM and a single-chip microcomputer including such a memory integrated circuit device. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor memory device having at least a bit configuration that can be optionally switched and having a reduction test function, and an apparatus or system including the same.

[0137]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, for example, in a synchronous DRAM or the like having a configuration in which the bit configuration can be switched as an option and having a reduction test function, for example, provided between a write amplifier and a main amplifier of each bank and a data input buffer and a data output buffer. Eight bits of the 16-bit data bus are fixedly formed irrespective of the bit configuration and shared for the × 4 bit and × 8 bit configuration, and the remaining 8 bits are selectively available only when the metal option is × 16 bit. Formed. In addition, these data buses are used together as test data buses for reduction tests, and bonding options, that is, bonding between predetermined pads, is selectively performed on the external terminal side, the write amplifier side, and the main amplifier side. A data selection circuit for switching the data transmission path. As a result, the required number of data buses is reduced, the layout required area is reduced, and the synchronous DRA
The chip size of M can be reduced, and the number of layout design steps for switching the bit configuration and the number of verification steps can be reduced, and the layout of the synchronous DRAM can be made more efficient.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

FIG. 2 is a block diagram showing an embodiment for explaining a mat configuration and bit allocation of banks included in the synchronous DRAM of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a bit configuration switching circuit included in the synchronous DRAM of FIG. 1;

FIG. 4 is a circuit diagram showing one embodiment of an input multiplexer included in the synchronous DRAM of FIG. 1;

FIG. 5 is a circuit diagram showing one embodiment of a unit input multiplexer constituting the input multiplexer of FIG. 4;

FIG. 6 is a circuit diagram showing one embodiment of an input data selection circuit included in the synchronous DRAM of FIG. 1;

FIG. 7 is a circuit diagram showing one embodiment of a unit input data selection circuit included in the input data selection circuit of FIG. 6;

8 is a circuit diagram showing one embodiment of a unit write amplifier and a unit main amplifier included in the write amplifier and the main amplifier of the synchronous DRAM of FIG. 1;

FIG. 9 is a circuit diagram showing one embodiment of a reduction test circuit included in the synchronous DRAM of FIG. 1;

FIG. 10 is a circuit diagram showing one embodiment of an output multiplexer included in the synchronous DRAM of FIG. 1;

FIG. 11 is a circuit diagram showing one embodiment of a unit output multiplexer included in the output multiplexer of FIG. 10;

12 is a connection diagram showing one embodiment of a × 4 bit configuration of a data input related circuit included in the synchronous DRAM of FIG. 1;

FIG. 13 is a connection diagram showing one embodiment of a data input related circuit included in the synchronous DRAM of FIG. 1 in a × 8-bit configuration;

14 is a connection diagram showing one embodiment of a data input related circuit included in the synchronous DRAM of FIG. 1 in a × 16-bit configuration;

FIG. 15 is a correspondence diagram showing one embodiment for explaining a relationship between a write data bus and a unit data input buffer of the synchronous DRAM of FIG. 1;

FIG. 16 is a correspondence diagram showing an embodiment for explaining a relationship between a unit write amplifier and a write data bus of the synchronous DRAM of FIG. 1;

17 is a connection diagram showing one embodiment of a × 4 bit configuration of a data output related circuit included in the synchronous DRAM of FIG. 1;

FIG. 18 is a connection diagram showing one embodiment of a data output related circuit included in the synchronous DRAM of FIG. 1 in a × 8-bit configuration;

FIG. 19 is a connection diagram showing one embodiment of a data output related circuit included in the synchronous DRAM of FIG. 1 in a × 16-bit configuration;

FIG. 20 is a correspondence diagram showing an embodiment for explaining a relationship between a unit main amplifier and a read data bus of the synchronous DRAM of FIG. 1;

21 is a correspondence diagram showing one embodiment for explaining a relationship between a read data bus of the synchronous DRAM of FIG. 1, a unit main amplifier, and a reduction test circuit;

[Explanation of symbols]

BNK0 to BNK3 ... bank, MARY ... memory array, RD ... row address decoder, SA ... sense amplifier, CD ... column address decoder, IS ... input data selection circuit, WA ... write amplifier, MA ... Main amplifier, TC: Reduction test circuit, AB: Address buffer, RA: Row address register, BA: Bank address register, BS: Bank selection circuit, CC
... Column address counter, CR command register, DIB data input buffer, MXI input multiplexer, WB0B to WBFB inverted write data bus, RB0B to RBFB inverted read data bus, MXO output multiplexer , DOB... Data output buffer, BC... Bit configuration switching circuit, TG
... Timing generation circuit. D0 to DF: data or input / output terminals thereof, CLK: clock signal or input terminal thereof, CKE: clock enable signal or input terminal thereof, CSB: chip selection signal or input terminal thereof, RA
SB: Row address strobe signal or its input terminal, CASB: Column address strobe signal or its input terminal, WEB: Write enable signal or its input terminal, DQM: Data mask signal or its input terminal, A0 to A13 ... Address signal or its input terminal.
IS0 ... input data selection circuit, UWA0 to UWAF ...
... Unit write amplifier, CD0 * -CDF * ... Complementary common data line, MAT0-MATF ... Memory mat, UM
A0 to UMAF ... Unit main amplifier, TC00 to TC
01, TC10 to TC11, TC20 to TC21, TC
30 to TC31 reduction test circuit. PVEE: ground potential pad, PB: bit configuration switching pad, BW ...
... bonding wire. UIB0 to UIBF ... unit data input buffer, DI0B to DIFB ... data input buffer output signal, UMXI0 to UMXIF ... unit input multiplexer, CSI1 to CSIE ... connection switching circuit. UIS0 to UISF ... Unit data input selection circuit. UMXO2 to UMXOD ... unit output multiplexer, CSO1 to CSOE ... connection switching circuit, DO0
B to DOFB... Output multiplexer output signals. IS0
To IS3 ... input data selection circuit, WA0 to WA3 ...
Light amplifier. MA0-MA3 ... Main amplifier, UO
B0 to UOBF: unit data output buffer, TD00
TD01, TD10 to TD11, TD20 to TD2
1, TD30 to TD31 ... reduction test circuit output signal. P
1-PI ... P-channel MOSFET, N1-NC ...
... N-channel MOSFET, G1 to G8, transfer gate, V1 to Vy, CMOS inverter, NA
1 to NAE: NAND gate, NO1 to NO6, NOR gate, AG1, AND gate, FF1, flip-flop.

Claims (8)

[Claims] An external terminal to which storage data is input or output; and an external terminal for transmitting the storage data to a predetermined internal circuit; and a predetermined bit is selectively formed according to a bit configuration. A data bus that is fixedly formed regardless of the bit configuration, and is provided on the external terminal side or the internal circuit side of the data bus, and is stored by selectively performing bonding between predetermined pads according to the bit configuration. And a data selection circuit for selectively transmitting data to the external terminal side or the internal circuit side in a predetermined combination. 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device includes a reduction test circuit, wherein a predetermined bit of said data bus is used for transmitting a test result by said reduction test circuit. A semiconductor memory device characterized by the above. 3. The storage device according to claim 2, wherein the storage data is composed of a plurality of bytes, and the reduction test by the reduction test circuit is performed in byte units of the storage data. A semiconductor memory device wherein test results of each byte of data are transmitted in parallel via corresponding bits of the data bus. 4. The test result according to claim 2, wherein the test result by said reduction test circuit is transmitted through a predetermined bit of said data bus to which said storage data is transmitted in a predetermined bit configuration, and to a bit configuration. A semiconductor memory device which is transmitted in the same combination regardless of the type. 5. The data bus according to claim 1, wherein the data bus includes a write data bus for transmitting write data, and a read data bus for transmitting read data. Wherein the internal circuit includes a write amplifier and a main amplifier, wherein the main amplifier selectively outputs an output signal to the read data bus in accordance with a first bus output control signal. An output circuit, wherein the reduction test circuit includes a second bus output circuit for selectively outputting a test result to the read data bus in accordance with a second bus output control signal; The data selection circuit is provided on the external terminal side of the write data bus, and selectively selects write data input via the external terminal in a predetermined combination. A first data selection circuit for transmitting the write data to the write data bus; and a write data bus provided on the write amplifier side of the write data bus for selectively writing the write data transmitted via the write data bus in a predetermined combination. A second data selection circuit for transmitting the data to the amplifier; and a read data bus provided on the external terminal side of the read data bus and selectively transmitting read data transmitted via the read data bus in a predetermined combination to the external terminal side. And a third data selection circuit for transmitting the data. 6. The first data selection circuit according to claim 5, wherein the first data selection circuit is provided corresponding to the write data bus which is not formed in a predetermined bit configuration, and is selectively opened in the bit configuration. The third data selection circuit is provided corresponding to the read data bus which is not formed at the time of a predetermined bit configuration, and converts the corresponding read data at the time of the bit configuration into a predetermined logic. A semiconductor memory device including a second connection switching circuit for fixing to a level. 7. The semiconductor memory device according to claim 1, wherein the bit configuration is selectively × 4.
Bits, × 8 bits or × 16 bits, wherein the data bus comprises eight write data buses and read data buses which are constantly formed regardless of the bit configuration; A semiconductor memory device comprising: another eight write data buses and read data buses selectively formed when the device has a × 16 bit configuration. 8. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a synchronous DRAM. Semiconductor storage device.