JPH11177098A - Semiconductor device and manufacture of the same - Google Patents

Semiconductor device and manufacture of the same

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Publication number
JPH11177098A
JPH11177098A JP34100897A JP34100897A JPH11177098A JP H11177098 A JPH11177098 A JP H11177098A JP 34100897 A JP34100897 A JP 34100897A JP 34100897 A JP34100897 A JP 34100897A JP H11177098 A JPH11177098 A JP H11177098A
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Japan
Prior art keywords
semiconductor film
semiconductor device
convex
control electrode
contact
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP34100897A
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Japanese (ja)
Inventor
Hajime Akimoto
Yoshinobu Kimura
Masanobu Miyao
正信 宮尾
嘉伸 木村
秋元  肇
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Hitachi Ltd
株式会社日立製作所
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Priority to JP34100897A priority Critical patent/JPH11177098A/en
Publication of JPH11177098A publication Critical patent/JPH11177098A/en
Application status is Pending legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters

Abstract

PROBLEM TO BE SOLVED: To realize a thin film transistor capable of a high speed operation effective to a semiconductor device to be used for a liquid crystal display device or a display terminal or the like. SOLUTION: A recessed part is worked on an insulating substrate 101, and an amorphous semiconductor film is accumulated on the insulating substrate 101. The surface of the amorphous semiconductor film is heated and scanned by an excimer laser, and a polycrstal semiconductor film 102 is formed. A first impurity area 103, a second impurity area 104, and an insulator film area 105 are formed in the polycrystal semiconductor film 102.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は特に高性能な薄膜トランジスタを有する半導体装置に関する。 The present invention relates to relates to a semiconductor device having a particularly high performance thin film transistor.

【0002】 [0002]

【従来の技術】従来技術による半導体装置とその製造方法について図2を用いて説明する。 BACKGROUND OF THE INVENTION prior art semiconductor device according to a method for manufacturing the same will be described with reference to FIG.

【0003】図2(a)に示すように、ガラス基板201 [0003] As shown in FIG. 2 (a), a glass substrate 201
の上に非晶質シリコン薄膜202を堆積する。 Depositing an amorphous silicon thin film 202 on the. 次に図2 Next, FIG. 2
(b)に示すように、非晶質シリコン薄膜の表面を線状のエキシマレーザ204で203の方向に走査すると、非晶質シリコン薄膜202は、エキシマレーザ204によって加熱され、非晶質構造から多結晶構造に変化する。 (B), when scanning in the direction of the surface of the amorphous silicon thin film at a linear excimer laser 204 203, amorphous silicon film 202 is heated by the excimer laser 204, an amorphous structure changes in the polycrystalline structure.
非晶質シリコン膜202の表面全体をエキシマレーザ2 Excimer laser 2 the entire surface of the amorphous silicon film 202
04で走査加熱すると、図2(c)に示すような多結晶シリコン薄膜が形成される。 04 Scanning heating, the polycrystalline silicon thin film as shown in FIG. 2 (c) is formed. 図2(c)において多結晶シリコン薄膜はシリコン結晶粒から構成されており、結晶粒間に、結晶粒界206が形成されている。 Polycrystalline silicon thin film in FIG. 2 (c) are composed of silicon grains, between crystal grains, grain boundaries 206 are formed. 以上のプロセスはレーザ加熱プロセスと呼ばれ、ガラスなどの低融点材料の基板上に薄膜トランジスタを形成するための高品質な多結晶シリコン薄膜を製造する際に用いられる。 Above process is called a laser heating process is used in producing a high quality polycrystalline silicon thin film for forming a TFT on a substrate of low melting point material such as glass. これらに関しては、たとえば、"1996 Society for Inform For these, for example, "1996 Society for Inform
ation Display International Symposium Digest of Te ation Display International Symposium Digest of Te
chnical Papers, pp.17-20"や、"IEEE Transactions on chnical Papers, pp.17-20 "and," IEEE Transactions on
Electron Devices, vol.43, no.9, 1996. pp.1454-145 Electron Devices, vol.43, no.9, 1996. pp.1454-145
8"等に詳しい。 Familiar with the 8 "or the like.

【0004】図2(c)の多結晶シリコン薄膜を用いてトランジスタを形成したのが図2(d)である。 [0004] Figure 2 is to that transistor is formed using a polycrystalline silicon thin film (c) is 2 (d). 多結晶シリコン薄膜205の上部には、シリコン酸化膜などのゲート絶縁膜208が設けられいる。 At the top of the polycrystalline silicon thin film 205, the gate insulating film 208 such as a silicon oxide film is provided. さらにソース不純物注入領域207、ドレイン不純物注入領域209が設けられている。 Moreover source impurity implanted region 207, the drain impurity implantation region 209 is provided. ソース、ドレイン領域、およびゲート絶縁膜上にゲート電極を設け、ゲート電極の電圧によって、ソースとドレイン間の電流を制御できる。 Source and drain regions, and a gate electrode on the gate insulating film provided by the voltage of the gate electrode can control the current between the source and the drain.

【0005】図3は、シリコン結晶粒の大きさの照射レーザエネルギーに対する依存性を示している。 [0005] Figure 3 shows the dependence of the silicon grains to the size irradiation of laser energy. レーザエネルギ密度が200mJ/cm 2以下のエネルギでは、シリコンは結晶化しないが、200mJ/cm 2を超えると結晶化が始まり、結晶粒の大きさはレーザエネルギ密度の増加とともに大きくなる。 In the laser energy density is 200 mJ / cm 2 or less of the energy is silicon does not crystallize but begin crystallization exceeds 200 mJ / cm 2, the crystal grain size increases with increasing laser energy density. しかしながら、レーザエネルギ密度が250mJ/cm 2を超えると、シリコン結晶粒は小さくなる。 However, when the laser energy density is more than 250 mJ / cm 2, the silicon crystal grains is reduced. 良好な特性をもつ多結晶シリコン薄膜トランジスタを作製するためには、シリコン結晶粒を大きくすればよいのでレーザのエネルギ密度を250mJ/cm 2にする。 To produce a polycrystalline silicon thin film transistor with good properties, the energy density of the laser to 250 mJ / cm 2 it is sufficient to increase the silicon grains. 上記従来におけるレーザエネルギ密度の値は、非晶質シリコン膜の性質(例えば、成長法、膜厚)に依存するため、異なることもある。 The value of the laser energy density in the prior art, because it depends on the nature of the amorphous silicon film (e.g., deposition, thickness), may be different. これらに関しては、たとえば、"AppliedPhysics Letters,vol.63,no.14,1993,pp.1 For these, for example, "AppliedPhysics Letters, vol.63, no.14,1993, pp.1
969-1971"等に詳しい。 969-1971 "familiar with like.

【0006】 [0006]

【発明が解決しようとする課題】上記従来技術では、ゲート電極下のシリコンのチャネル領域に存在する結晶粒の位置および結晶粒の大きさのばらつきに起因して、トランジスタ間で性能にばらつきが生じる。 In THE INVENTION to be solved INVENTION The above prior art, due to the variation of the grain position and grain size present in the channel region of the silicon under the gate electrode, variations in performance between the transistors .

【0007】 [0007]

【課題を解決するための手段】上記課題は、絶縁基板面に凸または凹部を設けたときに、この面に接して形成される半導体膜中にレーザ加熱により生じる熱分布の変化を積極的に利用して、結晶粒核の発生の位置および結晶粒の大きさを制御することにより解決できる。 Above problems SUMMARY OF THE INVENTION, when provided with a convex or concave portion on the insulating substrate surface, the change in heat distribution caused by laser heating the semiconductor film formed in contact with the surface positively using, it can be solved by controlling the position and the crystal grain size of the occurrence of grain nuclei.

【0008】具体的には、本絶縁基板上にこれに接して形成された多結晶半導体膜と、この多結晶半導体膜に電流を流すための第一および第二の導電領域と、多結晶半導体膜上にこれに接して形成された絶縁膜と、この絶縁膜上にこれに接して形成された第一および第二の導電領域間に流れる電流を制御するために制御電極とを有する半導体装置において、制御電極下の領域における多結晶半導体膜の結晶粒の体積の平均値が、制御電極下以外の領域における多結晶半導体膜の結晶粒の体積の平均値よりも大きい半導体装置等により解決できる。 [0008] More specifically, a polycrystalline semiconductor film formed by this contact with the insulating substrate, and first and second conductive regions for passing a current through the polycrystalline semiconductor film, a polycrystalline semiconductor a semiconductor device having an insulating film formed in contact with this on the membrane, and a control electrode for controlling a current flowing between the first and second conductive regions formed in contact with it on the insulating film in the average value of the grain volume of the polycrystalline semiconductor film in the region under the control electrode, it can be solved by a polycrystalline semiconductor film semiconductor device larger than the average value of the grain volume, such as in the area other than under the control electrode .

【0009】 [0009]

【発明の実施の形態】まず、図1を用い本発明の概要を説明する。 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of the present invention using FIG. 絶縁基板101に凹部を加工形成した後、絶縁基板101の上に非晶質半導体膜を堆積する。 After the recess has been processed and formed on the insulating substrate 101, depositing an amorphous semiconductor film on an insulating substrate 101. 非晶質半導体膜の表面をエキシマレーザで加熱走査して多結晶半導体膜102を形成する。 The surface of the amorphous semiconductor film to form a polycrystalline semiconductor film 102 is heated scanning an excimer laser. 多結晶半導体膜102に第一不純物領域103、第二不純物領域104、絶縁体膜領域105を設ける。 The first impurity regions 103 to the polycrystalline semiconductor film 102, the second impurity region 104, an insulating film region 105.

【0010】以下、本発明の実施例の多結晶薄膜トランジスタを、図4〜図7を用いて説明する。 [0010] Hereinafter, a polycrystalline thin film transistor embodiment of the present invention will be described with reference to FIGS.

【0011】図4に本発明による多結晶半導体膜の形成過程を示す。 [0011] A process of forming a polycrystalline semiconductor film according to the present invention in FIG. まず、絶縁基板402(例えば、ガラス、 First, an insulating substrate 402 (e.g., glass,
溶融石英、サファイアなど)に、下に凸の形状の溝を機械加工やレーザ、エッチングプロセス等で加工する。 Fused quartz, sapphire, etc.), machining a groove in the shape of a downwardly convex machining or laser, an etching process or the like. 次に該絶縁基板402の上に半導体薄膜401(例えばS Then the semiconductor thin film 401 on the insulating substrate 402 (e.g., S
i、Ge、SiGeなど)を化学気相成長法やスパッタ法などを用いて堆積する。 i, Ge, deposited using, etc.) SiGe such as chemical vapor deposition or sputtering. 該半導体膜401の厚さは50 nm以下が望ましい。 The thickness of the semiconductor film 401 is less desirable 50 nm. 次に該半導体薄膜401の表面をエキシマレーザ404(KrF、XeClなど)で、403の方向に走査する。 Then the surface excimer laser 404 of the semiconductor thin film 401 (KrF, XeCl, etc.), is scanned in the direction of 403. エキシマレーザ404のエネルギは、該半導体膜401の製法と厚みに依存する。 Energy of the excimer laser 404 is dependent on the method and the thickness of the semiconductor film 401. あらかじめ最適値を調べておく。 Know the pre-optimal value. エキシマレーザの照射エネルギの最適値は、該半導体膜が微結晶化状態になるところのエネルギ値から+100mJ/cm 2以下で行うことが望ましい。 The optimum value of the irradiation energy of the excimer laser, the semiconductor film is desirably performed from the energy value at which become microcrystalline state + 100 mJ / cm 2 or less. また、エキシマレーザビームの形状は、点状でも線状でもよい。 The shape of the excimer laser beam may be linear in punctate.
エキシマレーザによる走査が終ると半導体膜は、405 Semiconductor film when scanned by the excimer laser is completed, 405
の微結晶領域と406の多結晶領域に形成される。 It is formed on the polycrystalline region of the microcrystalline region and 406. ここで、多結晶領域は単結晶領域であることも含む。 Here, also it includes polycrystalline region is a single crystal region. なお結晶粒界は、図中では省略している。 Incidentally grain boundaries are not shown in the figure. また、多結晶領域は、絶縁基板402の溝の上に形成されている。 Further, the polycrystalline region is formed on the groove of the insulating substrate 402. 該微結晶領域405にソース電極のための第一の不純物領域と、ドレイン電極のための第二の不純物領域を形成し、 A first impurity region for the source electrode in the microcrystalline region 405, to form a second impurity region for the drain electrode,
多結晶領域にゲート電極のための絶縁膜を設けて、ソース、ドレイン、ゲートに金属電極を設けると、(d)の806の薄膜トランジスタとなる。 And an insulating film for the gate electrode to the polycrystalline region, a source, a drain, providing a metal electrode on the gate, the 806 thin film transistor of (d). (d)では、隣あうトランジスタ807の微結晶領域804をエッチングして素子分離を行っているまた、上記絶縁基板502、6 In (d), also a microcrystalline region 804 next to meet the transistor 807 is etched doing isolation, the insulating substrate 502,6
02において、溝の形状は図5の501のような点状の形や図6の601のような線状の形でもよい。 In 02, the shape of the groove may be a linear shape, such as a point-like shape and Figure 6 of 601, such as 501 in FIG. 5. 線状の場合、溝の形状はゲート電極803の幅に沿って並行、即ちチャネル電流に対して垂直であることがチャネル電流の均一化のためには望ましい。 For linear, the shape of the groove is parallel along the width of the gate electrode 803, i.e., for equalizing things channel current is perpendicular to the channel current desired.

【0012】また、線状の溝の方向と垂直方向にソース、ドレイン領域を設けて、さらに上記線状溝上に第一、第二、…第nゲート電極とそれぞれに対して多結晶半導体領域を設けることで高性能のゲートアレイが形成される。 Further, the linear groove direction and the source in a vertical direction, by providing a drain region, further first in the linear groove on the second, ... the polycrystalline semiconductor region with respect to the n-th gate electrode respectively high-performance gate array is formed by providing.

【0013】また、上記絶縁基板402において、溝の形状は、図7の701に示すようなくさび型のV溝でも、702のような半円形の溝、さらに矩形の溝でもよい。 Further, in the insulating substrate 402, the shape of the groove, in the V-groove of wedge-shaped as shown at 701 in FIG. 7, the semi-circular grooves such as 702, may be further rectangular groove. 半円形は製造時に異物がつきにくいという長所があり、矩形は異方性エッチングで加工が可能である。 Semicircular has the advantage foreign matter hardly attached at the time of manufacture, rectangles are possible processing by anisotropic etching.

【0014】また、上記絶縁基板402において、表面の形状は、下に凸の溝以外に703、704のような上に凸の突起でもよい。 Further, in the insulating substrate 402, the shape of the surface may be a convex projection on as 703 and 704 in addition to the groove of the downwardly convex.

【0015】 [0015]

【発明の効果】本発明によれば、液晶ディスプレイ装置や表示端末等に用いる半導体装置に有効な高速動作可能な薄膜トランジスタを実現できる。 According to the present invention can be realized an effective high-speed operable TFT in a semiconductor device used in a liquid crystal display device or a display terminal or the like.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施例における多結晶薄膜トランジスタの断面構造図である。 1 is a sectional view of a polycrystalline thin film transistor according to an embodiment of the present invention.

【図2】従来の多結晶薄膜トランジスタの製造工程断面図である。 2 is a manufacturing process sectional views of a conventional polycrystalline thin film transistor.

【図3】レーザ結晶化法における多結晶半導体膜の結晶粒の大きさの、レーザエネルギ密度との関係を示す図である。 [Figure 3] of the crystal grain size of the polycrystalline semiconductor film in the laser crystallization method is a diagram showing the relationship between laser energy density.

【図4】本発明の一実施例における多結晶薄膜トランジスタの製造工程断面図である。 4 is cross sectional view of a manufacturing process of a polycrystalline thin film transistor according to an embodiment of the present invention.

【図5】本発明の他の実施例の、(a)は絶縁基板の平面図、(b)はその断面図である。 , Of another embodiment of the present invention; FIG (a) is a plan view, (b) a sectional view of an insulating substrate.

【図6】本発明の他の実施例の、(a)は絶縁基板の平面図、(b)はその断面図である。 , Of another embodiment of the invention; FIG (a) is a plan view, (b) a sectional view of an insulating substrate.

【図7】(a)(b)(c)は、本発明の他の実施例の絶縁基板の断面図である。 7 (a) (b) (c) is a cross-sectional view of an insulating substrate of another embodiment of the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

101…絶縁基板、102…多結晶半導体、103…ドレイン不純物領域、104…ソース不純物領域、105 101 ... insulating substrate, 102 ... polycrystalline semiconductor, 103 ... drain impurity regions, 104 ... source impurity regions, 105
…ゲート絶縁体領域、201…絶縁基板、202…非晶質シリコン膜、203…エキシマレーザ走査方向、20 ... gate insulator region, 201: insulating substrate, 202 ... amorphous silicon film, 203 ... excimer laser scanning direction, 20
4…エキシマレーザ、205…多結晶シリコン膜、20 4 ... excimer laser, 205 ... polycrystalline silicon film, 20
6…結晶粒界、207…ソース不純物領域、208…ゲート絶縁物領域、209…ドレイン不純物領域、301 6 ... grain boundary, 207 ... source impurity region, 208 ... gate insulator region, 209 ... drain impurity regions, 301
…結晶粒の大きさのレーザエネルギ密度依存性、401 ... laser energy density dependence of the crystal grain size, 401
…非晶質半導体膜、402…絶縁基板、403…エキシマレーザ走査方向、404…エキシマレーザ、405… ... an amorphous semiconductor film, 402: insulating substrate, 403 ... excimer laser scanning direction, 404 ... excimer laser, 405 ...
微結晶領域、406…多結晶領域、501…溝、502 Microcrystalline region, 406 ... polycrystalline region, 501 ... groove, 502
…絶縁基板の上面、503…絶縁基板の側面、601… ... upper surface of the insulating substrate, 503: insulating substrate side of 601 ...
溝、602…絶縁基板の上面、603…絶縁基板の側面、701…V型溝、702…半円形溝、703…楔型突起 704…円形突起、801…絶縁基板、802…ソース不純物領域、803…ゲート絶縁膜領域、804…ドレイン不純物領域、805…多結晶チャネル領域、806 Groove, 602 ... upper surface of the insulating substrate, 603: insulating substrate side of, 701 ... V-groove, 702 ... semi-circular groove, 703 ... wedge projections 704 ... circular projection, 801: insulating substrate, 802 ... source impurity regions, 803 ... gate insulating film region, 804 ... drain impurity regions, 805 ... polycrystalline channel region, 806
…トランジスタ1、807…トランジスタ2。 ... transistor 1,807 ... transistor 2.

Claims (18)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】絶縁基板上にこれに接して形成された多結晶半導体膜と、該多結晶半導体膜に電流を流すための第一および第二の導電領域と、上記多結晶半導体膜上にこれに接して形成された絶縁膜と、該絶縁膜上にこれに接して形成された上記第一および第二の導電領域間に流れる電流を制御するために制御電極とを有する半導体装置において、上記制御電極下の領域における上記多結晶半導体膜の結晶粒の体積の平均値は、上記制御電極下以外の領域における上記多結晶半導体膜の結晶粒の体積の平均値よりも大きいことを特徴とする半導体装置。 And 1. A polycrystalline semiconductor film formed by this contact on an insulating substrate, and the first and second conductive regions for passing a current through the polycrystalline semiconductor film, on the polycrystalline semiconductor film an insulating film formed in contact with this, in a semiconductor device having a control electrode for controlling the current flowing in between the formed contact first and second conductive regions which on the insulating film, average value of the grain volume of the polycrystalline semiconductor film in the region under the control electrode, and being greater than the average value of the grain volume of the polycrystalline semiconductor film in a region other than under the control electrode semiconductor device.
  2. 【請求項2】絶縁基板上にこれに接して形成された多結晶半導体膜と、該多結晶半導体膜に電流を流すための第一および第二の導電領域と、上記多結晶半導体膜上にこれに接して形成された絶縁膜と、該絶縁膜上にこれに接して形成された上記第一および第二の導電領域間に流れる電流を制御するために制御電極とを有する半導体装置において、上記制御電極下の領域における上記絶縁基板の上記多結晶半導体膜に接する面は少なくとも一部で凸または凹部を有しており、かつ上記制御電極下の領域における上記多結晶半導体膜の結晶粒の体積の平均値は、 2. A polycrystalline semiconductor film formed by this contact on an insulating substrate, and the first and second conductive regions for passing a current through the polycrystalline semiconductor film, on the polycrystalline semiconductor film an insulating film formed in contact with this, in a semiconductor device having a control electrode for controlling the current flowing in between the formed contact first and second conductive regions which on the insulating film, surface in contact with the polycrystalline semiconductor film of the insulating substrate in the region under the control electrode has a convex or concave at least in part, and the crystal grains of the polycrystalline semiconductor film in the region under the control electrode the average value of the volume,
    上記制御電極下以外の領域における上記多結晶半導体膜の結晶粒の体積の平均値よりも大きいことを特徴とする半導体装置。 Wherein a greater than the average value of the grain volume of the polycrystalline semiconductor film in a region other than under the control electrode.
  3. 【請求項3】絶縁基板上にこれに接して形成された多結晶半導体膜と、該多結晶半導体膜に電流を流すための第一および第二の導電領域と、上記多結晶半導体膜上にこれに接して形成された絶縁膜と、上記第一および第二の導電領域間に流れる電流を制御するために該絶縁膜上にこれに接して形成された制御電極とを有する半導体装置において、上記制御電極下の領域における上記絶縁基板の上記多結晶半導体膜に接する面は少なくとも一部で凸または凹部を有していることを特徴とする半導体装置。 3. A polycrystalline semiconductor film formed by this contact on an insulating substrate, and the first and second conductive regions for passing a current through the polycrystalline semiconductor film, on the polycrystalline semiconductor film an insulating film formed in contact with this, in a semiconductor device having a control electrode formed in contact with it on the insulating film in order to control the current flowing between the first and second conductive regions, wherein a surface in contact with the polycrystalline semiconductor film of the insulating substrate in the region under the control electrode has a convex or concave at least in part.
  4. 【請求項4】上記凸または凹部を含む上記制御電極下の領域における上記絶縁基板面の高低差は、上記制御電極下以外の領域における上記絶縁基板の上記多結晶半導体膜に接する面の高低差よりも大きいことを特徴とする請求項3記載の半導体装置。 Height difference wherein the insulating substrate surface in regions under the control electrodes, including the convex or concave portions, the height difference between the surface in contact with the polycrystalline semiconductor film of the insulating substrate in a region other than under the control electrode the semiconductor device according to claim 3, wherein greater than.
  5. 【請求項5】上記制御電極下の領域の上記凸または凹部は島状であることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。 5. A semiconductor device according to any one of claims 1 to 4, characterized in that the convex or concave portion of the area under the control electrode is an island shape.
  6. 【請求項6】上記制御電極下の領域の上記凸または凹部は直線状であることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。 6. The semiconductor device according to any one of claims 1 to 4, characterized in that the convex or concave portion of the area under the control electrode is linear.
  7. 【請求項7】上記制御電極下の領域の上記凸または凹部は少なくとも一方向に対する断面形状がくさび型であることを特徴とする請求項5又は6に記載の半導体装置。 7. A semiconductor device according to claim 5 or 6 the convex or concave portion of the area under the control electrode is the cross-sectional shape for at least one direction, characterized in that a wedge.
  8. 【請求項8】上記制御電極下の領域の上記凸または凹部は少なくとも一方向に対する断面形状が半円形であることを特徴とする請求項5又は6に記載の半導体装置。 8. The semiconductor device according to claim 5 or 6 the convex or concave portion of the area under the control electrode is the cross-sectional shape for at least one direction, characterized in that a semi-circular.
  9. 【請求項9】上記制御電極下の領域の上記凸または凹部は少なくとも一方向に対する断面形状が矩形であることを特徴とする請求項5又は6に記載の半導体装置。 9. The semiconductor device according to claim 5 or 6 the convex or concave portion of the area under the control electrode is the cross-sectional shape for at least one direction characterized in that it is a rectangle.
  10. 【請求項10】上記凸または凹部の直線状の方向は、上記第一および第二の導電領域間に流れる電流の方向に対して垂直であることを特徴とする請求項6記載の半導体装置。 10. A linear direction of the convex or concave portion, the semiconductor device according to claim 6, characterized in that the perpendicular to the direction of the current flowing between the first and second conductive regions.
  11. 【請求項11】上記電流の通路となる上記多結晶半導体膜が複数形成されていることを特徴とする請求項10記載の半導体装置。 11. The semiconductor device according to claim 10, characterized in that the polycrystalline semiconductor film serving as the passage of the current are formed.
  12. 【請求項12】絶縁基板に凸または凹部を形成する工程と、該凸または凹部を含め上記絶縁基板に接して半導体膜を形成する工程と、該半導体膜にレーザを照射して多結晶半導体膜を形成する工程と、該多結晶半導体膜に接して絶縁膜を形成する工程と、該多結晶半導体膜に導電性を呈する不純物を導入して第一および第二の導電領域を形成する工程と、上記絶縁膜に接して上記第一および第二の導電領域間の上記多結晶半導体膜に流れる電流を制御するための制御電極を形成する工程を有することを特徴とする半導体装置の製造方法。 12. A process for forming a convex or concave portion on the insulating substrate, forming a semiconductor film in contact with the insulating substrate including the convex or concave portion, a polycrystalline semiconductor film by irradiating a laser beam to the semiconductor film forming, and forming and forming an insulating film in contact with the polycrystalline semiconductor film, the first and second conductive regions by introducing an impurity that exhibits conductivity polycrystalline semiconductor film a method of manufacturing a semiconductor device characterized by comprising a step of forming a control electrode for controlling the current flowing in contact with the insulating film in the polycrystalline semiconductor film between said first and second conductive regions.
  13. 【請求項13】上記凸または凹部は島状に形成することを特徴とする請求項12記載の半導体装置の製造方法。 13. The method according to claim 12, wherein the said projection or recess is formed in an island shape.
  14. 【請求項14】上記凸または凹部は直線状に形成することを特徴とする請求項12記載の半導体装置の製造方法。 14. The method according to claim 12, wherein the said projection or recess is formed in a linear shape.
  15. 【請求項15】上記第一および第二の導電領域は上記凸または凹部の形成領域以外の領域に形成することを特徴とする請求項12乃至14のいずれか一項に記載の半導体装置の製造方法。 15. The first and second conductive regions manufacturing a semiconductor device according to any one of claims 12 to 14, characterized in that formed in the region other than the formation area of ​​the convex or concave Method.
  16. 【請求項16】上記凸または凹部は、少なくとも一方向に対する断面形状をくさび型に形成することを特徴とする請求項12乃至15のいずれか一項に記載の半導体装置の製造方法。 16. the convex or concave portion, a method of manufacturing a semiconductor device according to any one of claims 12 to 15, characterized in that to form the cross-sectional shape for at least one direction in a wedge shape.
  17. 【請求項17】上記凸または凹部は、少なくとも一方向に対する断面形状を半円形に形成することを特徴とする請求項12乃至15のいずれか一項に記載の半導体装置の製造方法。 17. the convex or concave portion, a method of manufacturing a semiconductor device according to any one of claims 12 to 15, characterized in that to form the cross-sectional shape for at least one direction in a semi-circular.
  18. 【請求項18】上記凸または凹部は、少なくとも一方向に対する断面形状を矩形に形成することを特徴とする請求項12乃至15のいずれか一項に記載の半導体装置の製造方法。 18. the convex or concave portion, a method of manufacturing a semiconductor device according to any one of claims 12 to 15, characterized in that to form the cross-sectional shape for at least one direction in a rectangular.
JP34100897A 1997-12-11 1997-12-11 Semiconductor device and manufacture of the same Pending JPH11177098A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670638B2 (en) 2000-09-25 2003-12-30 Hitachi, Ltd. Liquid crystal display element and method of manufacturing the same
JP2015130536A (en) * 2011-04-22 2015-07-16 株式会社半導体エネルギー研究所 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670638B2 (en) 2000-09-25 2003-12-30 Hitachi, Ltd. Liquid crystal display element and method of manufacturing the same
JP2015130536A (en) * 2011-04-22 2015-07-16 株式会社半導体エネルギー研究所 Semiconductor device
US9660095B2 (en) 2011-04-22 2017-05-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

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