JPH11175024A - Plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a plasma display device capable of coping with the magnifying of a display screen and the increasing of the number of display gradations with an inexpensive constitution without raising a reading rate from a memory in which image information is stored. SOLUTION: A write control part 1 writes video data in a frame memory 6 by summarizing them by every same bit data in advance while performing a pre-processing with respect to them preliminarily and making the data correspond to the arrangement of display pixels of a plasma display panel 4. The dual port type memory provided with a write port and a read port is used as the frame memory 6. Consequently, address data can be directly supplied from the frame memory 6 to address drivers 3, 5 without changing the order. Thus, the data transfer between the write control part 1 and the frame memory 6 is made highly efficient and the device can cope with the magnifying of the display screen and the increasing of the number of display gradations without raising a data transfer rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to address control of a plasma display device and the like, and more particularly to a technique for rearranging video signal data.

[0002]

2. Description of the Related Art In a conventional AC plasma display device using an address / display period separated type subfield method, for example, in the case of 8 subfields, as shown in FIG. , The relative ratio of luminance is 1: 2: 4: 8: 16: 32: 6
It is divided into eight subfields SF1 to SF8 of 4: 128.

[0003] Each subfield is composed of an address period of a head portion and a light emission sustaining period following the address period. The light emission sustaining period is sequentially lengthened, and 1: 2: 4: 8: 1.
By scanning during a light emission period of a ratio of 6: 32: 64: 128, a multi-gradation video signal is displayed by combining the luminances of the eight subfields SF1 to SF8. Therefore, the reading of the subfield data must be performed at least eight times in one frame period, and it is necessary to transfer the data at a high speed as the display screen is enlarged and the number of display gradations is increased.

A conventional plasma display device has a configuration as shown in Japanese Patent Application Laid-Open No. 7-7702. This configuration will be described with reference to FIGS. FIG. 13 is an overall configuration diagram of the plasma display device, and FIG. 14 is a diagram showing the I / O buffer unit 9 shown in FIG.
It is an internal block diagram of.

[0005] In FIG. 13 and FIG. 14, video data input from a video input terminal 7 is subjected to processing such as blanking in a display control unit 10, and then is subjected to an address from an address control unit 91 of an I / O buffer unit 9. The data is stored in the frame memory 6 from the data control unit 92 according to the signal.

The data stored in the frame memory 6 is
Under the address control of the address control unit 91, the data is read out to the data control unit 92 corresponding to the part to be displayed on the screen, and the bit selection unit 93 performs bit selection corresponding to the subfield to be displayed. The data bit-selected by the bit selection unit 93 is supplied to the address drivers 3 and 5,
Information to be displayed is written on the plasma display panel 4.

[0007]

By the way, the reading of the subfield data must be performed the same number of times as the number of display gradations in one frame period, and with the enlargement of the display screen and the increase in the number of display gradations. It is necessary to transfer the data at high speed. That is, the reading speed of the data read from the frame memory 6 needs to be such that the reading period of the data from the frame memory 6 is at least a fraction of the subfield period of one frame of the display image data.

For example, 1024 (H) × 768 (V)
(× 3 colors) dot display, frame frequency 70H
In the case of displaying 8 subfields in z, the speed of reading from the frame memory 6 to the I / O buffer unit 9 for each pixel data can be as high as 1.3 GHz.

[0009] However, this speed is difficult to achieve with current semiconductor technology. Therefore, in the conventional plasma display device, enlargement of the display screen,
It was difficult to increase the number of display gradations.

Therefore, by increasing the output data bus width of the frame memory 6 to increase the amount of data that can be transferred at one time, or by devising the configuration of the frame memory 6,
It can be improved to some extent. However, an increase in the data bus width causes an increase in the board area, etc., resulting in an increase in cost,
This is not preferable because it causes an increase in the size of the device and an increase in power consumption.

An object of the present invention is to realize a plasma display device which can cope with an enlargement of a display screen and an increase in the number of display gradations with an inexpensive configuration without having to increase the reading speed from a memory for storing video information. It is another object of the present invention to realize a writing control device for the memory and a driving device for controlling writing and reading to the memory.

[0012]

In order to achieve the above object, the present invention is configured as follows. (1) In a plasma display device that constitutes one frame by a plurality of subfields having different luminance relative ratios and light emission sustain periods and displays multi-gradation video signals on a plasma display panel, the above-described subfield data is stored. Frame memory and video signal are input,
A write control unit that controls writing of the subfield data of the video signal to the frame memory; and an address driver that writes the subfield data stored in the frame memory to the plasma display panel. Storing the rearranged subfield data in the frame memory according to the specification of the input signal of the address driver and the position of the address driver in the plasma display panel; and storing the rearranged subfield data in the frame memory. Are read from the frame memory without changing the order, and are supplied to the address driver.

(2) Preferably, in the above (1),
The write control unit includes a line memory capable of storing at least two lines of video data in the horizontal direction.

(3) Preferably, in the above (1) or (2), the writing control section includes a bit developing section for selecting video data for each gradation, and the bit developing section includes at least: A first-stage shift register having a predetermined number of stages of a block having a predetermined number of bits; and a second-stage shift register for loading output data of each stage of the first-stage shift register. The data is loaded into the subsequent-stage shift register in a cycle, and the latter-stage shift register performs control so as to output the same gradation data from the loaded data.

(4) Preferably, the above (1),
In (2) or (3), assuming that one unit consisting of a predetermined number of bits is one word, the write control unit determines, according to the number of words that can be transferred to the frame memory at one time,
A burst memory is provided for collectively storing data to be written to the frame memory for the above-mentioned words that can be transferred at one time for each gradation.

(5) Preferably, the above (1),
In (2), (3) or (4), the write control unit may control the number of input bits of the address driver to be 4 × N.
(N is a natural number), and if one unit consisting of a predetermined number of bits is one word, the R, G, and B data of the video input signal input to the writing control unit is 4 × M (M is a natural number) word unit And a data number conversion unit for performing rearrangement.

(6) A sub-field of a plasma display device for displaying a multi-gradation video signal on a plasma display panel by forming one frame by a plurality of sub-fields having different luminance relative ratios and light emission sustain periods. In a writing control device for controlling writing of the subfield data to a frame memory for storing data, a subfield of a video signal input to the writing control device according to an input specification of data to be written to the plasma display panel. Sort the data,
Write and store in the frame memory.

(7) Preferably, in the above (6),
A line memory capable of storing at least two lines of video data in the horizontal direction is provided.

(8) Preferably, in the above (6) or (7), a bit developing section for selecting video data for each gradation is provided, and this bit developing section has at least a predetermined number of bits. A first-stage shift register having a predetermined number of stages of blocks; and a second-stage shift register for loading output data of each stage of the first-stage shift register. The data of the first-stage shift register is stored in the second-stage shift register at a cycle of the number of blocks. After loading, the subsequent-stage shift register controls so as to output the same gradation data from the loaded data.

(9) Preferably, the above (6),
In (7) or (8), one of a predetermined number of bits
Assuming that the unit is one word, a burst memory is provided which collectively stores the data to be written in the frame memory for each gray level in correspondence with the number of words that can be transferred at one time to the frame memory.

(10) Preferably, the above (6),
In (7), (8) or (9), if the number of bits input to the frame memory is 4 × N (N is a natural number) and one unit consisting of a predetermined number of bits is one word, A data number conversion unit for rearranging R, G, and B data of an input video input signal in units of 4 × M (M is a natural number) words is provided.

(11) A driving apparatus for a plasma display apparatus for displaying a multi-gradation video signal on a plasma display panel by forming one frame by a plurality of subfields having different luminance relative ratios and different light emission maintaining periods. In the above, according to the input specification of the data to be written to the plasma display panel, the subfield data of the video signal is rearranged, written to the frame memory, and write control means for storing the subfield data, the subfield data stored in the frame memory Address signal forming means for forming an address signal corresponding to a display pixel of the plasma display panel based on the information.

The pre-processing is performed in advance on the data to be written in the frame memory, and the processing for combining the same gradation data in advance is performed. Thus, the address data is directly supplied to the address driver without passing through the I / O buffer unit. With this configuration, it is possible to cope with the enlargement of the display screen and the increase in the number of display gradations with an inexpensive configuration without increasing the reading speed from the memory that stores the video information.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an overall schematic block diagram showing a first embodiment of a plasma display device according to the present invention. In FIG. 1, 1 is a write control unit, 2 is a read control unit, 3 and 5 are address drivers, 4 is a plasma display panel, 6 is a dual port type frame memory having a write port and a read port, and 7 is an image. A signal input terminal 8 is an input terminal for a clock signal, a vertical and horizontal synchronization signal.

The video data input from the video input terminal 7 is stored in the frame memory 6 after the writing control unit 1 rearranges data corresponding to the location of the address driver 3. The read control unit 2 sets the most significant bit of the read address of the frame memory 6 to the terminal 1c.
To the write control unit 1 via the
Controls the write and read addresses to the frame memory 6 so that they do not collide. The data in the frame memory 6 is read in accordance with a read address and a control signal input from the read control unit 2 via the terminal 6c corresponding to a portion to be displayed on the screen.

The data read from the frame memory 6 is supplied to address drivers 3 and 4 via terminals 6a and 6b. The address drivers 3 and 5 write information to be displayed on the plasma display panel 4. Further, the read control unit 2 supplies a driving pulse required for light emission to the plasma display panel 4 to emit light.

Next, an example of the write control unit 1 will be described with reference to FIG. Here, blocks and terminals having the same functions as those in FIG. 1 are denoted by the same reference numerals. In FIG. 3, reference numeral 11 denotes a data number conversion unit which holds data of 6 dots (2 dots for each of R, G, and B) input from the input terminal 11a and re-divides the data into data of 8 dots. Output.

Reference numeral 12 denotes a line memory, which has a capacity to store two lines of data from the output terminal 11c of the data number converter 11, and controls an address driver IC (not shown) by controlling a read address. ) Is rearranged into data corresponding to each of the specifications of the input signal. Reference numeral 13 denotes a bit expansion unit,
, Each bit data is selected from the data from the output terminal 13a, and is collectively output to the frame memory 6 from the output terminal 13c through the terminal 1e.

Reference numeral 15 denotes a timing control unit. The timing control unit 15 controls the timing of the write control unit 1 and outputs a write control signal to the frame memory 6. That is, a write control signal is supplied to the terminal 11b of the data number conversion unit 11, the line memory 12, the terminal 13b of the bit expansion unit 13, and the frame memory 6 based on a clock signal or the like from the input unit 1b.

Next, the arrangement of data supplied to the address driver 3 will be described with reference to FIG. Here, FIG.
Blocks and terminals having the same functions as those described above are denoted by the same reference numerals. Further, in this example, the case where the address drivers 3 and 5 are arranged on both sides of the plasma display panel 4 will be described, but they may be arranged collectively on one side.

In FIG. 2, reference numerals 31, 32, 33, 34 and 51, 52, 53, 54 denote data lines for supplying data from the frame memory 6 to the address drivers 3, 5, respectively. In addition, 311 and 312, 313 to 3
Reference numeral 15 denotes an address driver IC.

The address driver IC performs serial-parallel conversion of data input from the data line, and writes emission information to the plasma display panel 4 according to the data. Here, for example, a case will be described in which the number of bits of the input data line of one address driver IC is 4, and the number of bits of the data line to the plasma display panel 4 is 64.

The address driver ICs 311 and 312 are connected in cascade, and the address driver ICs 311 and 312 apparently have the same function as the address driver IC with 4-bit input and 128-bit output. This is to reduce the number of bits of the data lines input from the frame memory 6 to the address drivers 3 and 5.

The address drivers 3 and 5 are arranged on both sides of the plasma display panel 4, and address lines are alternately drawn from above and below the plasma display panel 4 in a comb-like manner (not shown). Since the data input to the address driver IC can handle the upper and lower four address driver ICs as one block, the data supplied to one block is 8 bits, and the output may be 256 bits of data.

That is, the relationship between the display data array on the screen and the data input to each address driver IC is 256 bits between adjacent blocks. Thus, the display pixels for one line can be set by inputting 8-bit (up and down) data 32 times for each block.
Hereinafter, the block other than the functional block indicates the above-mentioned block division. 1 to n added to the address driver IC in FIG. 2 indicate block numbers.

FIG. 4 shows display data and an address driver IC.
This shows the array relationship of the data to be input to.

FIG. 4A shows an array of display data at the upper left of the screen. As described above, data input simultaneously to one block is 8 bits.

Here, assuming that the address line starts on the address driver 3 side on the display screen, the first data supplied to the address driver IC 311 is:
There are four bits of R1, B1, G2, and R3. Similarly, the data to be supplied to the address driver IC 311 for the second time is repeated for B3, G4, R5, and B5, and becomes data for 128 dots by fetching the data 32 times ((b) in FIG. 4).

In this way, as shown in FIG. 4C, the upper and lower four address driver ICs are
Data for 6 dots can be set. By repeating this operation the number of times corresponding to the number of vertical lines, it is possible to set display pixels (for one bit) for one screen.

Next, a method of generating data to be supplied to the address driver will be described with reference to FIG. Here, the video data input to the data number conversion unit 11 is R, G,
B will be described as a two-phase input, but it goes without saying that a single-phase input can be handled in the same way once it is converted to a two-phase input.

In FIG. 5, reference numerals 111 and 112 denote shift registers, which hold input data at the rise of a clock signal. Here, the shift register 111
R1, G1, B1 and the like added to FIGS.
This corresponds to the display pixel in FIG. FIG. 5A shows the state at the second clock from the video data input. Similarly, FIGS. 5B and 5C show shift registers 111 and 1 at the third and fourth clocks, respectively.
12 is shown. In FIG. 5, the data at the timing of not being filled is sequentially used as valid data.

For example, in the second clock shown in FIG. 5A, R1, G1, B1, R2, G2, B2, R3, G
3. Select the 8-dot data. In the third clock shown in FIG. 5B, B3, R4, G4, B4, R
5, 8-dot data of G5, B5, and R6 are selected. In the third clock shown in FIG. 5C, G6, B6, R
7, 8-dot data of G7, B7, R8, G8, B8 is selected.

In this way, by sequentially selecting the outputs of the shift registers 111 and 112, 6-dot data is input four times and 8-dot data is output three times. This cycle is shown in FIG. 5D, and the clock signal is shown in FIG. With this operation, 6-dot data can be converted into 8-dot data. Therefore, if the bit of each gradation is selected for the data in units of 8 dots, the data is input to the address driver.

However, the data number conversion section 11 is not necessary when the input of the address driver IC (not shown) is 3 bits or an integral multiple of 3, and the writing to the line memory 12 may be performed continuously.

FIG. 6 is a diagram for explaining the operation of the line memory 12. FIG. 6A shows a horizontal direction 1024 × 3 (R, G,
B) In the case of using the address driver on both sides of the plasma display panel 4 on the dot display screen, and in the case of using the address driver on one side of the plasma display panel 4 in FIG. 2 shows a use area map of the line memory 12 of FIG.

In FIG. 6A, as described above, since 8 dot data becomes data for one block 32 times,
Considering 32 words as one block, 32 words × 12 blocks are used. In FIG. 6B, since the address driver is arranged only on one side of the plasma display panel 4, the address driver is 128 dots in one block unit. Therefore, since the 8-dot data becomes data for one block 16 times, 16 words are regarded as one block, and the data for one line is composed of 16 words × 24 blocks.

Here, the configuration of the line memory 12 will be described as a dual port memory capable of storing 1024 words with 80 bits per word, but the number of bits per word is at least eight times the number of bits of video data to be displayed. I just need. For example, in the case of an 8-bit display, it is sufficient to use 64 bits.

In this example, the number of words is described assuming that the pixels in the horizontal direction are 1024.times.3 dots. The memory of 512 words is assumed to have two banks (one bank for writing and one bank for reading). Each uses only 384 words.

The number of pixels in the horizontal direction is 1366 (× 3
(R, G, B)) 2048 when the number of dots exceeds
A word configuration may be used. The line memory 12 does not necessarily have to be a dual-port memory. If two banks of single-port memories each having half the word configuration of the dual-port memory are used and the write bank and the read bank are switched by a selector, the dual-port memory can be used. A function similar to that used is obtained.

Writing to the line memory 12 is performed, for example, sequentially from the lower address. In FIG. 6, the write address is set to 512 or later, and the read address is set to 0 or later. However, these write and read addresses are not accessed simultaneously and are used alternately.
That is, control is performed so that, after writing is completed, reading is performed next on each surface.

FIG. 7 shows an example of the operation at the time of reading data from the line memory 12. In this example, the read addresses are 0, 3,
Control is performed such that the data is sequentially read from 2, 64,. Similarly, the skip interval of the read address in the case of the one-side drawing shown in FIG. 6B may be set to 16 at a time. With the above control, the data read from the line memory 12 becomes data corresponding to each block.

If data of the same bit is selected from this data, data to be input to the address driver can be obtained. In this example, the write address of the line memory 12 is sequentially performed, and the data is rearranged by controlling the read address intermittently. However, the write address is controlled intermittently and the read address is continuously controlled. The same effect can be obtained even if the steps are sequentially performed.

FIG. 8 shows an example of the bit expanding section 13. Here, blocks having the same functions as those in FIG. 3 are denoted by the same reference numerals. The bit expansion unit 13 includes a first-stage shift register 131 and a second-stage shift register 132.

Next, the operation will be described. Data read from the line memory 12 is input from the terminal 13a.
A clock signal is input from the terminal 13b at the timing when the data is held.

The above data is sequentially input corresponding to each block, and the preceding stage shift register 131 is constituted by the same number of shift registers as the blocks. Immediately after the data is held in all the shift registers of the first-stage shift register 131, all data is loaded into the second-stage shift register 132. Thus, the data corresponding to each block is held in each of the subsequent-stage shift registers 132.

For example, as described above, the horizontal direction is 1024 dots (× 3 (R, G, B)), and a 64-bit driver (4-bit input, 64-bit output,
In the case of two cascade connections, both sides are drawn out, the number of blocks is 12 (= 3072/256), so that n is 12 in the second-stage shift register 132.

FIG. 9 is an explanatory diagram of the twelfth shift register 1321. FIG. 9A is an enlarged view of a state in which the first data is loaded into the shift register 1321 located at the last stage in the second-stage shift register 132 shown in FIG. FIG. 9B shows that R1 in the subsequent-stage shift register 132
Only data is enlarged. FIG. 9A shows a state in which the data of each dot is stored in order. Here, for example, attention is paid to the leading R1 data. 1
If the number of bits per dot is 10 bits, as shown in FIG. 9B, the R1 data is stored in a 10-stage shift register, and when a shift clock signal (not shown) is input, the R1 data is stored. Are output in order from the lowest data, for example.

Similarly, data is output one bit at a time from G1, G2, R2,..., And a total of eight bits of data are output. Since 8-bit data is output from each of the 12 shift registers in the subsequent-stage shift register 132 in FIG. 8, 96 (= 8 bits × 12) bits of data are output simultaneously for one clock. By this processing, data of the same gradation for each block can be selected.

FIG. 10 is a block diagram showing another example of the write control unit 1. Here, components having the same functions as the blocks and terminals shown in FIG. 3 are denoted by the same reference numerals.

In FIG. 10, reference numeral 14 denotes a burst memory. This burst memory 14 has a bit developing unit 13
Is supplied and stored from the terminal 13c. Also,
A timing control signal is supplied from the timing control unit 15 to the burst memory 14. Then, the data stored in the burst memory 14 is supplied to the frame memory 6.

As the frame memory 6, a block transfer type (if an address is given to the memory once, the address is automatically added to several words thereafter, and data can be written in a burst. By this operation, the writing and reading speeds can be increased. ), It is necessary to collect, for example, 16 words of data. Therefore, it is necessary to store the gradation data for the number of bursts in the burst memory 14 and send the data to the frame memory 6 collectively.

This operation will be described with reference to FIG. FIG.
Reference numeral 1 denotes an address map of the burst memory 14. Here, the burst memory 14 has two banks with the address 256 as a boundary, and writing and reading are alternately performed in each bank.

The data input to the burst memory 14 is rearranged into each bit (gradation) data by the bit developing unit 13 and is input in the gradation order. Therefore, in the burst memory 14, addresses may be written at 16 intervals. . Also,
When writing to the frame memory 6, it is necessary to write the same grayscale data at a time, so each grayscale data is 16 words.

FIG. 12 shows a write address of the burst memory 14. Thus, the write addresses are 0, 1,
6, 32, 48,..., 144 are controlled so as to be at intervals of 16, and after adding the number of gradations, 1, 17, 33,
.. 145 are repeatedly written, and each gradation data is written for 16 words. Reading is performed sequentially from the lower address, and if reading is performed, 0, 1, 2, 3,.
Data can be read out by 16 words for each gradation.

In this example, the data is rearranged by intermittently controlling the write address to the burst memory 14 and performing the read address sequentially and continuously. However, the write address is sequentially and continuously controlled. The same effect can be obtained even if the read address is intermittently controlled.

Although the number of bursts has been described as 16 here, it may be changed according to the specification of the memory to be used. The data conversion unit 11 is not necessary when the input of the address driver IC (not shown) is 3 bits or an integral multiple of 3, and the writing to the line memory 12 may be performed continuously.

By the above operation, the data input to each block can be rearranged for each bit, there is no redundant data, and the data read from the frame memory 6 is supplied to the address driver without changing the order. The writing speed and the reading speed from the write control unit 1 to the frame memory 4 can be suppressed to the minimum necessary.

Therefore, it is possible to realize a plasma display device capable of coping with an enlargement of the display screen and an increase in the number of display gradations with an inexpensive configuration without having to increase the reading speed from the memory for storing the video information. And a drive device that controls writing and reading to and from the memory.

In the above example, the frame memory 4 has been described as having a configuration outside the write control unit 1, but the write control unit 1 may include the frame memory 4.

Similarly, the read control unit 2 has been described with the configuration outside the write control unit 1, but the write control unit 1 may include the read control unit 2.

The relationship between the number of words in which the data number converter 11 rearranges the R, G, and B data of the video input signal and the number of input bits to the address drivers 3 and 5 is as follows. Is 4 × N (N is a natural number), the number of words to be rearranged is 4
X M (M is a natural number) may be used.

[0072]

Since the present invention is configured as described above, it has the following effects. It is possible to realize a plasma display device capable of coping with the enlargement of the display screen and the increase in the number of display gradations with an inexpensive configuration without increasing the reading speed from the memory for storing the video information, and a write control device for the memory. A driving device that controls writing and reading to and from a memory can be realized.

Further, the number of wires for data transfer between the memory for storing video information and the write control unit can be reduced, which is effective in reducing the board area and power consumption.

[Brief description of the drawings]

FIG. 1 is an overall schematic block diagram of an embodiment of a plasma display device according to the present invention.

FIG. 2 is a schematic configuration diagram of an address driver in FIG. 1;

FIG. 3 is a schematic configuration diagram of a write control unit in FIG. 1;

FIG. 4 is an explanatory diagram of an operation of the address driver in FIG. 2;

FIG. 5 is an explanatory diagram of an operation of a data number conversion unit in FIG. 3;

FIG. 6 is an explanatory diagram of an operation of the line memory in FIG. 3;

FIG. 7 is an explanatory diagram of an operation of the line memory in FIG. 3;

FIG. 8 is an explanatory diagram of an operation of a bit expanding unit in FIG. 3;

FIG. 9 is an explanatory diagram of the operation of the subsequent-stage shift register in FIG. 8;

FIG. 10 is a schematic configuration diagram of another example of the write control unit in FIG. 1;

11 is an explanatory diagram of the operation of the burst memory in FIG.

12 is an explanatory diagram of the operation of the burst memory in FIG.

FIG. 13 is a schematic configuration diagram of a conventional plasma display device.

FIG. 14 is a schematic configuration diagram of an I / O buffer unit of a conventional plasma display device.

FIG. 15 is an explanatory diagram of a driving method of a video signal in the plasma display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Write control part 2 Read control part 3, 5 Address driver 4 Plasma display panel 6 Frame memory 7 Video signal input terminal 8 Input terminal of clock signal etc. 11 Data number conversion part 12 Line memory 13 Bit development part 14 Burst memory 15 Timing control Units 31 to 34, 51 to 54 Data lines 111, 112 Shift register 131 Front-stage shift register 132 Rear-stage shift register 311 to 315 Address driver IC

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ken Kumakura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Home Appliances and Information Media Business Unit

Claims (11)

[Claims] 1. A plasma display apparatus for displaying a multi-gradation video signal on a plasma display panel by forming one frame with a plurality of subfields having different relative luminance ratios and different light emission sustain periods, wherein the subfield data is A frame memory for storing, a video signal input, a write control unit for controlling writing of subfield data of the video signal to the frame memory, and a subfield data stored in the frame memory to a plasma display panel. An address driver to be written, wherein the write control unit rearranges the subfield data according to the specification of the input signal of the address driver and the arrangement position of the address driver on the plasma display panel. Data A plasma display device, wherein the data is stored in the frame memory, and the data stored in the frame memory is read from the frame memory without changing its order and supplied to the address driver. . 2. The plasma display device according to claim 1, wherein said write control unit includes a line memory capable of storing at least two lines of video data in a horizontal direction. 3. The plasma display device according to claim 1, wherein said writing control unit includes a bit developing unit for selecting video data for each gradation, wherein said bit developing unit has at least a predetermined number of bits. A first-stage shift register having a predetermined number of stages of a block consisting of: and a second-stage shift register for loading output data of each stage of the first-stage shift register. The second-stage shift register shifts data of the first-stage shift register at a cycle of the number of blocks. A plasma display device, wherein the data is loaded into a register, and the subsequent shift register is controlled to output the same gradation data from the loaded data. 4. The plasma display device according to claim 1, wherein the writing control unit is configured to reduce the number of words that can be transferred to the frame memory at one time when one unit consisting of a predetermined number of bits is one word. A plasma display device comprising a burst memory for collectively storing data to be written to a frame memory for each gray level by the number of words that can be transferred at one time. 5. The plasma display device according to claim 1, wherein the write control section sets the number of input bits of the address driver to 4 × N (N is a natural number), Assuming that one unit is one word, a data number conversion unit for rearranging the R, G, B data of the video input signal input to the writing control unit into 4 × M (M is a natural number) word units is provided. A plasma display device characterized by the above-mentioned. 6. A sub-field data of a plasma display device for displaying a multi-gradation video signal on a plasma display panel by forming one frame by a plurality of sub-fields having different luminance relative ratios and light emission sustain periods. A writing control device that controls writing of the subfield data to a frame memory to be written, wherein the subfield data of the video signal input to the writing control device is arranged in accordance with an input specification of data to be written to the plasma display panel. Alternatively, the writing control device writes and stores the data in the frame memory. 7. The writing control device according to claim 6, further comprising a line memory capable of storing at least two lines of video data in a horizontal direction. 8. A writing control device according to claim 6, further comprising a bit developing section for selecting video data for each gradation, wherein said bit developing section includes at least a predetermined number of blocks having a predetermined number of bits. A first-stage shift register having a number of stages, and a second-stage shift register for loading output data of each stage of the first-stage shift register. The data of the first-stage shift register is loaded into the second-stage shift register at a cycle of the number of blocks. A write control device wherein the shift register controls the same grayscale data to be output from the loaded data. 9. The writing control device according to claim 6, wherein one unit consisting of a predetermined number of bits is one word, and the unit of the frame memory is determined according to the number of words that can be transferred to the frame memory at one time. A write control device, comprising: a burst memory that collectively stores data to be written for each gradation for the words that can be transferred at one time. 10. The writing control device according to claim 6, wherein the number of bits input to the frame memory is 4 × N (N is a natural number), and one unit consisting of a predetermined number of bits is 1 unit. In the case where the word is a word, there is provided a data number conversion unit for rearranging the R, G, and B data of the video input signal input to the writing control device into a unit of 4 × M (M is a natural number) words. Control device. 11. A frame is constituted by a plurality of subfields having different luminance relative ratios and light emission sustain periods,
In a driving apparatus of a plasma display device for displaying a multi-gradation video signal on a plasma display panel, subfield data of a video signal is rearranged according to an input specification of data to be written on the plasma display panel and written on the frame memory. Write control means for storing, and address signal forming means for forming an address signal corresponding to a display pixel of the plasma display panel based on the subfield data stored in the frame memory. Drive.