JPH1117308A - Electronic component packaging structure - Google Patents

Electronic component packaging structure

Info

Publication number
JPH1117308A
JPH1117308A JP17258197A JP17258197A JPH1117308A JP H1117308 A JPH1117308 A JP H1117308A JP 17258197 A JP17258197 A JP 17258197A JP 17258197 A JP17258197 A JP 17258197A JP H1117308 A JPH1117308 A JP H1117308A
Authority
JP
Japan
Prior art keywords
electronic component
sintered body
ceramic sintered
wiring patterns
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17258197A
Other languages
Japanese (ja)
Inventor
Takashi Ono
孝 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP17258197A priority Critical patent/JPH1117308A/en
Publication of JPH1117308A publication Critical patent/JPH1117308A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent crackings around a terminal electrode of an electronic component surface-packaged on a circuit board, and to prevent the breakage of the electronic component and degradation of electric characteristics, even if thermal history such as heating and cooling or an extraneous force is applied to the electronic component, while being used. SOLUTION: In a packaging structure, an electronic component 1 is constructed by packaging terminal electrodes 5 provided on the both ends of a ceramic sintered body 4 on a pair of wiring patterns 3 on an external circuit board 2, by using solders 6. If the line width of the wiring patterns 3 in a solder- packaging portion is Wh, the width of the ceramic sintered body 4 is Ws, the interval between the pair of wiring patterns 3 is Dh, and the interval between the terminal electrodes 5 is De, the relations 1.0<=Wh/Ws<=1.2 and 0.8<=Dh/De<=1.0 is satisfied.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、その両端部に端子
電極が形成された積層セラミックコンデンサ等の電子部
品を、外部の回路基板の配線パターン上に半田付けにて
表面実装する電子部品の実装構造であって、熱衝撃等の
熱的ストレスに対する強度及び耐久性を向上させたもの
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the mounting of an electronic component such as a multilayer ceramic capacitor having terminal electrodes formed at both ends thereof on the surface of a wiring pattern of an external circuit board by soldering. The present invention relates to a structure having improved strength and durability against thermal stress such as thermal shock.

【0002】[0002]

【従来の技術】従来の積層セラミックコンデンサ等の電
子部品11の実装構造の断面図を図7に示す。同図に示
すように、電子部品11の端子電極12,12を、外部
の電気回路基板や電子回路基板(以下、回路基板とい
う)13の配線パターン14,14上に半田15により
導電接続して構成していた。尚、同図において、16は
誘電体のセラミック焼結体であり、例えば複数の板状の
セラミックスの間に内部電極17を層状に埋設して積層
体を形成し、該積層体の両端の内部電極17の露出面に
銀等を主成分とする端子電極12,12を形成して構成
される。
2. Description of the Related Art FIG. 7 is a sectional view of a conventional mounting structure of an electronic component 11 such as a multilayer ceramic capacitor. As shown in FIG. 1, terminal electrodes 12, 12 of an electronic component 11 are conductively connected by solder 15 to wiring patterns 14, 14 of an external electric circuit board or an electronic circuit board (hereinafter, referred to as a circuit board) 13. Was composed. In FIG. 1, reference numeral 16 denotes a dielectric ceramic sintered body. For example, a laminated body is formed by embedding internal electrodes 17 in layers between a plurality of plate-shaped ceramics, and the inside of both ends of the laminated body is formed. Terminal electrodes 12 and 12 mainly composed of silver or the like are formed on the exposed surface of the electrode 17.

【0003】前記従来の実装構造では、回路基板13、
セラミック焼結体16、端子電極12,12及び半田1
5が有する熱膨張係数がそれぞれ異なるため、表面実装
時の半田付け等による加熱・冷却時の熱衝撃による互い
の熱膨張差及び熱収縮差でもって、セラミック焼結体1
6に引張応力が発生し、セラミック焼結体16の端子電
極12,12付近に亀裂が発生していた。前記亀裂は当
初は微小な場合もあり、その場合は回路基板13への表
面実装時に電気的特性は問題とならないが、使用中に周
囲の温度変化が繰り返し加わり、微小な亀裂が徐々に成
長して電気的特性が劣化していた。
[0003] In the conventional mounting structure, the circuit board 13,
Ceramic sintered body 16, terminal electrodes 12, 12, and solder 1
5 have different thermal expansion coefficients, the ceramic sintered body 1 has a difference in thermal expansion and thermal contraction due to thermal shock during heating and cooling by soldering or the like during surface mounting.
6, tensile stress was generated, and cracks were generated near the terminal electrodes 12, 12 of the ceramic sintered body 16. The cracks may be minute at first, in which case the electrical characteristics do not matter at the time of surface mounting on the circuit board 13, but the ambient temperature changes repeatedly apply during use, and the minute cracks gradually grow. The electrical characteristics were degraded.

【0004】そこで、前記問題を解決するために、セラ
ミック製の電子部品の本体を構成するセラミック焼結体
部分の全長に対して、端子電極の長さを一定の範囲以下
に設定することが提案されている(従来例1:特開平4
−294512号公報参照)。また、素子本体の両端に
外部電極を有するチップ型セラミック電子部品素子であ
って、前記外部電極の部分において、チップ型セラミッ
ク電子部品素子の対向する2面をばね性をもって挟むよ
うに、金属クリップを備えたものが提案されている(従
来例2:特開平7−22269号公報参照)。
Therefore, in order to solve the above-mentioned problem, it is proposed to set the length of the terminal electrode to a certain range or less with respect to the entire length of the ceramic sintered body constituting the main body of the ceramic electronic component. (Conventional Example 1: Japanese Patent Laid-Open No.
-294512). Further, a chip-type ceramic electronic component element having external electrodes at both ends of an element body, wherein a metal clip is provided so as to sandwich two opposing surfaces of the chip-type ceramic electronic component element with a spring property in the external electrode portion. A device provided with the same has been proposed (conventional example 2: see Japanese Patent Application Laid-Open No. 7-22269).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来例1では、回路基板に電子部品を半田付けで強固に表
面実装できるものの、長期にわたる使用中の熱履歴によ
り、セラミック焼結体の側面下部に発生する応力が、電
子部品の端子電極部近傍に亀裂を発生させる恐れがあ
り、外力が加わると電子部品が破壊されたり、電気的特
性が劣化するという問題点があった。
However, in the above-mentioned conventional example 1, although the electronic components can be firmly surface-mounted on the circuit board by soldering, due to the heat history during use for a long period of time, the electronic parts are formed on the lower side surface of the ceramic sintered body. The generated stress may cause a crack in the vicinity of the terminal electrode portion of the electronic component, and when an external force is applied, the electronic component is broken or the electrical characteristics are deteriorated.

【0006】また、従来例2は、回路基板の伸縮が金属
クリップに吸収され電子部品素子に発生する応力を低減
できるものの、電子部品素子の外部電極と金属クリップ
を接合する導電性接着剤が、長期にわたる使用中の熱履
歴により剥離してしまい、電気的特性が劣化するという
問題点があった。
Further, in the conventional example 2, although the expansion and contraction of the circuit board is absorbed by the metal clip and the stress generated in the electronic component element can be reduced, the conductive adhesive for joining the external electrode of the electronic component element and the metal clip is used. There has been a problem that the film is peeled off due to heat history during use for a long period of time, and electrical characteristics are deteriorated.

【0007】本発明は前記事情に鑑みて完成されたもの
であり、その目的は回路基板に電子部品を半田付けで強
固に表面実装できるとともに、表面実装した電子部品の
セラミック焼結体の端子電極部近傍に亀裂を生じること
なく、使用中に電子部品に加熱・冷却等の熱履歴や外力
が加わっても、電子部品が破壊されたり電気的特性が劣
化しない、耐久性に優れた実装構造を提供することにあ
る。
SUMMARY OF THE INVENTION The present invention has been completed in view of the above circumstances, and an object of the present invention is to enable an electronic component to be firmly surface-mounted on a circuit board by soldering, and to provide a terminal electrode of a ceramic sintered body of the electronic component surface-mounted. Even if a heat history such as heating and cooling or external force is applied to the electronic component during use without cracking near the part, the electronic component will not be damaged or the electrical characteristics will not be deteriorated. To provide.

【0008】[0008]

【課題を解決するための手段】本発明の電子部品の実装
構造は、複数のセラミック板と複数の内部電極とを交互
に積層して成るセラミック焼結体の両端部に設けられた
端子電極を、外部の回路基板の一対の配線パターン上に
半田付けにより実装して成る電子部品の実装構造であっ
て、前記半田実装部における前記配線パターンの線幅を
Wh 、前記セラミック焼結体の幅をWs 、前記一対の配
線パターンの間隔をDh 、端子電極間距離をDe とした
時、1.0≦Wh /Ws ≦1.2かつ0.8≦Dh /D
e <1.0の関係を満足することを特徴とし、配線パタ
ーンの線幅と電子部品の本体部分を構成するセラミック
焼結体の幅との関係、及び、一対の配線パターンの間隔
と端子電極間距離との関係を前記特定範囲に設定するこ
とにより、セラミック焼結体への応力集中を低減でき、
亀裂の発生や使用時の過酷な熱的条件下での亀裂の成長
を抑制、防止するものである。
According to the present invention, there is provided a mounting structure of an electronic component comprising terminal electrodes provided at both ends of a ceramic sintered body formed by alternately laminating a plurality of ceramic plates and a plurality of internal electrodes. An electronic component mounting structure mounted on a pair of wiring patterns of an external circuit board by soldering, wherein the line width of the wiring pattern in the solder mounting portion is Wh, and the width of the ceramic sintered body is Ws, when the distance between the pair of wiring patterns is Dh and the distance between the terminal electrodes is De, 1.0 ≦ Wh / Ws ≦ 1.2 and 0.8 ≦ Dh / D
e <1.0, wherein the relationship between the line width of the wiring pattern and the width of the ceramic sintered body constituting the main body of the electronic component, and the distance between the pair of wiring patterns and the terminal electrode By setting the relationship with the distance to the specific range, stress concentration on the ceramic sintered body can be reduced,
The purpose of the present invention is to suppress or prevent crack generation and crack growth under severe thermal conditions during use.

【0009】[0009]

【発明の実施の形態】本発明の電子部品の実装構造を図
面に基づき以下に詳述する。図1は本発明の電子部品の
斜視図であり、積層セラミックコンデンサ等の電子部品
を回路基板に表面実装した実装構造である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A mounting structure of an electronic component according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a perspective view of an electronic component of the present invention, which has a mounting structure in which an electronic component such as a multilayer ceramic capacitor is surface-mounted on a circuit board.

【0010】同図において、1は複数のセラミック板4
bと複数の内部電極4aとを交互に積層して成るセラミ
ック焼結体4を本体とするセラミックコンデンサ,積層
セラミックコンデンサ,チップ抵抗素子等の電子部品、
2は電子部品1を表面実装するための外部の回路基板、
3,3はCu,Ag,Au等からなり、回路基板2上に
形成されて電子部品1を導電接続する一対の配線パター
ン、4はチタン酸バリウム(BaTiO3 ),チタン酸
鉛(PbTiO3 ),チタン酸ジルコン酸鉛(PbZr
TiO3 )等を主成分とする誘電体セラミックから成る
セラミック焼結体、4aはセラミック焼結体4内部に層
状に積層されたAg,Pd,Ag−Pd合金,Ni,C
u等から成る内部電極、5,5はセラミック焼結体4の
両端に設けられAg,Cu,Ni,Ag−Pd等から成
る端子電極、6は端子電極5,5を配線パターン3,3
に導電接続するための半田、Wh は配線パターン3,3
の線幅、Ws はセラミック焼結体4の幅、De は端子電
極5,5間距離、Dh は一対の配線パターン3,3間の
間隔である。
In FIG. 1, reference numeral 1 denotes a plurality of ceramic plates 4.
b and a plurality of internal electrodes 4a alternately laminated, and electronic components such as a ceramic capacitor having a ceramic sintered body 4 as a main body, a multilayer ceramic capacitor, a chip resistor element, and the like.
2 is an external circuit board for surface mounting the electronic component 1,
Reference numerals 3 and 3 denote a pair of wiring patterns formed of Cu, Ag, Au or the like and formed on the circuit board 2 to electrically connect the electronic components 1 to each other. Reference numeral 4 denotes barium titanate (BaTiO 3 ) and lead titanate (PbTiO 3 ). , Lead zirconate titanate (PbZr
A ceramic sintered body 4 made of a dielectric ceramic mainly composed of TiO 3 ) or the like, 4a is a layered Ag, Pd, Ag-Pd alloy, Ni, C
u, etc., 5 and 5 are terminal electrodes provided on both ends of the ceramic sintered body 4 and made of Ag, Cu, Ni, Ag-Pd, etc., and 6 is a terminal pattern
For conductive connection to the wiring, Wh is the wiring pattern 3,3
, Ws is the width of the ceramic sintered body 4, De is the distance between the terminal electrodes 5 and 5, and Dh is the distance between the pair of wiring patterns 3 and 3.

【0011】このように、電子部品1はセラミック焼結
体4の両端に端子電極5,5を有しており、その端子電
極5,5が半田6により配線パターン3,3上に導電接
続され、回路基板2に表面実装される。
As described above, the electronic component 1 has the terminal electrodes 5 and 5 at both ends of the ceramic sintered body 4, and the terminal electrodes 5 and 5 are conductively connected to the wiring patterns 3 and 3 by the solder 6. , Is surface-mounted on the circuit board 2.

【0012】本発明において、1.0≦Wh /Ws ≦
1.2かつ0.8≦Dh /De <1.0とするものであ
り、Wh /Ws <1.0の場合、表面実装時にセラミッ
ク焼結体4が配線パターン3,3に対して捩じれて接続
され易く、その際に電子部品1が配線パターン3,3か
ら剥離する等の実装不良が発生するおそれがあり、耐久
性に問題がある。逆に、Wh /Ws >1.2の場合、セ
ラミック焼結体4に顕著な応力集中が生じて端子電極
5,5付近に亀裂が発生し易くなる。また、Dh /De
<0.8の場合、配線パターン3,3同士がショートし
易くなり、逆にDh/De ≧1.0の場合には、セラミ
ック焼結体4に顕著な応力集中が生じて端子電極5,5
付近に亀裂が発生し易くなる。
In the present invention, 1.0 ≦ Wh / Ws ≦
1.2 and 0.8 ≦ Dh / De <1.0. When Wh / Ws <1.0, the ceramic sintered body 4 is twisted with respect to the wiring patterns 3 and 3 during surface mounting. It is easy to be connected, and at this time, there is a possibility that a mounting failure such as peeling of the electronic component 1 from the wiring patterns 3 and 3 may occur, and there is a problem in durability. Conversely, when Wh / Ws> 1.2, remarkable stress concentration occurs in the ceramic sintered body 4 and cracks are likely to be generated near the terminal electrodes 5 and 5. Also, Dh / De
If <0.8, the wiring patterns 3 and 3 are likely to be short-circuited. Conversely, if Dh / De ≧ 1.0, significant stress concentration occurs in the ceramic sintered body 4 and 5
Cracks are likely to occur in the vicinity.

【0013】更に望ましくは、1.05≦Wh /Ws ≦
1.15かつ0.8≦Dh /De ≦0.95とするのが
良い。
More preferably, 1.05 ≦ Wh / Ws ≦
It is preferable that 1.15 and 0.8 ≦ Dh / De ≦ 0.95.

【0014】また、本発明では、半田実装部において、
配線パターン3,3表面と端子電極5,5との間に半田
が入り込んでおり、その半田の最小厚みtを90μm以
上とすることが好ましく、その場合セラミック焼結体4
への応力集中を更に低減できる。より好ましくは95μ
m以上とする。尚、tの上限は格別限定するものではな
いが、半田量の低減及び実装時の位置ずれを防止する上
で500μm以下が望ましい。
Further, according to the present invention, in the solder mounting portion,
Solder enters between the surface of the wiring patterns 3 and 3 and the terminal electrodes 5 and 5, and the minimum thickness t of the solder is preferably 90 μm or more.
Stress concentration on the substrate can be further reduced. More preferably 95μ
m or more. The upper limit of t is not particularly limited, but is preferably 500 μm or less in order to reduce the amount of solder and prevent displacement during mounting.

【0015】前記端子電極5,5は、Agから成る下地
層にNi層,Sn層等を積層させた積層構造とするのが
望ましく、その場合半田6との濡れ性が良好となり、ま
た端子電極5,5のセラミック焼結体4への密着性を高
めることができる。
The terminal electrodes 5 and 5 preferably have a laminated structure in which a Ni layer, a Sn layer and the like are laminated on an underlayer made of Ag. In this case, the wettability with the solder 6 is improved, and Adhesion to the ceramic sintered bodies 4 of 5, 5 can be enhanced.

【0016】また、半田6としては、Sn−Pb系共晶
半田等の半田が、導電性が良好である事や実装工程の容
易さ等の点で好適である。本発明において、半田6に関
しては、所定の温度への加熱により溶融し降温時に固化
する導電性の材料であれば、半田6以外の材料であって
も半田6と同等に使用可能である。
As the solder 6, a solder such as a Sn-Pb eutectic solder is suitable in terms of good conductivity, easy mounting process, and the like. In the present invention, any material other than the solder 6 can be used as the solder 6 as long as it is a conductive material that melts when heated to a predetermined temperature and solidifies when the temperature is lowered.

【0017】本発明の電子部品1の本体部分を構成する
セラミック焼結体4は、端子電極5,5が設けられる端
面の角部及び稜線を曲面で形成することが、角部での応
力集中を低減できることにより亀裂の発生を抑制する点
で望ましく、これは公知のバレル研磨法などにより容易
に加工することができる。
In the ceramic sintered body 4 constituting the main body of the electronic component 1 of the present invention, the corners and ridges of the end faces on which the terminal electrodes 5 and 5 are provided are formed by curved surfaces, so that the stress concentration at the corners is increased. This is desirable in that the generation of cracks can be suppressed by reducing the amount of cracks, which can be easily processed by a known barrel polishing method or the like.

【0018】更に、本発明における電子部品1の実装構
造は、セラミック焼結体4の両側端面に端子電極5,5
が形成されたものに対して適用できるものであり、上記
の積層セラミックコンデンサだけでなく、例えばセラミ
ック焼結体を構成部材とする積層コイルやLC複合フィ
ルタ等にも適用可能である。
Further, the mounting structure of the electronic component 1 according to the present invention is such that the terminal electrodes 5, 5
Can be applied to not only the above-described multilayer ceramic capacitor but also, for example, a multilayer coil or an LC composite filter having a ceramic sintered body as a constituent member.

【0019】かくして、本発明は、表面実装時の加熱・
冷却時の熱衝撃等の熱的ストレスによる、回路基板2、
電子部品1及び半田6間の互いの熱膨張差及び熱収縮差
でもって、セラミック焼結体4に生じる応力集中を低減
することができる。その結果、セラミック焼結体4に亀
裂が発生せず、しかも使用中に大きな加熱・冷却等の熱
履歴が加わるような過酷な条件下、あるいは電子部品1
に外力が加わっても、亀裂の進展や電気的特性の劣化が
なく、従って電子部品1の実装の歩留り及び長期的な信
頼性が向上する。
Thus, the present invention provides a method for heating and
The circuit board 2, due to thermal stress such as thermal shock during cooling,
Due to the difference in thermal expansion and contraction between the electronic component 1 and the solder 6, stress concentration occurring in the ceramic sintered body 4 can be reduced. As a result, cracks do not occur in the ceramic sintered body 4 and severe conditions in which a large heat history such as heating and cooling is applied during use, or the electronic component 1
Even if an external force is applied, the crack does not develop or the electrical characteristics do not deteriorate, so that the mounting yield and long-term reliability of the electronic component 1 are improved.

【0020】尚、本発明は上記の実施形態に限定される
ものではなく、本発明の要旨を逸脱しない範囲内で種々
の変更は何等差し支えない。
It should be noted that the present invention is not limited to the above embodiment, and various changes may be made without departing from the scope of the present invention.

【0021】[0021]

【実施例】以下、本発明の電子部品の実装構造の実施例
を示す。また、本実施例に付随して、コンピュータシミ
ュレーションにより本発明の作用効果を確認した。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the electronic component mounting structure of the present invention will be described below. Further, the operation and effect of the present invention were confirmed by computer simulation accompanying the present embodiment.

【0022】(実施例)図1の電子部品1の実装構造を
以下のように構成した。BaTiO3 を主成分とする複
数のセラミック板4bと、Agから成る複数の内部電極
4aとを交互に積層し焼結して、(長さ=2.0mm)
×(幅Ws =1.0mm)×(厚さ=1.0mm)の直
方体状のセラミック焼結体4を作製した。これを積層セ
ラミックコンデンサの本体とした。その後、その両端面
に順次Ag,Ni,Snを焼き付け端子電極5,5を形
成し、積層セラミックコンデンサを作製した。このと
き、端子電極5,5間の距離De は1.0mmである。
(Embodiment) The mounting structure of the electronic component 1 of FIG. 1 was constructed as follows. A plurality of ceramic plates 4b mainly composed of BaTiO 3 and a plurality of internal electrodes 4a made of Ag are alternately laminated and sintered (length = 2.0 mm).
× (width Ws = 1.0 mm) × (thickness = 1.0 mm) rectangular ceramic sintered body 4 was produced. This was used as the main body of the multilayer ceramic capacitor. Thereafter, Ag, Ni, and Sn were sequentially baked on both end surfaces to form terminal electrodes 5 and 5, thereby producing a multilayer ceramic capacitor. At this time, the distance De between the terminal electrodes 5 and 5 is 1.0 mm.

【0023】電子部品1としての前記積層セラミックコ
ンデンサを、回路基板2としてのアルミナ基板上に形成
され、Cuから成る一対の配線パターン3,3に、Sn
63wt%−Pd37wt%から成る共晶半田を用い
て、端子電極5,5を230℃で導電接続して表面実装
した。
The multilayer ceramic capacitor as the electronic component 1 is formed on a pair of wiring patterns 3 and 3 formed on an alumina substrate as a circuit board 2 and made of Sn.
Terminal electrodes 5 and 5 were conductively connected at 230 ° C. and surface-mounted using eutectic solder composed of 63 wt% -Pd 37 wt%.

【0024】このとき、Wh /Ws ,Dh /De ,tを
種々の値に設定し、その信頼性についてテストした結果
を表1に示す。具体的には、各試料のものを50個ずつ
作製し、これらを−40℃と130℃のガルデン液中に
各5分間交互に浸漬することを1サイクルとする熱衝撃
試験を、各構造体について2000サイクルまで実施し
た。そして、500サイクル後、1000サイクル後及
び2000サイクル後に、立体顕微鏡を用いた目視検査
と浸透探傷法により、セラミック焼結体4に亀裂の発生
した積層セラミックコンデンサの個数を調査した。尚、
表1の亀裂発生個数の欄の数字500,1000,20
00はサイクル数を示し、備考欄のコンデンサは積層セ
ラミックコンデンサを意味する。
At this time, Wh / Ws, Dh / De, and t were set to various values, and the results of tests for their reliability are shown in Table 1. Specifically, each structure was subjected to a thermal shock test in which 50 samples of each sample were prepared, and each of the samples was alternately immersed in Galden's solution at -40 ° C and 130 ° C for 5 minutes for one cycle. For up to 2000 cycles. Then, after 500 cycles, 1000 cycles, and 2000 cycles, the number of cracked multilayer ceramic capacitors in the ceramic sintered body 4 was examined by visual inspection using a stereoscopic microscope and penetrant inspection. still,
Numbers 500, 1000, and 20 in the column of the number of cracks in Table 1
00 indicates the number of cycles, and the capacitor in the remarks column means a multilayer ceramic capacitor.

【0025】[0025]

【表1】 [Table 1]

【0026】表1の結果から明らかなように、Wh /W
s <1.0の試料NO.1,2では、熱衝撃試験では大
きな問題はないものの、積層セラミックコンデンサが配
線パターン3,3から剥離してしまった。これは、積層
セラミックコンデンサが捩じれて実装されたためと考え
られる。
As is clear from the results in Table 1, Wh / W
s <1.0 sample NO. In Examples 1 and 2, although there was no major problem in the thermal shock test, the multilayer ceramic capacitor was peeled off from the wiring patterns 3 and 3. This is probably because the multilayer ceramic capacitor was mounted by being twisted.

【0027】Wh /Ws >1.2の試料NO.7では、
500サイクル後においてすでに亀裂の発生が認められ
た。
Sample No. Wh / Ws> 1.2 In 7,
Cracking was already observed after 500 cycles.

【0028】Dh /De <0.8の試料NO.10,1
5では、2000サイクル後に配線パターン間のショー
トが発生した。
Sample No. Dh / De <0.8 10,1
In No. 5, a short circuit occurred between the wiring patterns after 2,000 cycles.

【0029】Dh /De ≧1.0の試料NO.14,1
9では、2000サイクル後に10個以上の不良品が発
生し、信頼性に欠けるものであった。
Sample No. Dh / De ≧ 1.0 14,1
In No. 9, 10 or more defective products were generated after 2000 cycles, and the reliability was poor.

【0030】また、tが90μm未満の試料NO.24
では、2000サイクル後で10個の不良品が発生し
た。
The sample No. having t less than 90 μm. 24
Then, after 2000 cycles, 10 defective products occurred.

【0031】ここで、熱衝撃試験2000サイクル後に
おいて、亀裂が発生したセラミック焼結体の累積個数が
初期個数(本実施例では50個)の10%以内のもの
を、信頼性が良好であるという判定基準を採り入れる
と、上記の試料NO.1,2,7,9,10,14,1
5,19,24,25の実装構造のいずれも実用的では
ない。
Here, after 2,000 cycles of the thermal shock test, a ceramic sintered body in which the cumulative number of cracked ceramic sintered bodies is within 10% of the initial number (50 in this embodiment) has good reliability. When the determination criterion is adopted, the above sample NO. 1,2,7,9,10,14,1
None of the mounting structures 5, 19, 24 and 25 are practical.

【0032】これに対して、試料NO.3〜6,8,1
1〜13,16〜18,20〜23では、いずれも電気
的なショートは起きず、また熱衝撃試験2000サイク
ル後に亀裂が発生したセラミック焼結体の個数は、初期
個数の10%以内であり、十分な信頼性があることが判
った。
On the other hand, the sample No. 3-6,8,1
In Nos. 1 to 13, 16 to 18, and 20 to 23, no electrical short-circuit occurred, and the number of ceramic sintered bodies that had cracks after 2000 cycles of the thermal shock test was within 10% of the initial number. , Proved to be sufficiently reliable.

【0033】一方、本発明者は、本実施例の作用効果を
確認するために、有限要素法による応力解析をコンピュ
ータシミュレーションにより行った。
On the other hand, the present inventor performed a computer simulation for stress analysis by the finite element method in order to confirm the operation and effect of this embodiment.

【0034】図2に応力解析に用いた1/4カットモデ
ルの一例を示し、図中の符号は図1の符号に該当する。
本解析では、解析を詳細に行うために、実施例で使用し
た積層セラミックコンデンサの実装構造の形状を再現し
た3次元モデルを下記の4種類作成し、セラミック焼結
体4、端子電極5,5、半田6、配線パターン3,3、
アルミナ基板の物性値を、各々の要素にてパラメータと
して入力した。特に、半田6の部分は塑性を考慮し、弾
塑性熱応力解析を行った。
FIG. 2 shows an example of the 1/4 cut model used for the stress analysis, and the reference numerals in the figure correspond to those in FIG.
In this analysis, in order to carry out the analysis in detail, the following four types of three-dimensional models were created that reproduced the shape of the mounting structure of the multilayer ceramic capacitor used in the example, and the ceramic sintered body 4, the terminal electrodes 5, 5 , Solder 6, wiring patterns 3, 3,
The physical property values of the alumina substrate were input as parameters for each element. In particular, elasto-plastic thermal stress analysis was performed for the solder 6 in consideration of plasticity.

【0035】解析結果の代表例として、セラミック焼結
体4を図2のA方向(右側斜め下方向)から見たときの
応力分布を図3〜図6に示す。図3はWh /Ws =1.
0かつDh /De =0.9でt=98μm、図4はWh
/Ws =1.3かつDh /De =0.9でt=98μ
m、図5はWh /Ws =1.0かつDh /De =0.8
でt=104μm、図6はWh /Ws =1.0かつDh
/De =1.2でt=79μmの場合のそれぞれの1/
4カットモデルである。尚、図3〜図6で符号21はW
s の1/2の幅を図示している。
As representative examples of the analysis results, FIGS. 3 to 6 show stress distributions when the ceramic sintered body 4 is viewed from the direction A (obliquely downward rightward) in FIG. FIG. 3 shows Wh / Ws = 1.
0 and Dh / De = 0.9, t = 98 μm, FIG.
/Ws=1.3 and Dh / De = 0.9 and t = 98μ
m, FIG. 5 shows that Wh / Ws = 1.0 and Dh / De = 0.8
T = 104 μm, and FIG. 6 shows that Wh / Ws = 1.0 and Dh
/De=1.2 and t = 79 μm.
This is a 4-cut model. 3 to FIG.
The width of 1/2 of s is illustrated.

【0036】解析の結果、セラミック焼結体4の側面下
部に発生する最大引張応力22は、図3のものが5.5
kgf/mm2 であるのに対し、図4の場合は9.0k
gf/mm2 となり、約1.6倍にも達することが判明
した。従って、Wh がWs に対して大きくなるほど、セ
ラミック焼結体4に発生する応力は大きくなり、亀裂が
発生する可能性が高くなることが判った。
As a result of the analysis, the maximum tensile stress 22 generated at the lower part of the side surface of the ceramic sintered body 4 is 5.5 in FIG.
kgf / mm 2 , whereas in the case of FIG.
gf / mm 2 , which was found to be about 1.6 times. Therefore, it was found that as Wh becomes larger than Ws, the stress generated in the ceramic sintered body 4 becomes larger, and the possibility of cracking increases.

【0037】また、図5のものは最大引張応力22が
5.4kgf/mm2 であるのに対し、図6の場合は
8.4kgf/mm2 となり、約1.56倍であった。
Further, the maximum tensile stress 22 is that of Figure 5 whereas a 5.4kgf / mm 2, was 2, and about 1.56 times 8.4kgf / mm in the case of FIG.

【0038】[0038]

【発明の効果】本発明は、配線パターンの線幅をWh 、
セラミック焼結体の幅をWs 、配線パターンの間隔をD
h 、端子電極間距離をDe とすると、1.0≦Wh /W
s ≦1.2かつ0.8≦Dh /De <1.0の関係を満
足し、半田実装部における配線パターン表面から端子電
極までの半田の最小厚みtを90μm以上とすることに
より、温度変化が繰り返し加わるような過酷な条件下で
もセラミック焼結体に亀裂が発生せず、電子部品として
の電気的特性の劣化もなく、その結果電子部品の表面実
装後の歩留りが高く、かつ長期的な信頼性に優れるとい
う作用効果を有する。
According to the present invention, the line width of the wiring pattern is set to Wh,
The width of the ceramic sintered body is Ws, and the distance between the wiring patterns is D.
h, and when the distance between the terminal electrodes is De, 1.0 ≦ Wh / W
By satisfying the relationship of s ≦ 1.2 and 0.8 ≦ Dh / De <1.0, and setting the minimum thickness t of the solder from the surface of the wiring pattern to the terminal electrode in the solder mounting portion to 90 μm or more, the temperature change Cracks do not occur in the ceramic sintered body even under severe conditions where it is repeatedly applied, and there is no deterioration of the electrical characteristics as an electronic component.As a result, the yield after surface mounting of the electronic component is high, and long-term It has the effect of being excellent in reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の電子部品としての積層セラミックコン
デンサを回路基板に表面実装した実装構造を示す斜視図
である。
FIG. 1 is a perspective view showing a mounting structure in which a multilayer ceramic capacitor as an electronic component of the present invention is surface-mounted on a circuit board.

【図2】有限要素法による応力解析に用いた1/4カッ
トモデルの一例を示す斜視図。
FIG. 2 is a perspective view showing an example of a カ ッ ト cut model used for stress analysis by the finite element method.

【図3】Wh /Ws =1.0かつDh /De =0.9で
t=98μmのセラミック焼結体を図2のA方向から見
たときの1/4カットモデルの応力分布図である。
3 is a stress distribution diagram of a 1/4 cut model when a ceramic sintered body of Wh / Ws = 1.0 and Dh / De = 0.9 and t = 98 μm is viewed from a direction A in FIG. 2; .

【図4】Wh /Ws =1.3かつDh /De =0.9で
t=98μmのセラミック焼結体の応力分布図である。
FIG. 4 is a stress distribution diagram of a ceramic sintered body with Wh / Ws = 1.3 and Dh / De = 0.9 and t = 98 μm.

【図5】Wh /Ws =1.0かつDh /De =0.8で
t=104μmのセラミック焼結体の応力分布図であ
る。
FIG. 5 is a stress distribution diagram of a ceramic sintered body where Wh / Ws = 1.0, Dh / De = 0.8, and t = 104 μm.

【図6】Wh /Ws =1.0かつDh /De =1.2で
t=79μmのセラミック焼結体の応力分布図である。
FIG. 6 is a stress distribution diagram of a ceramic sintered body where Wh / Ws = 1.0, Dh / De = 1.2, and t = 79 μm.

【図7】従来の電子部品の実装構造の断面図である。FIG. 7 is a sectional view of a conventional electronic component mounting structure.

【符号の説明】[Explanation of symbols]

1:電子部品 2:回路基板 3:配線パターン 4:セラミック焼結体 5:端子電極 6:半田 22:最大引張応力 1: electronic component 2: circuit board 3: wiring pattern 4: ceramic sintered body 5: terminal electrode 6: solder 22: maximum tensile stress

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数のセラミック板と複数の内部電極とを
交互に積層して成るセラミック焼結体の両端部に設けら
れた端子電極を、外部の回路基板の一対の配線パターン
上に半田付けにより実装して成る電子部品の実装構造で
あって、前記半田実装部における前記配線パターンの線
幅をWh 、前記セラミック焼結体の幅をWs 、前記一対
の配線パターンの間隔をDh 、端子電極間距離をDe と
した時、1.0≦Wh/Ws ≦1.2かつ0.8≦Dh
/De <1.0の関係を満足することを特徴とする電子
部品の実装構造。
1. A terminal electrode provided at both ends of a ceramic sintered body formed by alternately laminating a plurality of ceramic plates and a plurality of internal electrodes on a pair of wiring patterns of an external circuit board. Wherein the line width of the wiring pattern in the solder mounting portion is Wh, the width of the ceramic sintered body is Ws, the interval between the pair of wiring patterns is Dh, and the terminal electrode is Assuming that the distance is De, 1.0 ≦ Wh / Ws ≦ 1.2 and 0.8 ≦ Dh
An electronic component mounting structure characterized by satisfying a relationship of /De<1.0.
JP17258197A 1997-06-27 1997-06-27 Electronic component packaging structure Pending JPH1117308A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17258197A JPH1117308A (en) 1997-06-27 1997-06-27 Electronic component packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17258197A JPH1117308A (en) 1997-06-27 1997-06-27 Electronic component packaging structure

Publications (1)

Publication Number Publication Date
JPH1117308A true JPH1117308A (en) 1999-01-22

Family

ID=15944507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17258197A Pending JPH1117308A (en) 1997-06-27 1997-06-27 Electronic component packaging structure

Country Status (1)

Country Link
JP (1) JPH1117308A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7186926B2 (en) 2004-02-12 2007-03-06 Kabushiki Kaisha Toyota Jidoshokki Surface mounting structure for surface mounting an electronic component
JP2007227857A (en) * 2006-02-27 2007-09-06 Toshiba Corp Printed board incorporating component, printed board, electronic apparatus, and electronic component
US20140003014A1 (en) * 2012-06-28 2014-01-02 Taiyo Yuden Co., Ltd. Mounting structure of electric chip device
US20150223334A1 (en) * 2014-01-31 2015-08-06 Murata Manufacturing Co., Ltd. Structure mounted with electronic component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7186926B2 (en) 2004-02-12 2007-03-06 Kabushiki Kaisha Toyota Jidoshokki Surface mounting structure for surface mounting an electronic component
JP2007227857A (en) * 2006-02-27 2007-09-06 Toshiba Corp Printed board incorporating component, printed board, electronic apparatus, and electronic component
US20140003014A1 (en) * 2012-06-28 2014-01-02 Taiyo Yuden Co., Ltd. Mounting structure of electric chip device
US8958213B2 (en) * 2012-06-28 2015-02-17 Taiyo Yuden Co., Ltd. Mounting structure of chip component
US20150223334A1 (en) * 2014-01-31 2015-08-06 Murata Manufacturing Co., Ltd. Structure mounted with electronic component
US10342130B2 (en) * 2014-01-31 2019-07-02 Murata Manufacturing Co., Ltd. Structure mounted with electronic component

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