JPH11168363A - Delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale in the case of delaying only the rise or fall of signals as one element of a logic circuit and to prevent an abnormal operation. SOLUTION: This delay circuit for inputting required logic input signals and obtaining target delay signals for which the signals are delayed is constituted of an inverter circuit 2 for outputting inverted signals Sr for which the input signals Sin are inverted and the (n) pieces (n) is an integer >=1} of small-sized delay circuits 31-3n. The small-sized delay circuits 31-3n are provided with three input terminals and one output terminal, the input signals Sin are inputted to a first input terminal, the input signals or the output of the small- sized delay circuit of a preceding stage are inputted to a second input terminal, the inverted signals Sr of the inversion circuit 2 are inputted to a third input terminal and the target delay signals are obtained from the output terminal Sout. By turning the output of the small-sized delay circuit 3n of a final stage to the delay signals, output signals for which only the rise is delayed are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly, to a delay circuit formed of a semiconductor integrated circuit and having a small circuit scale.

[0002]

2. Description of the Related Art Conventionally, as a delay circuit composed of a semiconductor integrated circuit, for example, there is one as shown in FIG. 7A shown in Japanese Patent Application Laid-Open No. 7-249970. FIG. 7 (a)
Is composed of a delay circuit 22 for delaying a signal at an input terminal 21 for a fixed time, an inverter 23 for inverting the signal and delaying the signal for a fixed time, and a NAND circuit 24 connected to the delay circuit 22 and an output of the inverter 23. , Output terminal 2
5 outputs a delay signal. Therefore, the output timing and pulse width of this signal, that is, the timing of outputting a pulse starting from the rising edge of the input signal and the pulse width of the output pulse are determined by the delay time in the delay circuit 22 and the delay time in the inverter 23. It will be determined based on the difference. Such a delay circuit is characterized in that the rising and falling timings of a signal can be set arbitrarily by a combination of two types of delay circuits. As a delay circuit similar to this, as shown in FIG. 7B, the NAND circuit 2 shown in FIG.
4 is changed to an AND circuit 26. However, the delay circuit shown in FIG. 7 can generate a target signal for a spontaneous signal, but cannot generate a target signal when a delay value and a signal repetition cycle are close to each other. I do.

[0003] As a specific example, logically 1
Is a time T1, a time logically 0 is T0, a rising delay value is Td1, and a falling delay value is Td0.
When Td0−Td1> T0, a target signal cannot be generated due to interference from the previous cycle of the signal. The reason for this will be described with reference to FIG. 8 which is an operation timing chart of the circuit in FIG. 8, (S21) is an input signal, (S22) is an output signal of the delay circuit 22, (S2
3) is an output signal of the inverter 23, and (S24) is an AND signal.
The output signal of the circuit 26, (S25) is a target signal originally intended to be output. First, inverter 2 in the first cycle
The output 3 (S23) is output with a delay value delayed by Td0. Therefore, (S23) becomes 0 with a delay of Td0,
Further, the input signal becomes 1 after a delay of time T1 when the input signal is logically 1. That is, it becomes possible to prepare for outputting the delay signal of the next cycle for the first time after the delay of Td0 + T1. The output of the delay signal in the next cycle is T from the beginning of the next cycle.
Since the value is delayed by d1, Td0 + T1 becomes T1 + T0
It must be smaller than + Td1. That is, Td0 + T1 <T1 + T0 + Td1. From this equation, if d0-Td1 <T0, the preparation of the signal of the inverter 23 cannot be made in time for the rise of the delay signal of the next cycle, and as a result, the rise of the signal is delayed or the target delay signal is obtained. The Tx portion of (S25) is not output.

In order to solve this problem, a method of not increasing the delay value of the inverter 23 for generating Td0 is as follows.
As shown in FIG. 9, there is a method of using a delay circuit 27 instead of the inverter 23. However, there is still a problem in this case. This time, the delay value of the delay circuit 27 is the delay time of the fall of the delay signal with respect to the fall of the input signal, and an arbitrary delay time cannot be set. In this case, if the delay time of the delay circuit 27 is Tdx0, a problem occurs when Td1−Tdx0> T0. The reason will be described with reference to the timing chart of FIG.

In FIG. 10, (S21) is an input signal,
(S22) is an output signal of the delay circuit 22, (S27) is an output signal of the delay circuit 27, (S26) is an output signal of the AND circuit 26, and (S25) is a target signal that is originally desired to be output. First, the output of the delay circuit 22 in the first cycle (S
22) is output with the delay value delayed by Td1. For this reason,
(S22) becomes 1 with a delay of Td1, and further becomes 0 with a delay of time T1 when the input signal is logically 1. That is, the signal 1 of the previous cycle is output for the time T1 from Td0. Therefore, during this time, the delay circuit 2
When the signal of 7 becomes 1, an unnecessary pulse is generated there. That is, Td1 + T1 is T1 + T0 + Td
It must be smaller than x0. From this, Td1 + T1 <T1 + T0 + Tdx0. From this equation, if Td1−Tdx0 <T0, as shown in Ty of (S26), an unnecessary pulse with a delay of Tdx0 is generated at the beginning of the next cycle.

A delay circuit shown in FIG. 11 has been proposed as a delay circuit for preventing a target pulse from being output or an unnecessary pulse from being generated. This delay circuit does not delay the fall of the signal. That is, this is an example equivalent to the circuit in which the delay circuit 27 of the conventional example shown in FIG. 9 has no delay. The delay circuit shown in FIG. 11 includes n arbitrary 2-input AND circuits 71 to 7 each having a fixed delay time.
n, and an input signal Sin is input to one input of each of the n two-input AND circuits 71 to 7n.
The input signal Sin is also input to the other input of the first two-input AND circuit 12, and the output of the first two-input AND circuit 12 is connected to one input of the second two-input AND circuit 72. . The output of the second two-input AND circuit 72 is connected to the other input of the third two-input AND circuit 73. The second two-input AND circuit 72 and the third two-input
The combination of the input AND circuit 73 is repeated, and the output of the n-th two-input AND circuit 7n is the output delay signal Sout.

The operation of the delay circuit shown in FIG. 11 will be described with reference to a timing chart shown in FIG. In FIG. 12, the waveform shown as (Sin) is an input signal, and the output of the first two-input AND circuit 71 is ( S7
The signal has the waveform shown in 1). A second gate input of a second two-input AND circuit 72 that connects an input signal Sin to a first gate input is connected to the first two-input AND circuit.
By connecting the output of the circuit 71, the rising waveform of the output signal of the second two-input AND circuit 72 becomes (S7
As shown in 2), compared to the input signal Sin, the first 2
The output is delayed by the sum of the delay time of the input AND circuit 71 and the delay time of the second two-input AND circuit 72. The output of the falling waveform of the second two-input AND circuit 72 is smaller than the falling of the input signal Sin by the input of the input signal Sin.
The output is delayed by the delay time of the input AND circuit 72 and is not affected by the delay time of the first two-input AND circuit 71. Similarly, the rise of the output signal of the third two-input AND circuit 73 is, as shown in (S73), the first to third two-input AND circuits 71 and the two-input A
The output is delayed by the sum of the delay times of the ND circuit 72 and the two-input AND circuit 73. The falling of the output signal of the third two-input AND circuit 73 corresponds to the input signal S
It falls later than in by the delay time of the third two-input AND circuit 73. This is the n-th two-input AND
The process is repeated up to the circuit 7n, and as shown in (S7n), the rise is delayed by the sum of the delay times of the n 2-input AND circuits, and the fall is the delay of the n-th two-input AND circuit 7n. A signal delayed by the time can be generated.

[0008]

In such a conventional delay circuit shown in FIGS. 7A and 7B or FIG. 9,
As described above, there is a problem that a target signal cannot be generated when a signal repetition cycle is close to a delay value. At the same time, there is a problem that the circuit scale becomes large because the delay circuit and the output signal generation unit are separated. That is, when a signal having an arbitrary delay time is generated, a resistance value corresponding to the delay time is required, and a circuit for generating the delay time and a circuit for generating the output signal are separated. Each circuit is required. Also, in the case of the delay circuit of FIG. 11 equivalent to the circuit in which the delay circuit 27 in the delay circuit of FIG. 9 has no delay, the two-input AND circuit is used in addition to the delay circuit. The number of MOS transistors increases and the circuit scale increases. In particular, as shown in FIG. 11, when a large number of two-input AND circuits are required, the number of MOS transistors becomes extremely large, and the circuit scale is significantly increased.

An object of the present invention is to provide a delay circuit with a reduced circuit scale.

[0010]

A delay circuit according to the present invention comprises: an inverting circuit for outputting an inverted signal obtained by inverting an input signal;
(N is an integer of 1 or more) small delay circuits,
The small delay circuit has three input terminals and one output terminal. The first input terminal receives the input signal, and the second input terminal receives the input signal or the previous small delay. An output of the circuit is input, an output of the inverting circuit is input to a third input terminal, and the target delay signal is obtained from an output terminal. The small delay circuit includes a first PMOS transistor having a source connected to a power supply and a gate connected to the first input terminal, a source grounded, a gate connected to the second input terminal, and a drain connected to the second input terminal. A first NMOS transistor connected to the drain of the first PMOS transistor; a source connected to the power source; a second PMOS transistor connected to the drain of the first PMOS transistor; a source grounded; Is connected to the third input terminal,
A second NMOS transistor having a drain connected to the drain of the second PMOS transistor, the second PMOS transistor and a second NMOS transistor;
The connection point of each drain of the transistor is connected to the output terminal.

Further, the delay circuit of the present invention comprises a non-inverting circuit for outputting a non-inverted signal obtained by non-inverting an input signal, and n (n is an integer of 1 or more) small delay circuits. The small delay circuit has two input terminals and one output terminal. The first input terminal receives the input signal, and the second input terminal receives the output of the non-inverting circuit. And obtaining the target delay signal from an output terminal. The small delay circuit includes a PMOS transistor having a source connected to a power supply and a gate connected to the first input terminal, a source connected to ground, a gate connected to the second input terminal, and a drain connected to the PMOS transistor. A NMOS transistor connected to a drain, and an inverting circuit having an input terminal connected to a connection point of each drain of the PMOS transistor and the NMOS transistor, wherein an output terminal of the inverting circuit is connected to the output terminal. Is done.

According to the present invention, an output signal whose only rising edge is delayed can be obtained by using the output of the last small delay circuit among the n cascade-connected small delay circuits as a delay signal. In addition, a delay circuit can be configured without using a two-input AND circuit, the number of elements configuring the circuit is reduced, and a delay circuit with a small circuit scale can be obtained.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of the first exemplary embodiment of the present invention. Referring to FIG. 1, there are provided an inverting circuit 2 having an input signal Sin input to an input terminal 1 as a gate input, and an arbitrary number n (n is an integer of 1 or more) of small delay circuits 31 to 3n. doing. The input signal is connected to all of the small delay circuits 31 to 3n, and the output signal of the inverting circuit 2 is connected to all of the small delay circuits 31 to 3n as inverted signals. The input signal is also connected to the first small delay circuit 31, and the output signals of the first to (n-1) th small delay circuits 31 to 3n-1 are respectively connected to the next-stage small delay circuits as input signals. And the n-th small delay circuit 3n output from the output terminal 4
Is the desired output signal Sout.

FIG. 2 is a block diagram showing a configuration example of the first to n-th small delay circuits 31 to 3n. Since the first to n-th small delay circuits 31 to 3n have the same configuration, the first small delay circuit 31 will be described below as an example. In FIG. 2, the first small delay circuit 31 is a PMO
S-transistors PMOS1, PMOS2 and NMOS
It comprises transistors NMOS1 and NMOS2.
The source of the PMOS transistor PMOS1 having the input signal Sin as a gate input is connected to a power supply VCC, and the output from the preceding small delay circuit, here the input signal S1
NMOS transistor NMOS with in as gate input
1 has its source grounded and its drain connected to the drain of the PMOS transistor PMOS1. The PM
The source of the PMOS transistor PMOS2 having the drain input of the OS transistor PMOS1 as the gate input is the power supply V.
An NMOS transistor NMO connected to the inverter CC and having an inverted signal Sr output from the inverting circuit 2 as a gate input.
The source of S2 is grounded and the NMOS transistor NMO
The drain of S2 is the PMOS transistor PMOS2
And outputs as an output signal Sout1 as an input signal of the next-stage small delay circuit.

Next, the operation of the circuit of FIG. 1 will be described with reference to the timing chart of FIG. In FIG. 3, a waveform indicated by (Sin) is an input signal, which is a signal connected to the inverting circuit 2 and the first small delay circuit 31. FIG. 3 (Sr) shows the output of the inverting circuit 2,
The output signal of the inverting circuit 2 is output after being inverted with a certain delay time with respect to the input signal Sin. The input signal Sin is input from the first small delay circuit 31 to the n-th small delay circuit 3n,
It is connected to the gate input of the MOS transistor PMOS1. When the input signal Sin is at a low level, P
The MOS transistor PMOS1 is turned on, and the HI level becomes the gate input of the PMOS transistor PMOS2,
The PMOS transistor PMOS2 turns off. Also,
On the other hand, when the input signal Sin is at the HI level, the NMOS
The transistor NMOS1 turns on, and the LOW level becomes PM
It becomes the gate input of the OS transistor PMOS2 and PM
The OS transistor PMOS2 turns on, and the HI level is propagated as the output signal Sout1.

When the inverted signal Sr shown in FIG. 2 is at the HI level, the NMOS transistor NMOS2 is turned on,
The LOW level is propagated as the output signal Sout1.
That is, when the input signal Sin is at the HI level and the inverted signal Sr is at the LOW level, the output signal Sout1 is at the HI level.
Level. When the input signal Sin is at the LOW level and the inverted signal Sr is at the HI level, the output signal So
ut1 becomes a LOW level.

Therefore, as shown in (S31), the first
The output signal Sout1 of the small delay circuit 31 of FIG.
The output is delayed by the fixed delay time of the MOS1 and the fixed delay time of the PMOS transistor PMOS2. At this time, the falling is caused by the output S of the inverting circuit 2.
NM in the first small delay circuit 31 having r as a gate input
Due to the action of the OS transistor NMOS2, the inverting circuit 2
Constant delay time and NMOS transistor NMOS
2 falls with a delay of a fixed delay time. Therefore, by using the output of the first small delay circuit 31 as the input signal of the second small delay circuit 32, the NM in the second small delay circuit 32 having a fixed delay time
Due to the action of the OS transistor NMOS1 and the PMOS transistor PMOS2, the output of the second small delay circuit 32 is fixed by the NMOS transistor NMOS1 and the PMOS transistor PMOS2 in the first small delay circuit 31 as shown in FIG. The delay time of the second small delay circuit 32 generates a signal having a waveform that is added to a fixed delay time of the NMOS transistor NMOS1 and the PMOS transistor PMOS2. This is propagated to the n-th small delay circuit 3n, and generates a signal having a waveform delayed by the rising edge as shown in FIG. 3 (S3n), that is, an output signal Sout.

Accordingly, in this delay circuit, when the small delay circuit has one minimum circuit configuration, a total of six MOS transistors forming the small delay circuit and two MOS transistors forming the inversion circuit are provided. It is possible to employ a configuration in which the number of MOS transistors is increased, and the number of MOS transistors is increased by one for each additional small delay circuit. Incidentally, even in the case of the minimum configuration of FIG. 11 in which the number of MOS transistors is the smallest in the conventional configuration and the delay circuit 37 is omitted from the delay circuit of FIG. The AND circuit 42 requires four MOS transistors, each having a total of eight MOS transistors, and it can be seen that the delay circuit of this embodiment can be configured with fewer MOS transistors.

In the case of this embodiment, a non-inverting circuit (buffer) is connected to the gate of the PMOS transistor PMOS1 shown in FIG. 2, and the input signal Sin is slightly delayed and input to the gate of the PMOS transistor PMOS1. It may be configured as follows. However, in this case, since one or two MOS transistors are required to form a non-inverting circuit, the effect of reducing the number of MOS transistors is reduced. Therefore, the two-input AND circuit 42 used in the conventional circuit is composed of five or more MOS transistors, and compared with the small delay circuit composed of four MOS transistors of the present embodiment, the mutual delay circuits are different. This is effective when there is a difference in the number of MOS transistors in the comparison.

FIG. 4 is a block diagram showing the configuration of the second embodiment of the present invention. In this embodiment, the output of the non-inverting circuit 17 to which the input signal Sin is input is connected as a non-inverted signal to the first to n-th small delay circuits 61 to 6n. Connected as an input signal to a small delay circuit of the
Is output as the output signal Sout.
FIG. 5 is a block diagram showing a configuration example of the first to n-th small delay circuits 61 to 6n shown in FIG. Since the first to n-th small delay circuits 61 to 6n have the same configuration,
Hereinafter, the first small delay circuit 61 will be described as an example.
In FIG. 5, a first small delay circuit 61 includes a PMOS transistor PMOS3 and an NMOS transistor NMO.
S3 and an inverting circuit INV. Non-inverted signal S
PMOS transistor PMOS3 having n as a gate input
Is connected to a power supply VCC, the source of an NMOS transistor NMOS3 having a gate input of an output signal of a previous stage, here, an input signal Sin, is grounded, and the drain is connected to the drain of the PMOS transistor PMOS3. The output waveform of the inverting circuit INV having the gate input of the drain of the PMOS transistor PMOS3 is an output signal, here, the output signal Sout of the next-stage small delay circuit.
It is output as 1.

Next, the operation of the circuit of FIG. 4 will be described with reference to the timing chart of FIG. In FIG. 6, the waveform indicated by (Sin) is an input signal, which is a signal connected to the non-inverting circuit 5 and the first small delay circuit 61. (Sn) is the output of the non-inverting circuit 5. The output signal Sn of the non-inverting circuit 5 is output with a certain delay time with respect to the input signal Sin, is input from the first small delay circuit 61 to the n-th small delay circuit 6n as a non-inverted signal, and is connected to a PMOS transistor. It is connected to the gate input of PMOS3. Therefore, when the input signal changes from the LOW level to the HI level, as shown in (S5),
After a predetermined time, the non-inverted signal Sn from the non-inverted circuit 5 becomes H
I level, and the PMOS transistor PMOS3
FF is performed, the NMOS transistor NMOS3 is turned on, and a LOW level is propagated as an input signal of the inverting circuit 5 after a certain period of time possessed by the NMOS transistor NMOS3. The signal is then propagated as an output signal Sout1. Therefore, when the non-inverted signal Sn is at the LOW level, the input signal Sin is also at the LOW level, the NMOS transistor NMOS3 is turned off, the PMOS transistor PMOS3 is turned on, the HI level becomes the gate input of the inverting circuit INV, and the LOW level Is the output signal Sout1
Is propagated as When the input signal Sin is at the HI level, the non-inverted signal Sn also becomes the HI level after a certain period of time of the non-inverting circuit, and the PMOS transistor PMOS
3 is OFF, NMOS transistor NMOS3 is ON
Then, the LOW level becomes the gate input of the inverting circuit INV, and the HI level is propagated as the output signal Sout1.

Therefore, as shown in (Sout1), when the input signal rises, the output signal of the first small delay circuit 61 has a certain delay time of the NMOS transistor NMOS3 and a certain delay time of the inversion circuit INV. Is output after being delayed by. Also, the input signal Sin
Falls, the PMOS transistor PMOS3
, The constant delay time of the non-inverting circuit 5 and P
The MOS transistor PMOS3 falls and is delayed by a fixed delay time of the MOS transistor PMOS3 and a fixed delay time of the inversion circuit INV. Therefore, by using the output signal of the first small delay circuit 61 as the input signal of the second small delay circuit 62, the NMOS transistor NMOS3 and the inversion circuit in the second small delay circuit 62 having a fixed delay time are provided. Due to the action of INV, the output of the second small delay circuit 62 is, as shown in (S62), at a fixed delay time of the NMOS transistor NMOS3 and the inversion circuit INV in the first small delay circuit 62 described above. A signal having a waveform added to a predetermined delay time of the NMOS transistor NMOS3 and the inverting circuit INV in the second small delay circuit 62 is generated. This is propagated to the n-th small delay circuit 6n to generate a signal having a waveform delayed by the rising edge as shown in (Sout).

In the delay circuit of the second embodiment, when the small delay circuit has one minimum circuit configuration, two MOS transistors forming the small delay circuit and two MOS transistors forming the inversion circuit And a total of five or six MOS transistors, one or two MOS transistors constituting a non-inverting circuit, and four additional MOS transistors each time a small delay circuit is added. A configuration in which the number of MOS transistors is increased can be employed. Therefore, as described above, it can be understood that the delay circuit of the present embodiment can be configured with a smaller number of MOS transistors than the configuration of the total of eight MOS transistors in the case of the minimum configuration in FIG.

[0024]

As described above, the present invention has three input terminals and one output terminal as a configuration of n cascaded small delay circuits, and the first input terminal has The input signal is input, and the input signal or the output of the preceding small delay circuit is input to a second input terminal.
The input terminal has an input terminal to which the output of the inverting circuit is input and a delay signal is obtained from the output terminal. Alternatively, a small delay circuit has two input terminals and one output terminal. The input signal is input to a first input terminal, the output of the non-inverting circuit is input to a second input terminal, and a delay signal is obtained from an output terminal. Since the signal generation function is included in the circuit, there is no need to provide a delay circuit and a pulse generation circuit separately, thereby reducing the number of MOS transistors, simplifying the circuit, and configuring an integrated circuit. In this case, the arrangement and wiring are facilitated, and there is an advantage that it is advantageous in terms of high integration. Further, in the delay circuit of the present invention, only the rising edge or only the falling edge is delayed, so that an abnormal pulse is generated when the level of the input signal opposite to the level to be delayed is shorter than the delay time. There is also an effect that it can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a small delay circuit shown in FIG.

FIG. 3 is a timing chart showing the operation of the first exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of a small delay circuit illustrated in FIG. 4;

FIG. 6 is a timing chart showing an operation of the second exemplary embodiment of the present invention.

FIG. 7 is a block diagram illustrating an example of a conventional delay circuit and another example.

FIG. 8 is a timing chart showing an operation example of the circuit of FIG. 7;

FIG. 9 is a block diagram showing still another example of the conventional delay circuit.

FIG. 10 is a timing chart showing an operation example of the circuit of FIG. 9;

FIG. 11 is a block diagram showing an improved example of a conventional delay circuit.

FIG. 12 is a timing chart illustrating an operation example of the circuit in FIG. 11;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Inverting circuit 31-3n Small delay circuit 4 Output terminal 5 Non-inverting circuit 61-6n Small delay circuit 71-7n 2-input AND circuit PMOS1-3 PMOS transistor NMOS1-3 NMOS transistor INV Inverting circuit

Claims (6)

[Claims] 1. A delay circuit for receiving a desired logic input signal and obtaining a target delay signal obtained by delaying the signal, comprising: an inverting circuit for outputting an inverted signal obtained by inverting the input signal; n is an integer of 1 or more), and the small delay circuit has three input terminals and one output terminal, and the first input terminal receives the input signal. The second input terminal receives the input signal or the output of the preceding small delay circuit, the third input terminal receives the output of the inverting circuit, and obtains the desired delay signal from the output terminal. A delay circuit, characterized in that: 2. The small delay circuit according to claim 1, wherein a source is a power supply,
A first PMO having a gate connected to the first input terminal;
An S transistor, a source connected to ground, a gate connected to the second input terminal, and a drain connected to the first PMO.
First NMOS connected to drain of S transistor
A second PMOS transistor having a source connected to the power supply and a gate connected to the drain of the first PMOS transistor;
A MOS transistor has a source grounded, a gate connected to the third input terminal, and a drain connected to the second P-type terminal.
A second NMOS transistor connected to the drain of the MOS transistor;
2. The delay circuit according to claim 1, wherein a connection point between a transistor and each drain of the second NMOS transistor is connected to the output terminal. 3. A plurality of the small delay circuits are cascaded, and the input signal is input to a second input terminal of a first stage small delay circuit. The output terminal of each preceding small delay circuit is connected to the second input terminal, and a target delay signal is output from the output terminal of the last small delay circuit. The delay circuit as described. 4. A delay circuit for receiving a target logical input signal and delaying the signal, comprising: a non-inverting circuit for outputting a non-inverted signal obtained by non-inverting the input signal; and n (n is an integer of 1 or more) ), The small delay circuit has two input terminals and one output terminal, the first input terminal receives the input signal, and the second
Wherein the output of the non-inverting circuit is input to an input terminal of the delay circuit, and the target delay signal is obtained from the output terminal. 5. The small delay circuit has a source connected to a power supply,
A PMOS transistor having a gate connected to the first input terminal, an NMOS transistor having a source grounded, a gate connected to the second input terminal, and a drain connected to the drain of the PMOS transistor; 5. The inverter according to claim 4, further comprising an inverting circuit having an input terminal connected to a connection point of each drain of the transistor and the NMOS transistor, and an output terminal of the inverting circuit being connected to the output terminal. Delay circuit. 6. A plurality of said small delay circuits are cascade-connected, said input signal is inputted to a second input terminal of a first stage small delay circuit, and a second stage and subsequent small delay circuits are provided. The output terminal of each preceding small delay circuit is connected to the second input terminal, and a target delay signal is output from the output terminal of the last small delay circuit. The delay circuit as described.