JPH11162164A - Dram and 3-transistor type dram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use the single power supply of a device as an initial voltage of a dummy cell by delaying a timing when the dummy cell opens as compared with the timing when a memory cell opens by a specific amount of time and by constituting the dummy cell in the same dimension as the memory cell. SOLUTION: In a memory cell array 1, a 3-transistor-type memory cell 14 for storing 1 or 0 is connected to each intersecting part between a plurality of bit pairs and word lines. Further, a dummy cell 15 is connected to each intersecting part between each pair of bit line 11-1a, 11-1b... and a dummy read word line 13. A diffusion resistor 16 is inserted into the dummy read word line 13. By selecting the resistance of the diffusion resistor 16 so that the read bit line of the dummy cell 15 reaches a potential at the middle of L and H levels, a timing when the dummy cell opens can be delayed from that when the memory cell opens.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a D-RAM and a three-transistor DRAM employing a read method using dummy cells.

[0002]

2. Description of the Related Art Generally, a DRAM stores 1-bit information ("1", "0") according to the presence or absence of electric charge stored in a capacitor in each memory cell. At the time of reading, the electric charge of the capacitor is transferred to a bit line precharged to a predetermined voltage, and the minute voltage is amplified by a sense amplifier to read information.

In order to prevent erroneous reading, a reading method using a dummy cell which outputs an intermediate potential between the "H" level and the "L" level is usually adopted.

According to the read method using the dummy cells, the sense amplifier compares the dummy potential with the value of the storage capacity of the selected cell when sensing the storage capacity of the memory cell, and reads the data based on the comparison result. The "H" level and the "L" level of the data are determined.

Hereinafter, a conventional DRAM using the dummy cell system will be described.

FIG. 6 is an equivalent circuit diagram of a conventional DRAM disclosed in Japanese Patent Application Laid-Open No. 54-52432.
One row of 64 memory arrays is shown. FIG.
FIG. 7 is a circuit diagram showing a configuration of a row decoder of the DRAM shown in FIG.

In this DRAM, a pair of bit lines DL1 and DL2 are connected to left and right nodes of a sense amplifier SA using a balanced flip-flop, and each bit line DL1
1 and DL2 each have a plurality of memory cells MC1 m
(M = 1,... I ... j,... 32), MC2 m (m = 1,.
.. 32) and one dummy cell DC1, DC21. Then, information is read out by simultaneously selecting a memory cell on one bit line and a dummy cell on the other bit line.

For example, when reading information (for example, "0") of the memory cell MC1m on the left side of the sense amplifier SA, first, the precharge of the bit lines DL1 and DL2 is performed by the "L" level of the signals φP and φR. Dummy cell DC1
, DC2 are written. Then, the signal .phi.Q becomes "H" level, and the row decoder of FIG.
Four word lines WL1 m (m = 1,... I ... j,.
2) and the dummy cell word line DWL2 are selected and set to "H" level.

As a result, the transistors of the memory cell MC1m and the dummy cell DC2 are turned on. As a result, charge is distributed between the memory cell MC1m, the bit line DL1, the dummy cell DC2, and the bit line DL1. Thereafter, when the signal φs becomes “H” level, discrimination of the stored information by the sense amplifier SA is performed, and the bit line D
L1 goes to "L" level and bit line DL2 goes to "H" level. Thus, the storage information (for example, "0") of the memory cell MC1m is read.

In the DRAM of this embodiment, when the storage level of the memory cell is floating by ΔV at the time of reading, the information discriminating ability of the sense amplifier SA is remarkably reduced. In response to the gate application signal φQ of the transistor connected to the bit line,
At the same time, the rise of the gate application signal φQ ′ of the transistor connecting the selected dummy cell to the bit line is delayed by the delay circuit DEL.

The above-mentioned DRAM is a one-transistor type in which one MOS transistor and one MOS capacitor are provided to constitute one memory cell. In recent years, however, a three-transistor type which can further simplify the manufacturing process is described. DR
AM is being generalized.

That is, at the time of reading, in a one-transistor type DRAM, since charge is directly distributed between a capacitor in a memory cell and a bit line, the capacitance of the capacitor needs to be increased. In the transistor type, charge is not distributed between the capacitor of the memory cell and the bit line. Therefore, since the capacitor of the memory cell can be made smaller than that of the one-transistor type, the manufacturing process does not need to be complicated.

FIG. 8 is a circuit diagram showing a configuration of a main part of a conventional three-transistor DRAM, in which one selected memory cell is shown. FIG. 9 is a graph showing a change in bit line potential at the time of reading in the DRAM of FIG.

At the time of writing in this DRAM, the write word line 102 goes to "H" level, and as a result, the transistor 105c of the memory cell 105 is turned on, and the "H" level ("1") transferred to the write bit line 103 is turned on. ”),
Write data of “L” level (“0”) is written to the capacitor CS.

At the time of reading, the precharge signal PCS
As a result, the transistors 121 and 122 are turned on, the memory cell bit line 104 and the dummy bit line 112 are precharged, and the read word line 101 and the dummy read word line 111 are simultaneously set to the “H” level. As a result, in the memory cell 105, the transistor 105a is turned on. At this time, if “1” is stored in the capacitor CS,
The “L” level is transferred to the memory cell bit line 104 via the transistor 105b (see P1 in FIG. 9). Conversely, if “0” is stored in the capacitor CS, the transistor 105b is off, so that the memory Cell bit line 1
04 is maintained at the “H” level (see P2 in FIG. 9).

On the other hand, in the dummy cell 113, since the initial voltage VDD / 2 is supplied to the gate of the transistor 113b, when the transistor 113a is turned on by the "H" level of the dummy read word line 111, the dummy bit line 112 becomes "H". The potential is set to an intermediate potential between the “L” level and the “L” level (see P3 in FIG. 9). This intermediate potential is a potential that changes about halfway between changes in the amount of leakage of the electric charge with time when the memory cell holds the “H” level or the “L” level. is there.

In response to a sense timing signal STS, the sense amplifier 130 performs a memory cell bit line 1 at a predetermined ST.
The potential of the read data is compared with the potential of the dummy bit line 112 to determine the “H” level and the “L” level of the read data.

FIG. 10 shows another conventional three-transistor type D.
FIG. 2 is a circuit diagram illustrating a main configuration of a RAM.

This DRAM differs from the DRAM of FIG. 8 in that the dummy cell 113 is replaced by a dummy cell 141 having another structure, and the other configuration is the same as that of FIG.

The dummy cell 141 of this embodiment is composed of transistors 141a and 141b having dimensions (transistor sizes) different from those of other memory cells. The supply voltage VDD of the DRAM is applied to the gate of the transistor 141b as an initial voltage. , The dummy bit line 112 is set to the intermediate potential at the time of reading.

[0021]

However, the above-mentioned conventional DRAM has the following problems.

(1) In the one-transistor DRAM of the above publication (FIGS. 6 and 7), the bit lines DL are provided by dummy cells.
In order to set 2 to an intermediate potential, its dimensions had to be changed from other memory cells. From the viewpoint of circuit symmetry and degree of integration, it is desirable that the dimensions of the dummy cells be the same as those of the other memory cells. If the dimensions of the dummy cells are different from the memory cells and the symmetry of the circuit is broken, the characteristics of the DRAM will vary. Could occur.

Even if the dimensions of the dummy cell are the same as those of the other memory cells,
It is necessary to change the initial voltage applied to the capacitor of the dummy cell from the power supply potential VD of the device to a lower intermediate potential. Although there is a simple method such as resistance division to generate the intermediate potential, it is difficult to obtain a desired potential accurately by this method. Is a problem for important DRAMs.

(2) The three-transistor DRAM shown in FIGS. 8 and 10 has the same problem as the DRAM disclosed in the above publication. That is, in the DRAM of FIG.
It is necessary to generate an initial voltage VDD / 2 to be applied to the gate of the transistor 113b of FIG.
In the RAM, the transistor 140 of the dummy cell 140
It is necessary to change the dimensions of a and 140b.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. An object of the present invention is to make it possible to form a dummy cell with the same dimensions as a memory cell and to use a single unit of the device as an initial voltage of the dummy cell. An object of the present invention is to provide a DRAM and a three-transistor type DRAM which can use a power supply. Another object is to provide a DRAM and a three-transistor type D that can improve the characteristics and the degree of integration.
To provide RAM.

[0026]

In order to achieve the above object, a DRAM according to a first aspect of the present invention is characterized by a precharge circuit for precharging first and second bit lines with a power supply potential in a read mode. A word line selection circuit for selecting first and second word lines designated by a row address based on an external signal supplied in the read mode, the first bit line and the first word A memory cell connected to a crossing point of the first word line and opened when the first word line is selected, and outputting storage information corresponding to a high level / low level to the precharged first bit line; Connected to the intersection of a second bit line and the second word line, and opened when the second word line is selected,
A dummy cell for setting the precharged second bit line to an intermediate potential that is an intermediate level between the high level and the low level; and a dummy cell at a predetermined timing after selection of the first and second word lines. In a DRAM including a sense amplifier that compares the potentials of the first and second bit lines and determines and outputs information read from the memory cell, the timing of opening the dummy cell is determined by the timing of opening the memory cell. A delay means for delaying the dummy cell by a predetermined time, the dummy cell has the same dimensions as the memory cell, and holds a charge for setting the second bit line to the intermediate potential using the power supply potential. In the configuration.

According to the first aspect of the present invention, the timing of opening the dummy cell is delayed by a predetermined time from the timing of opening the memory cell by the delay means, so that the dummy cell has the same dimension as that of the memory cell and has a single device. Even in the configuration using the power supply potential, the dummy cell accurately sets the second bit line to the intermediate potential, and the sense amplifier accurately determines and outputs the read information.

A feature of the DRAM according to the second invention is that, in the first invention, the delay means is provided on the second word line at a position between the word line selection circuit and the dummy cell. That is, the diffusion resistance has been set.

According to the second aspect, the delay means can be easily formed even in an integrated circuit.

A third aspect of the present invention is a DRAM according to the first aspect, wherein the delay means selects the second word line later than the first word line to select the second word line. In a delay circuit for delaying the delay time.

According to the third aspect, the delay means is simply configured.

Fourth invention, a three-transistor type DRA
The feature of M is that one electrode serving as a source or a drain of the first MOS transistor is connected to the gate of the second MOS transistor, the other electrode is connected to the write bit line, The source of the transistor is grounded, the drain of the transistor is connected to one electrode serving as the source or drain of the third MOS transistor, and the other electrode is connected to a read bit line.
A memory cell having a gate of an OS transistor connected to a write word line and a gate of the third MOS transistor connected to a read word line;
Fourth MOS having the same size as the type transistor
The gate of the type transistor is connected to the power supply, the source is grounded, and the drain is connected to one electrode serving as the source or drain of a fifth MOS transistor having the same size as the third MOS transistor. And
The other electrode is connected to the dummy bit line, and the fifth
A dummy cell in which the gate of the MOS transistor is connected to a dummy word line, a drain of the sixth MOS transistor is connected to the power supply, and a source thereof is connected to the read bit line. A precharge circuit in which a drain of a transistor is connected to the power supply and a source thereof is connected to the dummy bit line, and a read word line and a dummy word line specified by a row address are selected in a read mode. A word line selection circuit to be activated by a dummy word line, a diffusion resistor provided in the dummy word line at a position between the word line selection circuit and the dummy cell, the read bit line and the dummy bit line. A differential amplifier as an input signal, wherein in the read mode, the read bit line and the dummy bit line The differential amplifier compares the potentials of the read bit line and the dummy bit line at a predetermined timing after the read word line and the dummy word line are selected, The purpose is to determine and output the information read out.

According to the fourth aspect, the three-transistor DRAM exhibits the same operation as the first and second aspects.

The three-transistor type DRA according to the fifth invention
The feature of M is that one electrode serving as a source or a drain of the first MOS transistor is connected to the gate of the second MOS transistor, the other electrode is connected to the write bit line, The source of the transistor is grounded, the drain of the transistor is connected to one electrode serving as the source or drain of the third MOS transistor, and the other electrode is connected to a read bit line.
A memory cell having a gate of an OS transistor connected to a write word line and a gate of the third MOS transistor connected to a read word line;
Fourth MOS having the same size as the type transistor
The gate of the type transistor is connected to the power supply, the source is grounded, and the drain is connected to one electrode serving as the source or drain of a fifth MOS transistor having the same size as the third MOS transistor. And
The other electrode is connected to the dummy bit line, and the fifth
A dummy cell in which the gate of the MOS transistor is connected to a dummy word line, a drain of the sixth MOS transistor is connected to the power supply, and a source thereof is connected to the read bit line. A precharge circuit having a drain connected to the power supply and a source connected to the dummy bit line, and the read word line and the read word line specified by a row address based on an external signal supplied in a read mode. A word line selection circuit for selecting and activating a dummy word line;
A delay circuit for delaying the external signal in order to activate the dummy word line later than the read word line, and to set the read bit line and the dummy bit line in the read mode. The differential amplifier compares the potentials of the read bit line and the dummy bit line at a predetermined timing after the read word line and the dummy word line are selected, and The purpose is to determine and output the information read out.

According to the fifth aspect, the three-transistor DRAM exhibits the same operation as the first and third aspects.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an overall configuration of a DRAM according to the first embodiment of the present invention.

This DRAM includes a memory cell array 1 for storing information, a row decoder 2 for selecting a row direction of the memory cell array 1, and a column decoder 3 for selecting a column direction of the memory cell array 1. Further, a sense amplifier unit 4 for amplifying read data / write data is connected to the memory cell array 1, and an input buffer 5A and an output buffer 5B are connected via the sense amplifier unit 4.

The write data I0 is input to the input buffer 5A.
To I15, and read data O0 to O15 are output from the output buffer 5B. The output state of the output buffer 5B is controlled by the output enable OE (bar).

The row decoder 2 is connected to a row address buffer 6 for driving row addresses A9 to A16, and the column decoder 3 is connected to column addresses A0 to A8.
Are connected. An address generation counter 8 for refresh (CBR system) is provided, and a clock generation circuit 9 for generating operation timing of the DRAM is provided. The clock generation circuit 9 has a write enable W
E (bar), row address strobe RAS (bar), and column address strobe CAS (bar) are supplied.

FIG. 2 shows the memory cell array 1 shown in FIG.
2 is a schematic diagram showing a configuration of a row decoder 2. FIG.

The memory cell array 1 of this embodiment has a plurality of bit line pairs 11-1a, 11-1b, 11-2a, 1
, And the word lines 12-1, 12-2,..., Are connected to three-transistor type memory cells 14 that store information of “1” or “0”, respectively. Further, each bit line pair 11-1a, 11-1b, 1
1-2a, 11-2b,... And the dummy read word line 13
Is connected to a dummy cell 15 at each intersection. A diffusion resistor 16 which is a feature of the present embodiment is inserted in the dummy read word line 13.

Each bit line pair 11-1a, 11-
1b,... Have sense amplifiers 4-1 and 4-2, respectively.
Are connected to the row decoder 2, and the dummy read word lines 13 are connected to the row decoder 2 via the diffusion resistors 16.

The row decoder 2 comprises a memory cell decoding section 2a and a dummy decoding section 2b.
The row address A9 from the row address buffer 6 is generated by the row decode clock RCL generated from (bar).
To A16, and a predetermined one of the word lines 12-1... Is selected. The dummy decode unit 2b decodes the address A9 from the row address buffer 6 by the row decode clock RCL, and activates the dummy read word line 13.

FIG. 3 shows the memory cell array 1 shown in FIG.
Is a circuit diagram showing the details of the first embodiment, and only columns of the sense amplifiers 4-1 are shown for simplification of the description.

As shown in the figure, the memory cell 14 includes a pair of symmetrical memory cells 14A (for even numbers) and 14B.
(For odd numbers), and each memory cell 14A, 14B
Each is composed of a reading transistor 14a, a charge holding transistor 14b, a writing transistor 14c, and a capacitor CS. A read word line (even) 12-1a and a write word line (even) 12-1b are connected to the memory cell 14A, and a read word line (odd) 12-1c and a write word line (odd) are connected to the memory cell 14B. ) 12-1d are connected.

The dummy cell 15 also comprises a pair of symmetrical dummy cells 15A (for even numbers) and 15B (for odd numbers). Each of the dummy cells 15A and 15B is composed of a readout transistor 15a and a charge holding transistor 15b. The initial voltage applied to the gate of the transistor 15b is the same as the power supply potential VDD of the DRAM, and the dimensions of the transistors 15a and 15b are the same as those of the transistors 14a and 14b of the memory cell 14. That is, the dummy cells 15A and 15B have a shape in which the write portions of the memory cells 14A and 14B are omitted.

The dummy cells 15A and 15B have
A dummy read word line (even number) 13a and a dummy read word line (odd number) 13b are connected to each other, and the dummy read word line (even number) 13a and the dummy read word line (odd number) 13b are connected via diffusion resistors 16a and 16b. Connected to the row decoder 2 and the word line 12-1.
a to the word line 12-1d are directly connected to the row decoder 2.

Further, the power supply VDD and the bit line pair 11-1
a, 11-1b are connected to precharge transistors 18a, 18b, respectively, and between the bit line pair 11-1a, 11-1b, a precharge transistor 18c is connected, so that precharge is performed. A circuit 18 is configured. The gates of these transistors 18a to 18c have precharge signals PCG at the time of precharge.
Is applied.

The bit line pairs 11-1a and 11-1b
The sense amplifier 4-1 connected between the transistors 4
a, 4b, and operates at a predetermined timing according to the sense timing signal STS to amplify a delicate potential difference between the bit line pair 11-1a and 11-1b at the time of reading to store data in the memory cell 14. The “H” level and the “L” level of the information are determined, and the data line 19
a, 19a.

Next, the read operation of the DRAM of this embodiment will be described with reference to the graph of FIG. FIG. 4 is a graph showing the fluctuation of the bit line potential at the time of reading in the present embodiment.

At the time of reading, write enable WE
(Bar) is set to the “H” level (inactive), and the address A
This is performed by giving 0 to A16. The precharge signal PCG attains the "H" level, and the bit line pair 11-1a, 11-1
b is precharged to VDD. Also, the row address strobe RAS (bar) becomes “L” level (activated), and the row address A from the row address buffer 6 is
9 to A16 are taken into the row decoder 2. When the row addresses A9 to A16 are decoded by the row decoder 2, the row decoder 2 causes the n read word lines 12
.. And the dummy read word line 13 are simultaneously selected.

For example, a read word line (even number) 12-1a
Is selected and turned to the "H" level, the transistor 14a is turned on. At this time, if "1" is stored in the capacitor CS, the "L" level is changed to the bit line pair 11- through the transistor 14b. 1b (see Q1 in FIG. 4). Conversely, if "0" is stored in the capacitor CS, the transistor 14b is off, and the bit line pair 11-1b is held at the "H" level. (See Q2 in FIG. 9). At this time, the bit line pair 11-1b
Is gradually reduced by leakage as shown by Q1 and Q2 in FIG.

On the other hand, in the dummy cell 15, as a result of selecting the dummy read word line (even number) 13a, the dummy read word line (even number) 13a becomes "H" level and the transistor 15a of the dummy cell 15A is turned on. At this time, due to the delay effect of the diffusion resistor 16a, the timing at which the transistor 15a is turned on is a predetermined time DL longer than the timing at which the transistor 14a of the memory cell 14 is turned on.
(See FIG. 4).

As a result, the potential of the bit line pair 11-1a is reduced as shown by Q3 in FIG. 4, and the potential between the "L" level (Q1) and the "H" level (Q2) is near the sense timing ST. (Q3).
Therefore, the read bit line of the dummy cell 15 is Q3
It is necessary to set the resistance value of the diffusion resistor 16 so as to make the transition state as described above.

Then, in response to a sense timing signal STS activated at a predetermined sense timing ST, the sense amplifier 4-1 compares the potential of the bit line pair 11-1b with the intermediate potential of the bit line pair 11-1a to read. The data "H" level and "L" level are determined, and the result is output to the output buffer 5B via the data lines 19a and 19b. At this time, since the output enable OE (bar) is activated, the 16-bit read data O0 to O1 is output.
5 is output from the output buffer 5B to the outside.

As described above, in this embodiment, by inserting the diffusion resistor 16 into the dummy read word line 13,
At the time of reading, the dummy cell 15 is opened with a timing delayed from the selected memory cell 14, so that not only the intermediate voltage need not be used for the initial voltage of the dummy cell as in the conventional circuit, but also the dummy cell 15 Except for the part, the same memory cell 14 can be used. This simplifies the circuit and enables high integration.

Next, a second embodiment of the present invention will be described.

FIG. 5 shows a DR according to a second embodiment of the present invention.
FIG. 2 is a schematic diagram showing a configuration of a memory cell array 1 and a row decoder 2 in AM.

This embodiment is different from the first embodiment in that the timing of opening the dummy cell 15 using the diffusion resistor 16 is automatically generated inside the memory cell array 1 in the first embodiment. The present embodiment is characterized in that the timing for opening the dummy cell 15 can be controlled by an external signal.

More specifically, a delay circuit 2c in which a plurality of inverters are connected in cascade is provided in the row decoder 2, and a row decode clock RCL from the clock generation circuit 9 is sent to the dummy decode unit 2b via the delay circuit 2c. Supply. The delay value of the delay circuit 2c is
As shown in FIG. 4, it is necessary to set the read bit line of the dummy cell 15 to have a transition state like Q3.

Even with such a configuration, the same operation and effect as in the first embodiment can be obtained.

[0062]

As described above in detail, according to the DRAM of the first aspect, the delay means for delaying the timing of opening the dummy cell by a predetermined time from the timing of opening the memory cell is provided. Since they are configured with the same dimensions, the characteristics of the circuit can be improved. Furthermore, since the dummy cell is configured to hold the electric charge for setting the second bit line to the intermediate potential by using the power supply potential of the device, a single power supply of the device can be used as the initial voltage of the dummy cell. As a result, it is not necessary to generate an intermediate potential for the dummy cell as in the related art, and the degree of integration of the circuit can be improved.

According to the DRAM of the second aspect, in the first aspect, the delay means is provided with a diffusion resistor provided on the second word line at a position between the word line selection circuit and the dummy cell. Therefore, the same effect as that of the first invention can be obtained, and the delay means can be easily formed in the integrated circuit.

According to the DRAM of the third aspect, in the first aspect, the delay means delays an external signal in order to select the second word line later than the first word line. Since the circuit is constituted by a circuit, the same effects as those of the first invention can be obtained, and the delay means can be constituted more simply.

Four-transistor type three-transistor DRA
According to M, the same effects as those of the first and second inventions are provided.

The three-transistor type DRA according to the fifth invention
According to M, the same effects as those of the first and third aspects can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a configuration of a memory cell array 1 and a row decoder 2 shown in FIG.

FIG. 3 is a circuit diagram showing details of a memory cell array 1 shown in FIG. 2;

FIG. 4 is a graph showing a change in bit line potential at the time of reading in the first embodiment.

FIG. 5 is a schematic diagram showing a configuration of a memory cell array 1 and a row decoder 2 in a DRAM according to a second embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of a conventional DRAM.

FIG. 7 is a circuit diagram showing a configuration of a row decoder of the DRAM shown in FIG. 6;

FIG. 8 is a circuit diagram showing a main configuration of a conventional three-transistor DRAM.

9 is a graph showing a change in bit line potential at the time of reading in the DRAM of FIG. 8;

FIG. 10 is a circuit diagram showing a main configuration of another conventional three-transistor DRAM.

[Explanation of symbols]

 1 Memory cell array 2 Row decoder 2c Delay circuit 4-1 4-2 Sense amplifier 5B Output buffer 6 Row address buffer 9 Clock generation circuit 11-1a, 11-1b ... Bit line pair 12-1a Read word line (even number) 12-1b Write word line (even number) 12-1c Write word line (odd number) 12-1d Read word line (odd number) 13 Dummy read word line 13a Dummy read word line (even number) 13b Dummy read word line (odd number) 14 Memory Cell 14a Readout transistor 14b Charge retention transistor 14c Write transistor 15 Dummy cell 15a Dummy cell readout transistor 15b Dummy cell charge retention transistor 16 Diffusion resistance 16a, 16b Diffusion resistance 19a, 19a Data line CS capacitor RAS (bar) Row address strobe RCL Row decode clock A9 to A16 Row address

Continuing on the front page (72) Inventor Takayuki Abe 580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Semiconductor System Technology Center (72) Inventor Kyosuke Ogawa 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Co., Ltd. (72) Inventor Masahiro Kimura 25-1 Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Microelectronics Co., Ltd.

Claims (5)

[Claims] 1. A precharge circuit for precharging first and second bit lines with a power supply potential in a read mode, and a first and a second address specified by a row address based on an external signal supplied in the read mode. A word line selection circuit for selecting a second word line; a word line selection circuit connected to an intersection of the first bit line and the first word line; A memory cell for outputting storage information corresponding to a high level / low level to the first bit line, and a second bit line connected to an intersection of the second word line; A dummy cell which is opened when the word line is selected to set the precharged second bit line to an intermediate potential which is an intermediate level between the high level and the low level; Choice At a later specified timing, the first
And a sense amplifier that compares the potential of the second bit line with the potential of the second bit line to determine and output information read from the memory cell. A delay unit for delaying a predetermined time; the dummy cell having the same dimension as the memory cell, and holding the electric charge for setting the second bit line to the intermediate potential using the power supply potential; A DRAM characterized in that: 2. The DRAM according to claim 1, wherein said delay means is a diffusion resistor provided on said second word line at a position between said word line selection circuit and said dummy cell. . 3. The delay circuit according to claim 1, wherein said delay means comprises a delay circuit for delaying said external signal in order to select said second word line later than said first word line. The DRAM as described. 4. A second MOS transistor, wherein one electrode serving as a source or a drain of the first MOS transistor is connected to the gate of the second MOS transistor, and the other electrode is connected to a write bit line. The source of the transistor is grounded, the drain of the transistor is connected to one electrode serving as the source or the drain of the third MOS transistor, and the other electrode is connected to the bit line for reading. A memory cell having a gate connected to a write word line and a gate of the third MOS transistor connected to a read word line; and a fourth MOS transistor having the same size as the second MOS transistor. The gate of the transistor is connected to a power supply, its source is grounded, and its drain is connected to the third transistor.
Fifth M having the same size as the OS transistor
A dummy cell connected to one electrode serving as a source or a drain of the OS transistor, the other electrode connected to a dummy bit line, and a gate of the fifth MOS transistor connected to a dummy word line; The drain of the sixth MOS transistor is connected to the power supply, the source is connected to the read bit line, the drain of the seventh MOS transistor is connected to the power supply, and the source is connected to the dummy bit line. A word line selection circuit for selecting and activating the read word line and the dummy word line specified by a row address in a read mode; and a word line selection circuit and the dummy cell. Between the dummy bit line and the read bit line and the dummy bit line. A differential amplifier that uses a read bit line as an input signal, and in the read mode, the read bit line and the dummy bit line are precharged, and the read word line and the dummy word line are At a predetermined timing after the selection, the potential of the read bit line and the dummy bit line are compared by the differential amplifier, and information read from the memory cell is determined and output. 3-transistor DRAM. 5. A method according to claim 1, wherein one electrode serving as a source or a drain of the first MOS transistor is connected to a gate of the second MOS transistor, and the other electrode is connected to a write bit line. The source of the transistor is grounded, the drain of the transistor is connected to one electrode serving as the source or the drain of the third MOS transistor, and the other electrode is connected to the bit line for reading. A memory cell having a gate connected to a write word line and a gate of the third MOS transistor connected to a read word line; and a fourth MOS transistor having the same size as the second MOS transistor. The gate of the transistor is connected to a power supply, its source is grounded, and its drain is connected to the third transistor.
Fifth M having the same size as the OS transistor
A dummy cell connected to one electrode serving as a source or a drain of the OS transistor, the other electrode connected to a dummy bit line, and a gate of the fifth MOS transistor connected to a dummy word line; The drain of the sixth MOS transistor is connected to the power supply, the source is connected to the read bit line, the drain of the seventh MOS transistor is connected to the power supply, and the source is connected to the dummy bit line. A word line selection circuit that selects and activates the read word line and the dummy word line specified by a row address based on an external signal supplied in a read mode; A delay for delaying the external signal in order to activate the dummy word line later than the read word line. In the read mode, the read bit line and the dummy bit line are precharged, and at a predetermined timing after selection of the read word line and the dummy word line, 3. A three-transistor DRAM, wherein a potential of the read bit line and a potential of the dummy bit line are compared by a differential amplifier to determine and output information read from the memory cell.