JPH11150206A - Substrate for mounting semiconductor element - Google Patents
Substrate for mounting semiconductor elementInfo
- Publication number
- JPH11150206A JPH11150206A JP31474197A JP31474197A JPH11150206A JP H11150206 A JPH11150206 A JP H11150206A JP 31474197 A JP31474197 A JP 31474197A JP 31474197 A JP31474197 A JP 31474197A JP H11150206 A JPH11150206 A JP H11150206A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- underfill
- mounting
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子の実装
基板に関し、詳しくは半田等のバンプ付き半導体素子の
実装基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting substrate for a semiconductor device, and more particularly to a mounting substrate for a semiconductor device having bumps such as solder.
【０００２】[0002]
【従来の技術】従来の半田バンプ付き半導体素子を実装
基板（例えば、印刷配線板）に実装する工程を以下に説
明する。半田バンプ付き半導体素子を、その半田バンプ
を利用して実装基板に半田付けして実装する。その後、
実装基板と半導体素子との間の空間にエポキシ樹脂を充
填する。充填時には実装基板を８０℃程度に加熱してエ
ポキシ樹脂の進入を容易にし、半導体素子と実装基板と
の間のエポキシ樹脂に空隙ができるのを防止する。この
ようなエポキシ樹脂は一般にアンダーフィルと呼ばれて
いる。2. Description of the Related Art A process for mounting a conventional semiconductor device with solder bumps on a mounting board (for example, a printed wiring board) will be described below. A semiconductor element with solder bumps is mounted on the mounting board by soldering using the solder bumps. afterwards,
The space between the mounting board and the semiconductor element is filled with epoxy resin. At the time of filling, the mounting substrate is heated to about 80 ° C. to facilitate the entry of the epoxy resin and to prevent the epoxy resin between the semiconductor element and the mounting substrate from having a gap. Such an epoxy resin is generally called an underfill.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
半導体素子の実装基板にアンダーフィルを充填したので
は、アンダーフィルを塗布した半導体素子の一側部とは
反対側の半導体素子部分にはエポキシ樹脂のフィレット
が形成され難い。そのため、実装基板に対して半導体素
子が不安定になっていた。それを解消するためには、半
導体素子と実装基板との間を十分に埋め尽くす状態にフ
ィレット形成ができるように、さらにエポキシ樹脂を追
加塗布する必要があった。その結果、工程数が多くなる
という問題が生じていた。However, when a conventional mounting board for a semiconductor device is filled with an underfill, an epoxy resin is applied to a portion of the semiconductor device opposite to one side of the semiconductor device to which the underfill is applied. Is difficult to form. Therefore, the semiconductor element has become unstable with respect to the mounting substrate. In order to solve the problem, it is necessary to additionally apply an epoxy resin so that a fillet can be formed in a state where the space between the semiconductor element and the mounting board is sufficiently filled. As a result, there has been a problem that the number of steps is increased.
【０００４】[0004]
【課題を解決するための手段】バンプ付き半導体素子の
実装基板であって、実装基板の半導体素子の実装面側に
は基板パッド部を除いた箇所にソルダーレジスト膜を形
成する。ソルダーレジスト膜は、基板パッド部に実装さ
れる半導体素子の外側周の少なくとも一部分に沿って溝
又は突条部を形成する。基板パッド部に半導体素子が搭
載されているとともに、実装基板と半導体素子との間に
アンダーフィルが充填されている。SUMMARY OF THE INVENTION A solder resist film is formed on a mounting board of a semiconductor element with bumps on a mounting surface side of a semiconductor element of the mounting board except a substrate pad portion. The solder resist film forms a groove or a ridge along at least a part of the outer periphery of the semiconductor element mounted on the substrate pad portion. A semiconductor element is mounted on the substrate pad portion, and an underfill is filled between the mounting substrate and the semiconductor element.
【０００５】上記実装基板においては、基板パッド部に
バンプを介して半導体素子を実装した後、アンダーフィ
ルを半導体素子の一側部に供給すると、そのアンダーフ
ィルは、実装基板と半導体素子との隙間に毛細管現象に
よって進入する。それとともに、溝が形成されれている
ものでは、溝の内部にもアンダーフィルは進入する。す
なわち、アンダーフィルの供給部分の両側に延びる溝を
伝って、アンダーフィルを供給した部分とは半導体素子
を介して反対側の方向に向かって進む。一方、突条部が
形成されているものでは、アンダーフィルは突条部の半
導体素子側に沿っても進行する。すなわち、アンダーフ
ィルの供給部分の両側に延びる突条部に沿って、アンダ
ーフィルを供給した部分とは半導体素子を介して反対側
の方向に向かって進む。その結果、最後には、溝を伝っ
て半導体素子の周囲に回り込んだアンダーフィル、又は
突条部に沿って進んだアンダーフィルと、半導体素子と
実装基板との間を進んだアンダーフィルとがつながり、
それらのアンダーフィルによって、実装基板と半導体素
子との間が完全に充填されて、フィレットが形成され
る。In the above mounting board, after mounting a semiconductor element on a board pad portion via a bump, an underfill is supplied to one side of the semiconductor element, and the underfill causes a gap between the mounting board and the semiconductor element. To enter by capillary action. At the same time, if the groove is formed, the underfill also enters the inside of the groove. In other words, it travels along the groove extending on both sides of the underfill supply portion and proceeds in the direction opposite to the underfill supply portion via the semiconductor element. On the other hand, when the ridge is formed, the underfill also advances along the semiconductor element side of the ridge. In other words, along the protruding ridges extending on both sides of the underfill supply portion, the semiconductor device proceeds in a direction opposite to the underfill supply portion via the semiconductor element. As a result, finally, the underfill that has wrapped around the semiconductor element along the groove or the underfill that has advanced along the ridge and the underfill that has advanced between the semiconductor element and the mounting board are connection,
By these underfills, the space between the mounting substrate and the semiconductor element is completely filled, and a fillet is formed.
【０００６】[0006]
【発明の実施の形態】本発明の第１の実装基板に係わる
実施形態の一例を、図１の概略構成断面図および図２の
平面図によって説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of an embodiment according to a first mounting board of the present invention will be described with reference to a schematic sectional view of FIG. 1 and a plan view of FIG.
【０００７】図１および図２に示すように、実装基板１
には、バンプが付いた半導体素子を実装する部分となる
基板パッド部１１が設けられている。また実装基板１上
には、この基板パッド部１１の部分に開口１２ａを設け
たソルダーレジスト膜１２が形成されている。このソル
ダーレジスト膜１２には、上記基板パッド部１１に実装
される半導体素子３１の外側周に沿ってこの半導体素子
３１を囲む状態に溝２１が形成されている。このよう
に、実装基板１には、上記溝２１を形成した膜、すなわ
ち、ソルダーレジスト膜１２が形成されている。上記の
如くに半導体素子の実装基板１は構成されている。As shown in FIG. 1 and FIG.
Is provided with a substrate pad portion 11 which is a portion for mounting a semiconductor element with a bump. Further, on the mounting substrate 1, a solder resist film 12 having an opening 12a in the portion of the substrate pad portion 11 is formed. The groove 21 is formed in the solder resist film 12 along the outer periphery of the semiconductor element 31 mounted on the substrate pad portion 11 so as to surround the semiconductor element 31. As described above, the film in which the groove 21 is formed, that is, the solder resist film 12 is formed on the mounting substrate 1. The mounting board 1 of the semiconductor element is configured as described above.
【０００８】または上記溝２１は、アンダーフィル（図
示省略）が供給されることになる実装基板１上の部分か
ら基板パッド部１１に実装される半導体素子３１の外側
周に沿って形成することも可能である。言い換えれば、
上記半導体素子の実装基板１はアンダーフィルが供給さ
れる部分を除く基板パッド部１１に実装される半導体素
子３１の外側周に沿って溝２１を形成する構成であって
もよい。Alternatively, the groove 21 may be formed from the portion on the mounting substrate 1 to which the underfill (not shown) is supplied to the outer periphery of the semiconductor element 31 mounted on the substrate pad portion 11. It is possible. In other words,
The semiconductor element mounting substrate 1 may have a configuration in which the groove 21 is formed along the outer periphery of the semiconductor element 31 mounted on the substrate pad portion 11 except for the portion to which the underfill is supplied.
【０００９】上記実装基板１には、通常、半導体素子３
１が、この半導体素子３１に形成されているバンプ（例
えば、半田バンプまたは金バンプ）３２を介して接続さ
れているとともに、この実装基板１とこの半導体素子３
１との間にアンダーフィルが充填されてフィレット（図
示省略）が形成されている。Usually, the semiconductor element 3 is mounted on the mounting substrate 1.
1 are connected via bumps (for example, solder bumps or gold bumps) 32 formed on the semiconductor element 31, and the mounting substrate 1 and the semiconductor element 3
1 is filled with an underfill to form a fillet (not shown).
【００１０】次に上記図１および図２によって説明した
半導体素子の実装基板の適用方法を、図３によって説明
する。図３では、左側に平面図を示し、右側に断面図を
示す。また、前記図１および図２によって説明した構成
部品と同様のものには、同一の符号を付す。Next, a method of applying the semiconductor device mounting board described with reference to FIGS. 1 and 2 will be described with reference to FIG. In FIG. 3, a plan view is shown on the left side, and a cross-sectional view is shown on the right side. The same components as those described with reference to FIGS. 1 and 2 are denoted by the same reference numerals.
【００１１】図３の（１）に示すように、実装基板１の
基板パッド部にバンプ〔図示省略〕を介して半導体素子
３１を実装した後、例えばエポキシ樹脂からなるアンダ
ーフィル３４を半導体素子の一側部３１Ａ側に供給す
る。したがって、溝２１（２１Ａ）〔以下、図３の断面
図では図示省略〕内にも供給される。そのとき、実装基
板１はアンダーフィル３４が流動し易い温度（例えば８
０℃程度）に加熱されている。As shown in FIG. 3A, a semiconductor element 31 is mounted on a substrate pad portion of a mounting substrate 1 via a bump (not shown), and an underfill 34 made of, for example, epoxy resin is applied to the semiconductor element. It is supplied to one side 31A. Therefore, it is also supplied to the groove 21 (21A) (hereinafter, not shown in the cross-sectional view of FIG. 3). At this time, the mounting substrate 1 is heated to a temperature (for example, 8
(About 0 ° C.).
【００１２】そして図３の（２）に示すように、供給さ
れたアンダーフィル３４は、半導体素子３１と実装基板
１との隙間に毛細管現象によって進入するとともに、基
板パッド部に実装されている半導体素子３１の外側周に
沿って形成されている溝２１の内部にも進入する。そし
てアンダーフィル３４は、その供給部分の両側に延びる
溝２１（２１Ｒ，２１Ｌ）を伝って、それを供給した部
分とは半導体素子３１を介して反対側の方向〔矢印方
向〕に向かって進む。As shown in FIG. 3 (2), the supplied underfill 34 enters the gap between the semiconductor element 31 and the mounting substrate 1 by a capillary phenomenon and is mounted on the substrate pad portion. It also enters the inside of the groove 21 formed along the outer periphery of the element 31. Then, the underfill 34 travels along the groove 21 (21R, 21L) extending on both sides of the supply portion, and proceeds in the opposite direction (arrow direction) via the semiconductor element 31 with the portion to which the underfill 34 is supplied.
【００１３】その結果、図３の（３）に示すように、溝
２１を伝って半導体素子３１の周囲に回り込んだアンダ
ーフィル３４と、半導体素子３１と実装基板１との間を
進んだアンダーフィル３４とがつながり、それらのアン
ダーフィル３４によって、バンプ〔図示省略〕によって
生じた実装基板１と半導体素子３１との隙間が完全を埋
め尽くされて、フィレット３３が形成される。As a result, as shown in FIG. 3 (3), the underfill 34 which has passed around the semiconductor element 31 along the groove 21 and the underfill which has advanced between the semiconductor element 31 and the mounting substrate 1. The gaps between the mounting substrate 1 and the semiconductor element 31 caused by the bumps (not shown) are completely filled by the underfills 34, and the fillets 33 are formed.
【００１４】また図示はしないが、アンダーフィル３４
が供給される部分から基板パッド部に実装される半導体
素子３１の外側周に沿って上記溝２１が形成されている
構成（アンダーフィル３４が供給される部分には溝が形
成されている構成）であってもよい。このような構成で
も上記説明したのと同様に、供給されたアンダーフィル
３４は流動するにしたがい上記溝２１の内部に流れ込
む。そしてアンダーフィル３４の一部は溝２１の内部を
伝わって半導体素子３１の周囲に回り込むとともに、そ
の他のアンダーフィル３４は半導体素子３１と実装基板
１との間を進む。その結果、半導体素子３１と実装基板
１との間がアンダーフィル３４によって完全を埋め尽く
されて、フィレット３３が形成される。Although not shown, the underfill 34
In which the groove 21 is formed along the outer periphery of the semiconductor element 31 mounted on the substrate pad portion from the portion where the underfill 34 is supplied (the portion where the underfill 34 is supplied with a groove). It may be. Even in such a configuration, the supplied underfill 34 flows into the groove 21 as it flows, as described above. A part of the underfill 34 travels around the semiconductor element 31 along the inside of the groove 21, and the other underfill 34 advances between the semiconductor element 31 and the mounting board 1. As a result, the space between the semiconductor element 31 and the mounting substrate 1 is completely filled with the underfill 34, and the fillet 33 is formed.
【００１５】本発明の第２の実装基板に係わる実施形態
の一例を、図４の概略構成断面図および図５の平面図に
よって説明する。なお、前記図１および図２によって説
明した構成部品と同様のものには同一符号を付すことに
する。An example of an embodiment according to the second mounting board of the present invention will be described with reference to a schematic sectional view of FIG. 4 and a plan view of FIG. The same components as those described with reference to FIGS. 1 and 2 are denoted by the same reference numerals.
【００１６】図４および図５に示すように、実装基板２
には、バンプが付いた半導体素子を実装する部分となる
基板パッド部１１が設けられている。また実装基板２上
には、この基板パッド部１１の部分に開口１２ａを設け
たソルダーレジスト膜１２が形成されている。このソル
ダーレジスト膜１２には、上記基板パッド部１１に実装
される半導体素子３１の外側周に沿ってこの半導体素子
３１を囲む状態に、かつこの半導体素子３１と所定間隔
を置いた状態に突条部４１が形成されている。上記所定
間隔は、例えば、供給されるアンダーフィル（図示省
略）が半導体素子３１と突条部４１との間を流れ進むこ
とができ、かつ、このアンダーフィルが半導体素子３１
の側周部に十分に付着できるように設定されている。こ
の突条部４１は、例えば上記ソルダーレジスト膜１２か
らなる。上記の如くに半導体素子の実装基板２は構成さ
れている。なお、アンダーフィル（図示省略）が供給さ
れる領域では、突条部４１と基板パッド部１３に実装さ
れる半導体素子３１との間隔を供給されるアンダーフィ
ルがはみ出さない程度に置いて上記突条部４１を形成す
ることが好ましい。As shown in FIG. 4 and FIG.
Is provided with a substrate pad portion 11 which is a portion for mounting a semiconductor element with a bump. Further, on the mounting board 2, a solder resist film 12 having an opening 12a in the portion of the board pad portion 11 is formed. The solder resist film 12 is provided with a projection in a state of surrounding the semiconductor element 31 along the outer periphery of the semiconductor element 31 mounted on the substrate pad portion 11 and at a predetermined distance from the semiconductor element 31. A part 41 is formed. The predetermined interval is such that, for example, the supplied underfill (not shown) can flow between the semiconductor element 31 and the ridge 41 and the underfill is
It is set so that it can be sufficiently adhered to the side peripheral portion. The ridge 41 is made of, for example, the solder resist film 12 described above. The mounting board 2 of the semiconductor element is configured as described above. In the region where the underfill (not shown) is supplied, the interval between the ridge 41 and the semiconductor element 31 mounted on the substrate pad 13 is set such that the supplied underfill does not protrude. It is preferable to form the ridges 41.
【００１７】または上記突条部４１は、アンダーフィル
（図示省略）が供給されることになる実装基板２上の部
分から基板パッド部１１に実装される半導体素子３１の
外側周に沿って、かつその半導体素子３１と所定の間隔
を置いて形成することも可能である。言い換えれば、上
記実装基板２はアンダーフィルが供給される部分を除く
基板パッド部１１に実装される半導体素子３１の外側周
に沿って突条部４１を形成する構成であってもよい。Alternatively, the ridge portion 41 extends from a portion on the mounting substrate 2 to which an underfill (not shown) is supplied to the outer periphery of the semiconductor element 31 mounted on the substrate pad portion 11 and It is also possible to form them at a predetermined interval from the semiconductor element 31. In other words, the mounting substrate 2 may have a configuration in which the ridge 41 is formed along the outer periphery of the semiconductor element 31 mounted on the substrate pad portion 11 except for the portion to which the underfill is supplied.
【００１８】上記実装基板２には、通常、半導体素子３
１がこの半導体素子３１に形成されているバンプ（例え
ば、半田バンプまたは金バンプ）３２を介して接続され
ているとともに、この実装基板２とこの半導体素子３１
との間にアンダーフィルが充填されてフィレット〔図示
省略〕が形成されている。Usually, the semiconductor element 3 is mounted on the mounting substrate 2.
1 are connected via bumps (for example, solder bumps or gold bumps) 32 formed on the semiconductor element 31, and the mounting substrate 2 and the semiconductor element 31 are connected to each other.
Is filled with an underfill to form a fillet (not shown).
【００１９】次に上記図４および図５によって説明した
半導体素子の実装基板の適用方法を、図６によって説明
する。図６では、左側に平面図を示し、右側に断面図を
示す。また、前記図４および図５によって説明した構成
部品と同様のものには、同一の符号を付す。Next, a method of applying the semiconductor element mounting board described with reference to FIGS. 4 and 5 will be described with reference to FIG. In FIG. 6, a plan view is shown on the left side, and a cross-sectional view is shown on the right side. The same components as those described with reference to FIGS. 4 and 5 are denoted by the same reference numerals.
【００２０】図６の（１）に示すように、実装基板２の
基板パッド部にバンプ（例えば、半田バンプまたは金バ
ンプ）〔図示省略〕を介して半導体素子３１を実装した
後、例えばエポキシ樹脂からなるアンダーフィル３４を
半導体素子の一側部３１Ａ側に供給する。その際、アン
ダーフィル３４は半導体素子３１の一側部３１Ａと突条
部４１〔以下、図６の断面図では図示省略〕との間に供
給するようにする。そのとき、実装基板２はアンダーフ
ィル３４が流動し易い温度（例えば８０℃程度）に加熱
されている。As shown in FIG. 6A, after the semiconductor element 31 is mounted on the board pad portion of the mounting board 2 via a bump (for example, a solder bump or a gold bump) (not shown), for example, an epoxy resin Is supplied to one side 31A of the semiconductor element. At this time, the underfill 34 is supplied between one side 31A of the semiconductor element 31 and the ridge 41 (hereinafter, not shown in the sectional view of FIG. 6). At this time, the mounting substrate 2 is heated to a temperature (for example, about 80 ° C.) at which the underfill 34 easily flows.
【００２１】そして図６の（２）に示すように、供給さ
れたアンダーフィル３４は、半導体素子３１と実装基板
２との隙間に毛細管現象によって進入するとともに、基
板パッド部の外側部に沿って、すなわち、実装されてい
る半導体素子３１と所定間隔を置いて形成されている突
条部４１との間に沿って進行する。そしてアンダーフィ
ル３４は、アンダーフィル３４の供給部分の両側に延び
る突条部４１（４１Ｒ，４１Ｌ）の半導体素子３１側に
沿って、それを供給した部分とは半導体素子３１を介し
て反対側の方向（矢印方向）に向かって進む。As shown in FIG. 6 (2), the supplied underfill 34 enters the gap between the semiconductor element 31 and the mounting substrate 2 by capillary action, and along the outside of the substrate pad portion. That is, it travels between the mounted semiconductor element 31 and the ridge 41 formed at a predetermined interval. The underfill 34 extends along the semiconductor element 31 side of the ridges 41 (41R, 41L) extending on both sides of the supply part of the underfill 34, and is opposite to the part to which the underfill 34 is supplied via the semiconductor element 31. Proceed in the direction (arrow direction).
【００２２】その結果、図６の（３）に示すように、突
条部４１の半導体素子３１側に沿って半導体素子３１の
周囲に回り込んだアンダーフィル３４と、半導体素子３
１と実装基板２との間を進んだアンダーフィル３４とが
つながり、それらのアンダーフィル３４によって、バン
プ〔図示省略〕によって生じた実装基板２と半導体素子
３１との隙間が完全を埋め尽くされて、フィレット３３
が形成される。As a result, as shown in FIG. 6 (3), the underfill 34 wrapping around the semiconductor element 31 along the semiconductor element 31 side of the ridge 41 and the semiconductor element 3
1 and the underfill 34 that has advanced between the mounting substrate 2 are connected, and the underfill 34 completely fills the gap between the mounting substrate 2 and the semiconductor element 31 caused by a bump (not shown). , Fillet 33
Is formed.
【００２３】また図示はしないが、アンダーフィル３４
が供給される部分から基板パッド部に実装される半導体
素子３１の外側周に沿って上記突条部４１が形成されて
いる構成（アンダーフィル３４が供給される部分には突
条部が形成されている構成）であってもよい。このよう
な構成でも上記説明したのと同様に、供給されたアンダ
ーフィル３４は流動するにしたがい上記突条部４１と半
導体素子３１との間に流れ込む。そしてアンダーフィル
３４の一部は突条部４１と半導体素子３１との間を伝わ
って半導体素子３１の周囲に回り込むとともに、その他
のアンダーフィル３４は半導体素子３１と実装基板２と
の間を進む。その結果、半導体素子３１と実装基板２と
の間がアンダーフィル３４によって完全を埋め尽くされ
て、フィレット３３が形成される。Although not shown, the underfill 34
Is formed along the outer periphery of the semiconductor element 31 mounted on the substrate pad portion from the portion where the underfill 34 is supplied (the portion where the underfill 34 is supplied is formed with a ridge portion). Configuration). Even in such a configuration, the supplied underfill 34 flows between the ridge 41 and the semiconductor element 31 as it flows, as described above. Part of the underfill 34 travels between the ridge 41 and the semiconductor element 31 and goes around the semiconductor element 31, and the other underfill 34 travels between the semiconductor element 31 and the mounting board 2. As a result, the space between the semiconductor element 31 and the mounting substrate 2 is completely filled with the underfill 34, and the fillet 33 is formed.
【００２４】なお、上記各実施形態における実装基板に
は、通常、ガラスエポキシ基板を用いるが、その他の材
質のものであってもよい。また、基板パッド部に実装さ
れる半導体素子の外周部における当該実装基板に溝また
は突条部を直接形成してもよい。The mounting board in each of the above embodiments is usually a glass epoxy board, but may be made of another material. Further, a groove or a ridge may be directly formed on the mounting substrate in the outer peripheral portion of the semiconductor element mounted on the substrate pad portion.
【００２５】[0025]
【発明の効果】以上、説明したように本発明によれば、
少なくともアンダーフィルが供給される部分から実装基
板の基板パッド部に実装される半導体素子の外側周に沿
って溝又は突条部が形成されているので、供給したアン
ダーフィルは溝の内部を伝って又は突条部と半導体素子
との間に沿って進行し、半導体素子の周囲に回り込むこ
とができる。そのため、半導体素子と実装基板との間を
進んだアンダーフィルとつながって、実装基板と半導体
素子との間が完全に充填することができるので、信頼性
の高いフィレットの形成が可能になる。またアンダーフ
ィルを追加供給するような工程が不要になり、スループ
ットの向上が図れる。As described above, according to the present invention,
Since a groove or a ridge is formed along the outer periphery of the semiconductor element mounted on the substrate pad portion of the mounting board from at least the portion to which the underfill is supplied, the supplied underfill travels along the inside of the groove. Alternatively, it can progress along the ridge portion and the semiconductor element and go around the semiconductor element. Therefore, the underfill that has progressed between the semiconductor element and the mounting substrate is connected, and the space between the mounting substrate and the semiconductor element can be completely filled, so that a highly reliable fillet can be formed. Further, a step of additionally supplying an underfill is not required, and the throughput can be improved.
【図１】第１の本発明に係わる実施形態の概略構成断面
図である。FIG. 1 is a schematic configuration sectional view of an embodiment according to a first invention.
【図２】第１の本発明に係わる実施形態の平面図であ
る。FIG. 2 is a plan view of the first embodiment according to the present invention.
【図３】図１，図２に示した実装基板の適用方法の説明
図である。FIG. 3 is an explanatory diagram of a method of applying the mounting board shown in FIGS. 1 and 2;
【図４】第２の本発明に係わる実施形態の概略構成断面
図である。FIG. 4 is a schematic sectional view of a second embodiment of the present invention.
【図５】第２の本発明に係わる実施形態の平面図であ
る。FIG. 5 is a plan view of a second embodiment according to the present invention.
【図６】図４，図５に示した実装基板の適用方法の説明
図である。FIG. 6 is an explanatory diagram of a method of applying the mounting board shown in FIGS. 4 and 5;
１ 実装基板 １１ 基板パッド部 １２ ソルダーレジスト膜 ２１ 溝 ３１ 半導体素子 ３２ バンプ DESCRIPTION OF SYMBOLS 1 Mounting board 11 Substrate pad part 12 Solder resist film 21 Groove 31 Semiconductor element 32 Bump
Claims (1)
て、 前記実装基板の前記半導体素子の実装面側には基板パッ
ド部を除いた箇所にソルダーレジスト膜を形成し、 前記ソルダーレジスト膜は、前記基板パッド部に実装さ
れる半導体素子の外側周の少なくとも一部分に沿って溝
又は突条部を形成し、 前記基板パッド部に前記半導体素子が搭載されていると
ともに、前記実装基板と前記半導体素子との間にアンダ
ーフィルが充填されていることを特徴とする半導体素子
の実装基板。1. A mounting board for a semiconductor device with bumps, wherein a solder resist film is formed on a portion of the mounting substrate other than a substrate pad portion on a mounting surface side of the semiconductor device, wherein the solder resist film comprises: A groove or a ridge is formed along at least a part of an outer periphery of a semiconductor element mounted on the substrate pad portion, and the semiconductor element is mounted on the substrate pad portion, and the mounting substrate and the semiconductor element are formed. A semiconductor element mounting substrate, wherein an underfill is filled between the substrate and the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31474197A JPH11150206A (en) | 1997-11-17 | 1997-11-17 | Substrate for mounting semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31474197A JPH11150206A (en) | 1997-11-17 | 1997-11-17 | Substrate for mounting semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11150206A true JPH11150206A (en) | 1999-06-02 |
Family
ID=18057033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31474197A Pending JPH11150206A (en) | 1997-11-17 | 1997-11-17 | Substrate for mounting semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11150206A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100884038B1 (en) * | 2006-06-22 | 2009-02-17 | 알프스 덴키 가부시키가이샤 | Electronic component mounted structure |
| US7592708B2 (en) * | 2005-10-07 | 2009-09-22 | Samsung Electro-Mechanics Co., Ltd. | Package board, semiconductor package, and fabricating method thereof |
| US7682872B2 (en) | 2007-03-02 | 2010-03-23 | Stats Chippac Ltd. | Integrated circuit package system with underfill |
| US20100155965A1 (en) * | 2008-12-24 | 2010-06-24 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
| KR101022942B1 (en) * | 2008-11-12 | 2011-03-16 | 삼성전기주식회사 | A printed circuit board having a flow preventing dam and a manufacturing method of the same |
| KR101067216B1 (en) | 2010-05-24 | 2011-09-22 | 삼성전기주식회사 | Printed circuit board and semiconductor package with the smae |
| CN102271458A (en) * | 2011-05-11 | 2011-12-07 | 福建星网锐捷网络有限公司 | Printed circuit board (PCB), implementing method of PCB and method for removing electronic component by adopting PCB |
| US8536718B2 (en) | 2010-06-24 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit packaging system with trenches and method of manufacture thereof |
| US8546957B2 (en) | 2010-12-09 | 2013-10-01 | Stats Chippac Ltd. | Integrated circuit packaging system with dielectric support and method of manufacture thereof |
| US9030030B2 (en) | 2010-04-27 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of forming adjacent channel and dam material around die attach area of substrate to control outward flow of underfill material |
-
1997
- 1997-11-17 JP JP31474197A patent/JPH11150206A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7592708B2 (en) * | 2005-10-07 | 2009-09-22 | Samsung Electro-Mechanics Co., Ltd. | Package board, semiconductor package, and fabricating method thereof |
| KR100884038B1 (en) * | 2006-06-22 | 2009-02-17 | 알프스 덴키 가부시키가이샤 | Electronic component mounted structure |
| US7682872B2 (en) | 2007-03-02 | 2010-03-23 | Stats Chippac Ltd. | Integrated circuit package system with underfill |
| KR101022942B1 (en) * | 2008-11-12 | 2011-03-16 | 삼성전기주식회사 | A printed circuit board having a flow preventing dam and a manufacturing method of the same |
| US20100155965A1 (en) * | 2008-12-24 | 2010-06-24 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
| US8169083B2 (en) * | 2008-12-24 | 2012-05-01 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
| US9030030B2 (en) | 2010-04-27 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of forming adjacent channel and dam material around die attach area of substrate to control outward flow of underfill material |
| KR101067216B1 (en) | 2010-05-24 | 2011-09-22 | 삼성전기주식회사 | Printed circuit board and semiconductor package with the smae |
| US8253034B2 (en) | 2010-05-24 | 2012-08-28 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board and semiconductor package with the same |
| US8536718B2 (en) | 2010-06-24 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit packaging system with trenches and method of manufacture thereof |
| US8546957B2 (en) | 2010-12-09 | 2013-10-01 | Stats Chippac Ltd. | Integrated circuit packaging system with dielectric support and method of manufacture thereof |
| CN102271458A (en) * | 2011-05-11 | 2011-12-07 | 福建星网锐捷网络有限公司 | Printed circuit board (PCB), implementing method of PCB and method for removing electronic component by adopting PCB |
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