JPH11142878A - Formation of display transistor array panel - Google Patents

Formation of display transistor array panel

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Publication number
JPH11142878A
JPH11142878A JP31029997A JP31029997A JPH11142878A JP H11142878 A JPH11142878 A JP H11142878A JP 31029997 A JP31029997 A JP 31029997A JP 31029997 A JP31029997 A JP 31029997A JP H11142878 A JPH11142878 A JP H11142878A
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substrate
forming
transistor array
array panel
method
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JP3406207B2 (en
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Masabumi Shimizu
正文 清水
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Sharp Corp
シャープ株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F2001/13613Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit the semiconductor element is formed on a first substrate and thereafter transferred to the final cell substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate

Abstract

PROBLEM TO BE SOLVED: To sharply reduce a manufacturing cost. SOLUTION: Plural TFT elements 43 are formed on a 1st substrate consisting of a Si substrate at pitches dx/m, dy/n with respective element separation grooves 44 intervened. The dx and dy are array pitches of pixels and each of (m) and (n) is a natural number of >=2. A 2nd substrate 45 is stuck to the 1st substrate with UV peeling resin 46, and after removing the 1st substrate by etching, respective TFT elements 43 are separated. Only TFT elements 43 to be transferred are selectively stuck with adhesive resin 51, and selectively irradiated with ultraviolet rays 62 from the side of the 2nd substrate 45 to selectively be transferred to a 3rd substrate 47. Thus, the same selected TFT element 43 can be transferred to (m×n) pieces of panel substrates 47 while forming (m×n) times as many as a necessary number of TFT elements 43 on one piece of 2nd substrate 45, so that cost required for forming TFT elements 43 on the 1st substrate can be reduced approximately to become 1/(m×n).

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】この発明は、薄膜トランジスタ(以下、TFTと言う)等のスイッチング素子を有して、ディスプレイに使用される表示用トランジスタアレイパネルに関する。 TECHNICAL FIELD The present invention is a thin film transistor includes a switching element (hereinafter, referred to as TFT) or the like, a display transistor array panel used in the display.

【0002】 [0002]

【従来の技術】従来、コンピュータやテレビジョン装置等のディスプレイに使用される表示用トランジスタアレイパネルの形成方法として、特開平1−38727号公報(以下、従来例1と言う)やUSP5438241(以下、従来例2と言う)に開示されているようなものがある。 Conventionally, as a method for forming the display transistor array panel used in a display such as a computer or television apparatus, JP-A-1-38727 Publication (hereinafter referred to as Conventional Example 1) and USP5438241 (hereinafter, there are those disclosed in the prior referred example 2). この表示用トランジスタアレイパネルの形成方法では、シリコン単結晶基板上に単結晶シリコンのTFTアレイを形成し、これを別のパネル用ガラスあるいは透明有機フィルム基板に転写して表示用トランジスタアレイパネルを得ている。 In this display transistor array panel forming method of a silicon single crystal substrate to form a TFT array of single crystal silicon, to obtain a display transistor array panel which transfer to the a different glass or a transparent organic film substrate panel ing.

【0003】上記従来例1では、単結晶シリコン薄膜にTFTアレイおよび周辺回路を形成し、ガラス基板上にこの単結晶シリコン薄膜の各辺を互いに密着させて複数枚を平面的に敷き詰めて広い画面を得ている。 [0003] The above first conventional example, a single-crystal silicon thin film to form a TFT array and the peripheral circuit, on a glass substrate in close contact with each side of the single-crystal silicon thin film to each other wider spread a plurality in a plane screen the are obtained. また、従来例2では、SOI技術を使用して第1の基板上に酸化物層を介して薄いシリコン単結晶フィルムを形成し、このシリコン単結晶フィルム上にTFTアレイを作成する。 Further, in the conventional example 2, using the SOI technology oxide layer to form a thin single crystal silicon film through to the first substrate, to create a TFT array on the silicon single crystal film. 続いて、このTFTアレイをガラス等の第2の透明絶縁基板上に転写し、上記シリコン単結晶フィルムが形成された上記基板全体を除去することで第1の転写プロセスを完了する。 Subsequently, this TFT array is transferred to the second transparent insulating substrate such as glass, to complete the first transfer process by removing the entire the substrate on which the silicon single crystal film is formed. また、必要な場合には第2の転写プロセスに移行し、第3のディスプレイパネル基板に転写して表示用TFTアレイパネルとしている。 Further, if necessary have a second shifted to the transfer process, the third display panel is transferred to the substrate by the display TFT array panel.

【0004】ここで、上記シリコン単結晶フィルムが形成された基板全体を除去する方法には、図10に示すような基板とディバイスとの間に剥離層を設けエッチングによって剥離層を除去する方法、あるいは、図11に示すような基板全体をエッチバック工程によってエッチ除去する方法がある。 [0004] Here, the method of removing the entire substrate on which the silicon single crystal film is formed, a method of removing the peeling layer by etching is provided a peeling layer between the substrate and the devices as shown in FIG. 10, Alternatively, a method of etching removing the entire substrate as shown in FIG. 11 by an etch-back process.

【0005】上記基板下の剥離層を除去する方法では、 [0005] In the method for removing the peeling layer under the substrate,
先ず、半導体基板1の表面側から剥離層2を介してディバイス3を形成する(図10(a))。 First, through the separation layer 2 from the surface side of the semiconductor substrate 1 to form the devices 3 (Fig. 10 (a)). そして、ディバイス3上にUV(紫外線)キュアエポキシ4を塗布し(図10 Then, by applying a UV (ultraviolet) curing epoxy 4 on devices 3 (Fig. 10
(b))、上記ディバイス3の箇所である残し部6とこの残し部6間で成るエッチング用溝5とを形成する(図10 (B)), to form the etching grooves 5 formed between the remaining portion 6 of the remaining portion 6 Toko is a portion of the devices 3 (Fig. 10
(c))。 (C)). こうして、剥離層2除去用のエッチング溶液導入用アクセスストリート構造を得る。 This gives an etching solution for introducing access street structure for the release layer 2 is removed. 次に、上記UVキュアエポキシ3側から透明基板等で成る支持板7を張り合わせてチャネルを形成する(図10(d))。 Next, a channel by bonding the support plate 7 made of a transparent substrate such as from the UV cure epoxy 3 side (FIG. 10 (d)). そして、このチャネルに、矢印(A)で示すようにエッチング溶液を走らせることによって剥離層2を除去し、半導体基板1からディバイス3をリフトオフする。 Then, to this channel, removing the release layer 2 by running an etching solution as indicated by the arrow (A), it is lifted off the devices 3 from the semiconductor substrate 1.

【0006】また、上記基板全体をエッチ除去する方法では、図11(a)に示すように、ディバイス11が形成されたSOI構造シリコンウエハ12を接着剤13でガラス等の透明絶縁体で成る支持板としての上部基板14 [0006] In the method of etching removes the entire the substrate, as shown in FIG. 11 (a), made of a transparent insulating material such as glass an SOI structure silicon wafers 12 devices 11 are formed in the adhesive 13 support the top of the plate substrate 14
に接着する。 To adhere to. このウエハをKOH(水酸化カリウム)または同等溶液に入れ、酸化物層15との高い選択比20 Put this wafer KOH (potassium hydroxide) or an equivalent solution, high selection ratio between the oxide layer 15 20
0:1を利用して図11(b)に示すようにシリコン基板16をエッチ除去する。 0: The silicon substrate 16 is etched away as shown 1 in FIG. 11 (b) using a. 尚、17は、薄いシリコン単結晶フィルムである。 Incidentally, 17 is a thin single crystal silicon film.

【0007】さらに、上記従来例2には、GeSi(シリ化ゲルマニュウム)を中間エッチストップ層としたシリコン薄膜転写法が開示されている(図12)。 Furthermore, the above conventional example 2, GeSi (silylated germanium) an intermediate etch stop layer and silicon thin film transfer method is disclosed (Fig. 12). このシリコン薄膜転写法においては、図12(a)に示すように、Ge In the silicon thin film transfer method, as shown in FIG. 12 (a), Ge
Si層21を介してディバイス(TFT)22が形成されたシリコンウエハ23を、図12(b)に示すように、エポキシ接着剤24によってガラスまたは他の基板25にマウントする。 The Si layer 21 of the silicon wafer 23 devices (TFT) 22 is formed through, as shown in FIG. 12 (b), mounted on glass or other substrate 25 by an epoxy adhesive 24. そして、KOHに浸漬して、先ずシリコンウエハ23のみに選択エッチを行い、次にGeSi層2 Then, by immersion in KOH, first performed only on the selected etch the silicon wafer 23, then GeSi layer 2
1を別途選択エッチする。 Separately selected etch the 1.

【0008】また、上記従来例2には、上述の基板から支持板への転写と上記支持板からディスプレイパネル基板への転写との2つの転写方法として、UV照射によって剥離する性質を有するUV剥離接着剤をテープの両面に塗布したUV剥離両面テープを上記支持板との接着に使用する方法が開示されている(図13)。 Further, the above conventional example 2, as a two transfer method and a transfer from the transfer and the support plate from the substrate above the support plate to the display panel substrate, UV peeling having a property of peeling by UV irradiation how to use UV peelable double-sided tape adhesive was applied to both surfaces of the tape to the adhesion between the support plate has been disclosed (Fig. 13). この転写方法では、上記支持板からディスプレイパネル基板への転写の場合には、透明支持板26にUV剥離両面テープ27 In this transfer method, in the case of transfer from the support plate to the display panel substrate, UV peeling two-sided tape 27 on the transparent support plate 26
によってディバイス28を転写した後にディバイス28 Device 28 after transferring the devices 28 by
が形成されていた基板を除去して図13(a)の状態にする。 A state shown in FIG. 13 (a) by removing the substrate but was formed. そうした後に、図13(b)に示すように、別のUV After these, as shown in FIG. 13 (b), another UV
剥離両面テープ29にディバイス28を当接させて透明支持板26側からUV照射してUV剥離両面テープ27 Peeling both sides of the devices 28 is brought into contact with the tape 29 with UV radiation from the transparent support plate 26 side UV peelable double-sided tape 27
の接着力を低下させて、ディバイス28をUV剥離両面テープ29に転写する。 The adhesive strength is lowered, and transferring the devices 28 to UV peelable double-sided tape 29. または、図13(b')に示すように、エポキシ樹脂30を塗布した基板31上にディバイス28を当接させて、透明支持板26側からUV照射しつつ転写する。 Alternatively, as shown in FIG. 13 (b '), by contact with devices 28 on the substrate 31 coated with epoxy resin 30 is transferred while UV irradiation from the transparent support plate 26 side.

【0009】さらに、上記従来例2には、基板上に密に形成したディバイスを粗に配置し直す転写方法が開示されている(図14)。 Furthermore, the above conventional example 2, the transfer method is disclosed rearrange devices 60 densely formed on the substrate roughness (Figure 14). 先ず、図14(a)に示すように、接着剤付きの伸縮性基板35にディバイス36を転写した後に、図14(b)に示すように、各ディバイス36毎にディバイス36の間隔と位置とをモニタしながら、伸縮性基板35をX方向へ伸張してX方向のディバイス36 First, as shown in FIG. 14 (a), after transferring the devices 36 to stretch the substrate 35 with adhesive, as shown in FIG. 14 (b), the position and spacing of the devices 36 for each Device 36 while monitoring a stretchable substrate 35 in the X direction extends in the X-direction devices 36
の間隔を所定間隔にする。 The distance to a predetermined distance. 次に、図14(c)に示すように、伸縮性基板35をY方向へ伸張してY方向のディバイス36の間隔を所定間隔にする。 Next, as shown in FIG. 14 (c), the stretchable substrate 35 is stretched in the Y direction a distance Y direction devices 36 at predetermined intervals. そうした後、ディバイス36をディスプレイパネル基板(図示せず)に転写する。 After doing so, to transfer the devices 36 on the display panel substrate (not shown). 他の方法として、テープ上のディバイスチップを回転ドラム上の他のテープ上に転写することによって、機械的にディバイス間隔を変換させる方法も開示されている。 Alternatively, by transferring the devices chips on the tape on the other tape on a rotating drum, it is also disclosed a method for converting mechanical devices intervals.

【0010】 [0010]

【発明が解決しようとする課題】しかしながら、上記従来の表示用トランジスタアレイパネルの形成方法には、 [SUMMARY OF THE INVENTION However, the above conventional method of forming a display transistor array panel,
以下のような問題がある。 There is a problem such as the following.

【0011】すなわち、従来例1では、パネルの高輝度化,高精細化,広視野角化の点で問題がある。 [0011] That is, in the conventional example 1, the high luminance of the panel, high resolution, there is a problem in terms of wide viewing angle. すなわち、 That is,
能動素子(TFT)および受動素子(画素電極,補助電極, Active elements (TFT) and a passive element (pixel electrode, auxiliary electrode,
電極配線等)を同時に形成した複数枚の単結晶シリコン薄膜を、ガラス基板上に敷き詰めている。 A plurality of single-crystal silicon thin film to form an electrode wiring, etc.) At the same time, is laid on a glass substrate. ところが、従来の張り合わせ材料や精度では、ダイシング加工精度や接着加工精度の点で張り合わせ箇所の余裕代を目的とする素子ピッチの半分にできない。 However, in the conventional bonding materials and accuracy, it can not be half the element pitch for the purpose of allowance point bonding in terms of dicing accuracy and bonding machining accuracy. そのために、各単結晶シリコン薄膜のつなぎ目部における透過光量とつなぎ目以外の箇所における透過光量とが異なることになり、例えば視野角によって表示むら等が発生する。 Therefore, it will be the amount of transmitted light in the portions other than the transmitted light amount and the seams in the joint portion of the monocrystalline silicon thin film is different, for example, display unevenness occurs due to the viewing angle. したがって、パネルの輝度,精細度,視野角を確保するのに技術的に困難なのである。 Accordingly, the panel brightness, definition, is the technically difficult to ensure the viewing angle.

【0012】また、従来例1および従来例2に開示された単結晶シリコン薄膜に形成されたTFTアレイをパネル用基板に転写する方法は、単結晶シリコン薄膜上のT Further, a method of transferring a TFT array formed on a single crystal silicon thin film disclosed in prior art 1 and prior art example 2 in panel substrate, T on the single crystal silicon thin film
FT数とパネル用基板上のTFT数とが1:1の関係に在り、パネル用基板に直接TFTアレイを作り込む方法に比べて工数が転写プロセス分だけ増加することになり、コストがアップするという問題がある。 And the FT number and TFT number of panel substrates 1: 1 relationship, steps will be increases by transfer process amount in comparison with the method of directly fabricate a TFT array panel substrate, the cost is up there is a problem in that.

【0013】また、従来例2に開示されている基板上に密に形成したディバイスを粗に配置し直す転写方法は、 [0013] The transfer method rearrange devices 60 densely formed on the substrate disclosed in prior art 2 in coarse,
伸縮性基板の伸長時の不動点(支点)がディバイスチップの接着面のどの位置になるかによって、ディバイス位置が最小でチップサイズ(≧20μm)だけずれるという本質的な問題を抱えている。 Depending elongation at fixed points of the stretchable substrate (supporting point) is in any position of the bonding surface of the devices chips, devices position is having intrinsic problem that deviates by chip size (≧ 20 [mu] m) at the minimum. そのために、ディバイスチップ毎の精密位置制御が不可欠になる。 Therefore, precise position control for each devices chip becomes indispensable. したがって、少なくとも1μm程度の位置合わせ精度が必要な高精細TF Thus, high-definition TF require at least 1μm about positioning accuracy
Tアレイパネルの形成には、TFTディバイスチップ毎の位置計測と制御を含む位置合わせに多大な時間を要する。 The formation of the T array panel, time-consuming alignment including positional measurement and control for each TFT devices chip. さらに、熱膨張係数の大きな樹脂フィルムへの転写の場合には、位置決め前後の温度/応力変動によって位置合わせ精度が損なわれ易い。 Furthermore, in the case of transfer to a large resin film of the thermal expansion coefficient is likely alignment accuracy is impaired by temperature / stress variation before and after the positioning. 以上の理由から、量産技術として採用することには極めて大きな問題がある。 For these reasons, the adoption as mass production technology there is a very large problem.

【0014】そこで、この発明の目的は、製造コストの大幅な削減を可能にする表示用トランジスタアレイパネルの形成方法を提供することにある。 [0014] Accordingly, an object of the present invention is to provide a method of forming a display transistor array panel that allows a significant reduction in manufacturing cost.

【0015】 [0015]

【課題を解決するための手段】上記目的を達成するため、請求項1に係る発明の表示用トランジスタアレイパネルの形成方法は、基板上に,画素の一方向への配列ピッチdxを2以上の自然数mで除したdx/mのピッチ,および,他方向への配列ピッチdyを2以上の自然数nで除したdy/nのピッチで素子を設ける工程と、上記基板上に設けられた素子のうち,上記画素の配列ピッチdx,dy To achieve the above object, according to an aspect of method for forming the display transistor array panel according to the invention of claim 1, on a substrate, the array pitch dx in one direction of the pixel 2 or more pitch dx / m obtained by dividing the natural number m, and a step of providing an element in an array pitch dy two or more pitch divided by dy / n a natural number n in the other direction, the element provided on the substrate of the arrangement pitch dx of the pixel, dy
に対応する素子のみを選択的に他の基板に転写する工程を備えたことを特徴としている。 It is characterized by comprising a step of transferring only selectively other substrate corresponding elements.

【0016】上記構成によれば、最終的に表示用トランジスタアレイに形成される画素数の(m×n)倍の素子が基板上に設けられている。 According to the above arrangement, finally displayed transistor array number of pixels that are formed in the (m × n) times the element is provided on the substrate. したがって、上記素子が設けられた1枚の基板から(m×n)枚の表示用トランジスタアレイパネルを形成することが可能となり、上記素子を形成する場合のコストが1/(m×n)に低減される。 Therefore, it is possible to form from one substrate to the elements are provided with (m × n) Like the display transistor array panel, the cost in the case of forming the element to 1 / (m × n) It is reduced.

【0017】さらに、上記構成によれば、上記素子が設けられた1枚の基板から他の基板上への素子の選択転写を(m×n)回繰り返すことによって、上記素子の一方向への配列ピッチがdxであり、他方向への配列ピッチがdyであると共に、上記素子が形成設けられていた基板の大きさの(m×n)倍の大きさの上記他の基板が得られる。 Furthermore, according to the arrangement, by repeating the selection transfer elements from one substrate to the elements are provided to other substrates (m × n) times, in one direction of the element arrangement pitch is dx, the arrangement pitch in the other direction, together with a dy, the other substrate of the element substrate provided form the size of (m × n) times the size is obtained. こうして、上記素子の形成に要する材料費が低減される。 Thus, material costs required for forming the element is reduced.

【0018】また、請求項2に係る発明の表示用トランジスタアレイパネルの形成方法は、第1の基板上に,画素の一方向への配列ピッチdxを2以上の自然数mで除したdx/mのピッチ,および,他方向への配列ピッチdy Further, the method of forming the display transistor array panel according to the invention of claim 2, the first substrate, dx / m to the arrangement pitch dx divided by a natural number of 2 or more m in one direction of the pixel arrangement pitch dy in the pitch, and the other direction
を2以上の自然数nで除したdy/nのピッチで素子を形成する工程と、上記第1の基板上に形成された素子を第2の基板上に全体転写する工程と、上記第1の基板を除去して上記素子を上記第2の基板上に孤立配列させる工程と、記第2の基板上に転写された素子のうち,上記画素の配列ピッチdx,dyに対応する素子のみを選択的に表示用トランジスタアレイ用の第3の基板に転写する工程を備えたことを特徴としている。 And forming a device at a pitch of dividing the dy / n in a natural number of 2 or more n, a step of whole transferring the first element formed on the substrate on the second substrate, the first select a step to isolate arranging the element on said second substrate the substrate is removed, among the elements that are transferred to the serial second substrate, only the elements corresponding to the arrangement pitch dx, dy of the pixel It is characterized by comprising a step of transferring to a third substrate for a display transistor array.

【0019】上記構成によれば、最終的に表示用トランジスタアレイ用の第3の基板上に形成される画素数の According to the above arrangement, the final display transistor array of the third number of pixels formed on a substrate of
(m×n)倍の素子が、第1の基板上に形成されている。 (M × n) times the element is formed on the first substrate.
したがって、上記素子が形成された1枚の第1の基板から(m×n)枚の第3の基板を形成することが可能となり、上記第1の基板上への素子形成コストが1/(m× Therefore, it is possible to form the first substrate 1 Like the element is formed of (m × n) pieces of the third substrate, the element formation cost 1 / to the first substrate ( m ×
n)に低減される。 Is reduced to n).

【0020】また、請求項3に係る発明は、請求項1あるいは請求項2に係る発明の表示用トランジスタアレイパネルの形成方法において、上記素子が選択転写される基板上の位置には、上記素子が嵌合される凹部が形成されていることを特徴としている。 [0020] The invention according to claim 3, in the formation method of a display transistor array panel of the invention according to claim 1 or claim 2, the position on the substrate where the element is selected transferred, the elements It is characterized in that the recess but is fitted is formed.

【0021】上記構成によれば、上記素子が選択転写される基板上の位置には凹部が形成されているので、上記凹部に接着剤層を形成することによって、上記素子の選択転写が更に容易に行われる。 According to the above arrangement, since the position on the substrate where the element is selected transfer is a recess, by forming an adhesive layer on the recess, select transfer of the device is more easily It is carried out.

【0022】また、請求項4に係る発明は、請求項1あるいは請求項2に係る発明の表示用トランジスタアレイパネルの形成方法において、上記素子が選択転写される基板上の位置には、接着剤層が選択的に形成されていることを特徴としている。 [0022] The invention according to claim 4, in the formation method of a display transistor array panel of the invention according to claim 1 or claim 2, the position on the substrate where the element is selected transferred, adhesive layer is characterized by being selectively formed.

【0023】上記構成によれば、上記素子が選択転写される基板上の位置に接着剤層が選択的に形成されているので、上記素子の選択転写が更に容易に行われる。 According to the above arrangement, since the adhesive layer at a position on the substrate where the element is selected transfer is selectively formed, selectively transfer of the device is more easily performed.

【0024】また、請求項5に係る発明は、請求項1あるいは請求項2に係る発明の表示用トランジスタアレイパネルの形成方法において、上記素子は順スタガ型のT [0024] The invention according to claim 5, in the formation method of a display transistor array panel of the invention according to claim 1 or claim 2, the above elements of staggered T
FTであることを特徴としている。 It is characterized in that it is a FT.

【0025】上記構成によれば、基板上への順スタガ型TFTの形成コストが1/(m×n)に低減される。 According to the above arrangement, formation cost of staggered TFT on the substrate is reduced to 1 / (m × n).

【0026】また、請求項6に係る発明は、請求項1あるいは請求項2に係る発明の表示用トランジスタアレイパネルの形成方法において、上記素子は逆スタガ型のT [0026] The invention according to claim 6, in the formation method of a display transistor array panel of the invention according to claim 1 or claim 2, the above elements of the inverted staggered T
FTであることを特徴としている。 It is characterized in that it is a FT.

【0027】上記構成によれば、上記基板上への逆スタガ型TFTの形成コストが1/(m×n)に低減される。 According to the above arrangement, formation cost of a reverse stagger TFT onto the substrate is reduced to 1 / (m × n).

【0028】また、請求項7に係る発明は、請求項1あるいは請求項2に係る発明の表示用トランジスタアレイパネルの形成方法において、上記素子はコプレーナ型のTFTであることを特徴としている。 [0028] The invention according to claim 7, in the formation method of a display transistor array panel of the invention according to claim 1 or claim 2, the above elements are characterized by a coplanar type of the TFT.

【0029】上記構成によれば、上記基板上へのコプレーナ型TFTの形成コストが1/(m×n)に低減される。 According to the above arrangement, formation cost of the coplanar type TFT onto the substrate is reduced to 1 / (m × n).

【0030】また、請求項8に係る発明は、請求項5乃至請求項7の何れか一つに係る発明の表示用トランジスタアレイパネルの形成方法において、上記素子は配線交差部をも含んでいることを特徴としている。 [0030] The invention according to claim 8, in the formation method of a display transistor array panel of the invention according to any one of claims 5 to 7, the above-mentioned element contains also a wiring intersection portion it is characterized in that.

【0031】上記構成によれば、上記基板上への配線交差部をも含むTFTの形成コストが1/(m×n)に低減される。 According to the above arrangement, formation cost of TFT also includes a wiring intersection portion onto the substrate is reduced to 1 / (m × n).

【0032】また、請求項9に係る発明は、請求項2に係る発明の表示用トランジスタアレイパネルの形成方法において、上記第1の基板はシリコン基板であることを特徴としている。 [0032] The invention according to claim 9, in the formation method of a display transistor array panel according to the invention of claim 2 is characterized in that said first substrate is a silicon substrate.

【0033】上記構成によれば、上記第1の基板はシリコン基板であるから上記素子を高密度に形成できる。 According to the above arrangement, the first substrate can be formed at high density the device from a silicon substrate. したがって、上記自然数m,nを容易に大きくすることが可能となり、上記第1の基板上への素子形成コストが大幅に低減される。 Therefore, the natural number m, it is possible to easily increase the n, elements forming cost to the first substrate is greatly reduced.

【0034】また、請求項10に係る発明は、請求項2 [0034] The invention according to claim 10, claim 2
に係る発明の表示用トランジスタアレイパネルの形成方法において、上記第1の基板はガラス基板であることを特徴としている。 A method of forming a display transistor array panel of the invention according to the above first substrate is characterized by a glass substrate.

【0035】上記構成によれば、上記第1の基板はガラス基板であるから、大型の第1の基板の形成が可能となり、大型の表示用トランジスタアレイパネルが容易に形成される。 [0035] According to the above configuration, the first substrate from a glass substrate, formed of a first substrate of large is possible, large display transistor array panel is easily formed.

【0036】また、請求項11に係る発明は、請求項2 [0036] The invention according to claim 11, claim 2
に係る発明の表示用トランジスタアレイパネルの形成方法において、上記第1の基板上の素子の上記第2の基板上への全体転写は,光によって接着力が低下する接着剤によって行い、上記第2の基板上の素子の上記第3の基板上への選択転写は,上記第2の基板の裏面から上記画素の配列ピッチdx,dyに対応する素子の箇所への光照射によって転写の対象となる素子のみを選択的に上記第2の基板から剥離することによって行うことを特徴としている。 A method of forming a display transistor array panel according to the invention of the entire transfer to the first element of the second substrate on the substrate is carried out by an adhesive bond strength by light is reduced, the second selection transferred to the third substrate of the devices on the substrate are subject to transfer by light irradiation from the back surface of the second substrate to the portion of the element corresponding to the arrangement pitch dx, dy of the pixel of It is characterized in that performed by separating an element selectively only from the second substrate.

【0037】上記構成によれば、光によって接着力が低下する接着剤の塗布および上記第2の基板の裏面からの光の選択照射という簡単な方法によって、上記第2の基板上の素子の上記第3の基板上への選択転写が行われる。 According to the above configuration, by a simple method that the light of the selected irradiation from the back surface of the coating and the second substrate of the adhesive bond strength is reduced by light, said element on said second substrate selection transferred to the third substrate is conducted.

【0038】また、請求項12に係る発明は、請求項2 [0038] The invention according to claim 12, claim 2
に係る発明の表示用トランジスタアレイパネルの形成方法において、上記第1の基板上にフッ化水素酸に対して耐性を有する透明絶縁膜を形成し、この透明絶縁膜上に上記素子を形成することを特徴としている。 A method of forming a display transistor array panel according to the invention of, the transparent insulating film having resistance to hydrofluoric acid is formed on the first substrate, forming the element on the transparent insulating film It is characterized in.

【0039】上記構成によれば、上記第1の基板の除去に際して、エッチャントとしてフッ化水素酸が使用された場合に、フッ化水素酸に対して耐性を有する透明絶縁膜の存在によって上記素子が保護される。 According to the above arrangement, when the removal of the first substrate, when the hydrofluoric acid is used as an etchant, the device is the presence of the transparent insulating film having resistance to hydrofluoric acid It is protected.

【0040】また、請求項13に係る発明は、請求項1 [0040] The invention according to claim 13, claim 1
2に係る発明の表示用トランジスタアレイパネルの形成方法において、上記フッ化水素酸に対して耐性を有する透明絶縁膜は、酸化タンタル膜あるいはダイヤモンド膜の何れ一方であることを特徴としている。 A method of forming a display transistor array panel of the invention according to 2, a transparent insulating film having a resistance to the hydrofluoric acid is characterized in that it is one any of the tantalum oxide film or a diamond film.

【0041】上記構成によれば、上記第1の基板除去用のエッチャントとしてフッ化水素酸が使用された場合に、酸化タンタル膜あるいはダイヤモンド膜の何れ一方の存在によって上記素子が確実に保護される。 [0041] According to the above configuration, when the hydrofluoric acid as an etchant for the first substrate removed is used, the element is reliably protected by the presence of any one of the tantalum oxide film or a diamond film .

【0042】 [0042]

【発明の実施の形態】以下、この発明を図示の実施の形態により詳細に説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, will be explained in detail by embodiments thereof illustrated in the accompanying drawings.

【0043】<第1実施の形態>図1および図2は、本実施の形態の表示用トランジスタアレイパネルの形成方法における手順を示す図である。 [0043] <First Embodiment> Figures 1 and 2 are diagrams showing the procedure in the method of forming a display transistor array panel of this embodiment. 本実施の形態においては、第1の基板としてシリコン(Si)基板を用いている。 In the present embodiment uses a silicon (Si) substrate as the first substrate.

【0044】図1(a)に示すように、上記第1の基板としてのSi基板41上に透明絶縁膜としてSi酸化膜42 As shown in FIG. 1 (a), Si oxide film as the transparent insulation film on the Si substrate 41 serving as the first substrate 42
を形成した後、i線スパッタを用いたフォトプロセスを含む公知の素子形成プロセスを行って、TFT素子43 After forming the, by performing a known element forming process including a photo process using the i-line sputtering, TFT elements 43
を素子分離溝44を隔てて所定のピッチで形成する。 The spaced isolation trenches 44 are formed at a predetermined pitch. ここで、上記ピッチは、目的とする表示用トランジスタアレイパネルの画素ドットの配列ピッチdx,dyを、「2」 Here, the pitch, the arrangement pitch dx of pixel dots of the display transistor array panel for the purpose, the dy, "2"
以上の自然数m,nで除した値dx/m,dy/nである。 Or larger natural number m, the value dx / m divided by n, is dy / n. また、形成するTFT素子43は、例えばTFTと周辺電極配線の一部を含むものであるが、画素電極は含まない。 Further, TFT elements 43 to be formed, for example, is intended to include a portion of the TFT and the peripheral electrode wiring, not including the pixel electrode. 尚、形成するTFTの構造については後に詳述する。 Incidentally, the structure of the formed TFT will be described in detail later.

【0045】次に、図1(b)に示すように、上記TFT Next, as shown in FIG. 1 (b), the TFT
素子43側にUV剥離樹脂46を塗布し、第2の基板である光透過性基板としてのガラス基板45を張り付ける。 Applying a UV peelable resin 46 to the element 43 side, pasting glass substrate 45 as a light-transmitting substrate is a second substrate. ここで、UV剥離樹脂46としては、シリコン(メタ)アクリレート添加のアクリル系樹脂や紫外線照射で接着力が低下するUV硬化型粘着剤等を用いる。 Here, the UV releasable resin 46, using a UV curable adhesive such as a silicon (meth) adhesive strength acrylic resin or ultraviolet irradiation acrylate additive is reduced. 次に、 next,
図1(c)に示すように、Si基板(第1の基板)41をKO As shown in FIG. 1 (c), the Si substrate (first substrate) 41 KO
Hでエッチング除去した後に、TFT素子分離溝44の箇所のSi酸化膜42に対してTFT素子分離エッチングを行って個々のTFT素子43を孤立した状態にする。 After etching is removed by H, into an isolated state in the individual TFT device 43 performs TFT isolation etching relative to the Si oxide film 42 of the portion of the TFT element isolation groove 44.

【0046】次に、図1(d)に示すように、TFTパネル用の第3の基板であるガラス基板47に接着樹脂48 Next, as shown in FIG. 1 (d), the adhesive resin 48 to the glass substrate 47 which is a third substrate for TFT panels
を塗布したものを、アライメントを行いつつガラス基板 Glass substrate that was applied, while performing the alignment of the
(第2の基板)45に近接させる。 It is closer to the (second substrate) 45. そして、フォトマスク49を用いて、接着樹脂48における転写の対象となる Then, using a photomask 49, as a target of transfer in the adhesive resin 48
(後に画素を構成する)TFT素子43の箇所に位置する部分を紫外線50を照射して半硬化させて接着性を高め、その半硬化部分51を転写対象のTFT素子43に押し付けてガラス基板(第3の基板)47を貼り合わせる。 (After composing the pixel) a portion located at a position of the TFT element 43 is semi-cured by irradiation with ultraviolet rays 50 adhesion elevated, glass substrates and the semi-hardened portion 51 is pressed against the TFT element 43 to be transcribed ( bonding the third substrate) 47. 尚、接着樹脂48としては、例えばアクリレート系のUV硬化樹脂やUV硬化エポキシ系樹脂等を用いる。 As the adhesive resin 48, for example, a acrylate-based UV curable resin or UV curable epoxy resin, or the like.

【0047】また、上記第3の基板を貼り合わせる方法として、図2(d')に示す方法を用いても差し支えない。 Further, as a method of bonding the third substrate, no problem even using the method shown in FIG. 2 (d ').
すなわち、第3の基板55における転写対象のTFT素子43の箇所に位置する部分を、例えばCF 4やCHF 3 That is, a portion located at a position of the TFT element 43 to be transcribed in the third substrate 55, for example, CF 4 and CHF 3
を用いたドライエッチ(RIE)によって、TFT素子4 By dry etching (RIE) using, TFT elements 4
3のチップが入るサイズの凹部56を形成し、この凹部56のみに予め接着樹脂57を塗布しておく。 3 of a recess 56 sized chip enters, advance the adhesive resin 57 is applied only to the recess 56. そして、 And,
凹部56に転写対象のTFT素子43を嵌合して第3の基板55を貼り合わせるのである。 Is for laminating a third substrate 55 is fitted a TFT element 43 of the transfer target in the recess 56.

【0048】次に、図2(e)に示すように、フォトマスク61を用いて、ガラス基板45(第2の基板:光透過性基板)側から、UV剥離樹脂46における転写対象のTFT素子43の箇所の部分に紫外線62を選択的に照射して、UV剥離樹脂46の接着力を低下させてTFT Next, as shown in FIG. 2 (e), using a photomask 61, a glass substrate 45 (second substrate: a light transmissive substrate) from the side, of the transfer target in the UV peelable resin 46 TFT element UV 62 in the portion of part of the 43 selectively irradiated with, to reduce the adhesive strength of the UV releasable resin 46 TFT
素子43との密着性を低減させる。 Reducing the adhesion between the element 43.

【0049】以上の処理によって、上記転写対象のTF [0049] By the above processing, of the transfer target TF
T素子43は隣接しているTFT素子43とは孤立しており、ガラス基板(第2の基板)45との間のUV剥離樹脂46は接着力が低下している。 T element 43 is isolated from the TFT elements 43 that are adjacent, UV peeling resin 46 between the glass substrate (second substrate) 45 adhesion is reduced. したがって、図2(f) Accordingly, FIG. 2 (f)
に示すように、パネル用のガラス基板(第3の基板)47 As shown, the glass substrate (the third substrate) for the panel 47
に転写対象のTFT素子43のみが移し取られる(転写接着)される。 Only TFT element 43 of the transfer object is taken and transferred (transfer adhesive) on. そして、未露光のTFT素子43は、ガラス基板(第3の基板)47に転写接着されない。 Then, TFT elements 43 of unexposed, not transferred adhered to the glass substrate (third substrate) 47. 尚、未露光の接着樹脂48は選択転写後に除去しておく。 The adhesive resin 48 of unexposed keep removed after selection transcription.

【0050】最後に、受動素子部形成プロセスを行う。 [0050] Finally, perform a passive element portion forming process.
この受動素子部形成プロセスでは、図3に示すように、 In this passive element portion forming process, as shown in FIG. 3,
上記パネル用のガラス基板(第3の基板)47上に画素ドットの配列ピッチdx,dyで転写接着されたTFT素子43に、データ信号線65に接続するためのソース電極配線66,走査信号線67に接続するためのゲート電極配線68およびドレイン電極配線69を配線する。 Arrangement pitch dx of pixel dots on the glass substrate (third substrate) 47 for the panel, the TFT element 43, which is transferred adhered by dy, the source electrode wiring 66 for connecting to the data signal lines 65, the scanning signal lines connecting the gate electrode wiring 68 and the drain electrode wiring 69 for connecting to 67. さらに、ドレイン電極配線69に接続される液晶駆動用の画素電極70を形成する。 Further, a pixel electrode 70 for driving liquid crystal which is connected to the drain electrode wiring 69. その場合の配線間絶縁膜として、例えばポリイミド膜を用いる。 As inter-wiring dielectric film in this case, for example, a polyimide film. そして、上述の図1 Then, the above-mentioned FIG. 1
(c)におけるTFT素子分離エッチング等の際にTFT TFT in such TFT element isolation etching in (c)
素子43を保護するためにTFT素子43を覆って形成されている例えばSi酸化膜(図示せず)に、電極接続用のコンタクトホールを穴あけエッチングで形成する。 For example Si oxide film is formed to cover the TFT element 43 (not shown) in order to protect the element 43, to form contact holes for electrode connections drilling etching. そして、ガラス基板(第3の基板)47上のデータ信号線6 Then, the glass substrate (the third substrate) on 47 of the data signal lines 6
5や走査信号線67とTFT素子43の電極との接続等を行う。 For 5 and connection between the electrode of the scanning signal line 67 and the TFT element 43 or the like.

【0051】こうして、図4に示すような表示用トランジスタアレイパネルが形成される。 [0051] Thus, the display transistor array panel shown in FIG. 4 is formed. 尚、71はカラーフィルタガラス基板であり、72はRGBのカラーフィルタである。 Incidentally, 71 is a color filter glass substrate, 72 is an RGB color filter. また、上記配線65〜69および画素電極7 Further, the wiring 65 to 69 and the pixel electrode 7
0は、TFT素子43が転写接着される前に、予めガラス基板(第3の基板)47上に形成しておいても構わない。 0 Before the TFT element 43 is transferred adhered, may be previously formed on the pre-glass substrate (third substrate) 47.

【0052】従来より、表示用トランジスタアレイパネルに採用されているTFT素子の構造として、順スタガ構造,逆スタガ構造およびコプレーナ構造の3種類がある。 [0052] Conventionally, as a structure of the TFT elements are employed in the display transistor array panel, staggered structure, there are three types of reverse staggered structure and coplanar structures. 図5は順スタガTFTの構造の一例を示し、図5 Figure 5 shows an example of a structure of a staggered TFT, FIG. 5
(a)は断面図であり、図5(b)は平面図である。 (A) is a sectional view, FIG. 5 (b) is a plan view. 順スタガTFTでは、ゲート電極81が、ソース電極82下のオーミック・コンタクト層83とドレイン電極84下のオーミック・コンタクト層85とに接続するチャネル層8 In a staggered TFT, the channel layer a gate electrode 81 is connected to the ohmic contact layer 83 and the drain electrode 84 ohmic contact layer 85 under the lower source electrode 82 8
6の上側に、ゲート絶縁膜87を介して形成されている。 The upper 6, is formed via a gate insulating film 87. 尚、89は、上記選択転写後の配線プロセスにおいてSi酸化膜88に形成されるゲート電極71に対するコンタクトホールである。 Incidentally, 89 is a contact hole for the gate electrode 71 formed on the Si oxide film 88 in the wiring process after the selective transcription. 同様に、90はソース電極8 Similarly, 90 denotes a source electrode 8
2に対するコンタクトホールであり、91はドレイン電極84に対するコンタクトホールである。 A contact hole for 2, 91 is a contact hole for the drain electrode 84.

【0053】また、図6は、上記逆スタガTFTの構造の一例の断面図を示す。 [0053] Also, FIG. 6 shows a cross-sectional view of an example of the structure of the inverted staggered TFT. 逆スタガTFTでは、ゲート電極101が、ソース電極102とドレイン電極103とに接続するチャネル層104の下側に、ゲート絶縁膜1 In inverted staggered TFT, a gate electrode 101, the lower side of the channel layer 104 to be connected to the source electrode 102 and the drain electrode 103, the gate insulating film 1
05及び金属酸化膜106を介して形成されている。 05 and are formed through the metal oxide film 106.
尚、107,108はオーミック・コンタクト層であり、 In addition, 107 and 108 is an ohmic contact layer,
110はSi酸化膜109に形成されたソース電極10 110 The source electrode 10 is formed on the Si oxide film 109
2に対するコンタクトホールであり、111はドレイン電極103に対するコンタクトホールである。 A contact hole for 2, 111 is a contact hole for the drain electrode 103.

【0054】また、図7は、上記コプレーナTFTの構造の断面図を示す。 [0054] Further, FIG. 7 shows a cross-sectional view of the structure of the coplanar TFT. コプレーナTFTでは、ゲート電極121が、ソース電極122とドレイン電極123とを接続するオーミック・コンタクト層124の中間部に形成されるチャネル層125の上側に、ゲート絶縁膜12 In the coplanar TFT, the gate electrode 121, the upper side of the channel layer 125 is formed in an intermediate portion of the ohmic contact layer 124 for connecting the source electrode 122 and the drain electrode 123, the gate insulating film 12
6を介して形成されている。 It is formed through 6. 尚、128はSi酸化膜1 Incidentally, 128 Si oxide film 1
27に形成されたソース電極122に対するコンタクトホールであり、129はドレイン電極123に対するコンタクトホールである。 A contact hole for the source electrode 122 formed on the 27, 129 denotes a contact hole for the drain electrode 123.

【0055】上記順スタガTFT,逆スタガTFTおよびコプレーナTFTの何れの場合にも、ガラス基板(第2の基板)45への全体転写後におけるNaOH(水酸化ナトリウム)あるいはKOHをエッチャントとしたSi基板(第1の基板)41への選択エッチングを行う際に、上記エッチャントに耐性のあるSi酸化膜42でTFTが保護される構成になっている。 [0055] The order-staggered TFT, in each case inverted staggered TFT and coplanar TFT, Si substrate was etchant NaOH (sodium hydroxide) or KOH after total transfer to the glass substrate (second substrate) 45 when performing selective etching to (first substrate) 41 has a structure in which TFT is protected by the Si oxide film 42 is resistant to the etchant. したがって、何れの構成の場合も、本実施の形態の表示用トランジスタアレイパネルの形成方法が適用可能である。 Thus, in either case of the configuration, the method of forming the display transistor array panel of this embodiment can be applied. 尚、上記保護膜42 Incidentally, the protective film 42
は、Si酸化膜に限定されるものではなく、第1の基板に対する選択エッチング時に使用されるエッチャントに対して耐性を有する膜であればよい。 Is not intended to be limited to Si oxide film may be a film having resistance to etchant used during the selective etching for the first substrate. 例えば、第1の基板がガラス基板である場合には、エッチャントとしてのフッ化水素酸に対して耐性を有する酸化タンタル膜あるいはダイアモンド膜を上記保護膜として上記ガラス基板とTFTとの間に形成すればよい。 For example, if the first substrate is a glass substrate, a tantalum oxide film or a diamond film having resistance to hydrofluoric acid as the etchant be formed between the glass substrate and the TFT as the protective film Bayoi. 尚、上記保護膜は、 Incidentally, the protective film,
上記第1の基板とTFTとの間のみならず、図5〜図7 Not only between the first substrate and the TFT, 5-7
に示すように、TFTの表面および側面にも形成することが望ましい。 As shown, it is desirable to be formed on the surface and side of the TFT.

【0056】尚、図8は、図6に示す逆スタガTFTにおけるソース電極102に接続されたソース電極配線1 [0056] Incidentally, FIG. 8, a source electrode wiring 1 that is connected to the source electrode 102 in the reverse stagger TFT shown in FIG. 6
15とゲート電極配線116との交差部115の断面図である。 It is a cross-sectional view of the intersection 115 between the 15 and the gate electrode wiring 116. このようなソース電極配線115とゲート電極配線116との交差部115も、TFT素子43に含めて、第3の基板47上に選択転写することが可能である。 Intersection 115 with such a source electrode wiring 115 and the gate electrode wiring 116 is also included in the TFT element 43, it is possible to select transferred onto a third substrate 47.

【0057】上述のように、本実施の形態においては、 [0057] As described above, in this embodiment,
Si基板で成る第1の基板41上にTFT素子43を素子分離溝44を隔ててピッチdx/m,dy/nで形成する。 Pitch dx / m at a device isolation trench 44 a TFT element 43 on the first substrate 41 made of Si substrate, formed with dy / n. ここで、dx,dyは画素ドットの配列ピッチであり、m,nは「2」以上の自然数である。 Here, dx, dy is an array pitch of the pixel dots, m, n is a natural number greater than or equal to "2". そして、TFT Then, TFT
素子43側にUV剥離樹脂46で第2の基板45を張り付けた後、第1の基板41をエッチング除去し、TFT After pasting the second substrate 45 in the UV peelable resin 46 to the element 43 side, the first substrate 41 is removed by etching, TFT
素子分離エッチングを行って各TFT素子43を分離させる。 To separate the TFT elements 43 by performing an isolation etching. そして、第3の基板47に接着樹脂48で転写対象のTFT素子43のみを選択的に接着させ、第2の基板45側から転写対象のTFT素子43の箇所に紫外線62を選択的に照射してUV剥離樹脂46の接着力を低下させて、転写対象の(つまり、画素を構成する)TFT Then, the adhesive resin 48 only TFT element 43 of the transfer object selectively adhered to the ultraviolet 62 selectively irradiating the portion of the TFT element 43 to be transcribed from the second substrate 45 side in the third substrate 47 lowering the adhesion of the UV peelable resin 46 Te, the transfer object (i.e., constituting pixels) TFT
素子43のみを第3の基板47に選択転写するのである。 Only element 43 is to select transferred to the third substrate 47.

【0058】したがって、上記第2の基板45上のTF [0058] Thus, TF on the second substrate 45
T素子43のピッチdx/m,dy/nの第3の基板47上でのピッチdx,dyへの拡大を、従来例2の如く伸縮性基板を用いる転写方法に比して正確に行うことができる。 Pitch dx / m of T elements 43, pitch dx in on the third substrate 47 of dy / n, the expansion to dy, accurately performed that compared the transfer method using a stretchable substrate as in the conventional example 2 can. したがって、1枚の第2の基板45を用いて、この第2の基板45から第3の基板(パネル用基板)47への選択転写を、第2の基板45をx方向へdx/mあるいはy方向へdy/nだけ移動させながら(m×n)枚の第3の基板47に対して行うことによって、第1の基板41を1枚作成すれば、(m×n)枚のパネル用基板47に対して同一の選択転写を行うことができる。 Thus, by using the second substrate 45 of one, a selection transfer from the second substrate 45 to the third substrate (panel substrate) 47, dx / m or to the second substrate 45 x-direction by performing relative while moving the y direction by dy / n (m × n) pieces of third substrate 47, the first substrate 41 by creating one, (m × n) sheets for the panels it is possible to perform the same selection transfer to the substrate 47. すなわち、本実施の形態によれば、第1の基板41上にTFT素子43 That is, according to this embodiment, TFT elements on the first substrate 41 43
を形成するコストを概略1/(m×n)にできる。 The cost of forming can be schematically 1 / (m × n).

【0059】このように、本実施の形態によれば、表示用トランジスタアレイパネルとして必要な画素数のm, [0059] Thus, according to this embodiment, the number of required pixel as the display transistor array panel m,
n倍のTFT素子を第1の基板41上に形成することが可能となる。 N times of the TFT element can be formed on the first substrate 41. したがって、必要画素数と第1の基板上のTFT素子数とが同数の従来の表示用トランジスタアレイパネルの形成方法に比して、第1の基板41に形成するTFT素子密度を10倍〜100倍にできる。 Therefore, in comparison required number of pixels and the number of TFT elements on the first substrate to the method of forming the same number of conventional display transistor array panel, 10 times the TFT element density to be formed on the first substrate 41 to 100 It can be doubled. したがって、表示用トランジスタアレイパネル製造設備におけるイニシャルコストの約30%を占める成膜工程設備および約26%を占めるフォト工程設備のスループットを、実質的に10倍〜100倍程度向上させることができる。 Therefore, it is possible throughput photo process equipment occupying the deposition process equipment and about 26% account for about 30% of the initial cost of the display transistor array panel manufacturing equipment, substantially improve about 10 to 100 times. また、TFT素子43の形成に要する材料費も1 Also, material costs required for forming the TFT elements 43 1
/10〜1/100に低減できる。 It can be reduced to / 10-1 / 100. 結果として、表示用トランジスタアレイパネルの製造コストの大幅な削減が可能となるのである。 As a result, it become possible to greatly reduce the manufacturing cost of the display transistor array panel.

【0060】ところで、上記第1の基板41としてSi By the way, Si as the first substrate 41
基板を用いた場合には、基板サイズに制限があるもののTFT素子を高密度に形成できる。 In the case of using the substrate, a TFT element can be formed at a high density but have limited substrate size. そこで、以下のようにして、上記基板サイズの制限を超えたサイズの第3の基板47を形成することができる。 Therefore, it is possible in the following manner to form a third substrate 47 having a size exceeding the limit of the substrate size. すなわち、TFT素子43が高密度で形成されたSi基板(第1の基板)41 That, Si substrate (first substrate) on which a TFT element 43 is formed at a high density 41
を複数枚形成する。 The multiple sheets formed. そして、この複数枚のSi基板(第1 Then, the plurality of Si substrates (first
の基板)41の位置をずらして第2の基板45に全体転写することによって、TFT素子43が高密度で転写された(つまり、自然数m,nが大きい)第2の基板45を形成するのである。 By whole transferred to the second substrate 45 by shifting the position of the substrate) 41, TFT elements 43 is transferred at high density (i.e., a natural number m, n is large) so to form the second substrate 45 is there.

【0061】上記ガラス基板(第2の基板)45に、複数枚のSi基板(第1の基板)41上のTFT素子43を転写する場合には、図1(a)〜図1(c)に示す第1の基板4 [0061] In the glass substrate (second substrate) 45, in the case of transferring a plurality of Si substrate (first substrate) TFT element 43 on 41, FIG. 1 (a) ~ FIG 1 (c) the first substrate 4 shown in
1から第2の基板45への転写プロセスに従って、1枚の第1の基板41毎にアライメントしつつ第1の基板4 According transfer process from 1 to the second substrate 45, the first substrate 4 while alignment for each first substrate 41 of one
1の枚数だけ転写を繰り返して行えばよい。 Only the number of 1 may be carried out by repeating the transfer. こうすることによって、複数枚の第1の基板41上のTFT素子4 By doing so, TFT elements 4 on the plurality first substrate 41
3を10μm以下の間隔で第2の基板45上に転写することが可能となる。 3 can be transferred onto the second substrate 45 at intervals of less than 10μm to. 従来例1の如く、複数枚の第1の基板を第2の基板上に敷き詰める方法の場合には、第1の基板形成時のダイシング加工精度や第2の基板への接着加工精度の点で、各素子を10μm以下の間隔で配列することは一般には困難である。 As in the conventional example 1, in the process laying the plurality of first substrate to the second substrate, in terms of adhesion machining accuracy to the first substrate during formation of the dicing machining accuracy and a second substrate it is generally difficult to arrange the respective elements in the following intervals 10 [mu] m. ところが、本実施の形態の場合には、第1の基板41の枚数だけ第2の基板45 However, in the case of this embodiment, only the number of the first substrate 41 second substrate 45
への転写を繰り返せば、TFT素子43を10μm以下の間隔で第2の基板45上に配列することは簡単にできるのである。 Repeating the transfer to it is able to easily be arranged on the second substrate 45 the TFT element 43 at intervals of less than 10 [mu] m.

【0062】上述の場合、上記第1の基板41から第2 [0062] When the above-described, first from the first substrate 41 2
の基板45への全体転写の回数が増加する。 Number of total transfer to the substrate 45 is increased. しかしながら、TFT素子43は高密度に形成されているために自然数m,nの値は大きく、1枚の第2の基板45から多数の第3の基板47を形成できる。 However, natural numbers m, the value of n for the TFT element 43 is formed at a high density is large, it can form a plurality of third substrate 47 from the second substrate 45 of one. したがって、上記全体転写によるコストアップを埋めて、尚且つコストダウンを図ることができるのである。 Thus, to fill the cost due to the overall transcriptional, besides it is possible to reduce the cost.

【0063】尚、上記実施の形態においては、紫外線に対するUV剥離樹脂の性質を利用して選択転写を行っている。 [0063] Incidentally, in the above embodiment is selectively performed transfer by utilizing the property of the UV peelable resin to ultraviolet light. しかしながら、この発明はこれに限定されるものではなく、例えば、転写側の基板の一方側,他方側あるいは両側からの静電引力や電磁力を利用して選択転写を行っても差し支えない。 However, the present invention is not limited thereto, for example, one side of the transfer side of the substrate, even if the selected transfer by utilizing an electrostatic attraction or an electromagnetic force from the other side or both sides no problem.

【0064】<第2実施の形態>図9は、本実施の形態の表示用トランジスタアレイパネルの形成方法における手順を示す図である。 [0064] <Second Embodiment> FIG. 9 is a diagram showing a procedure in the method of forming a display transistor array panel of this embodiment. 本実施の形態においては、第1の基板としてガラス基板を用いている。 In the present embodiment, a glass substrate is used as the first substrate.

【0065】図9(a)に示すように、上記第1の基板としてのガラス基板131上に、例えばSi膜132とSi [0065] As shown in FIG. 9 (a), on a glass substrate 131 serving as the first substrate, for example, the Si film 132 and the Si
窒化膜(あるいはSi酸化膜)133との2層構造で成る犠牲層134を形成する。 Forming a sacrificial layer 134 made of a two-layer structure of a nitride film (or Si oxide film) 133. そうした後、i線スパッタを用いたフォトプロセスを含む公知の素子形成プロセスを行って、TFT素子135を素子分離溝136を隔てて所定のピッチで形成する。 After doing so, it performs a known element forming process including a photo process using the i-line sputtering, to form the TFT element 135 at a device isolation trench 136 at a predetermined pitch. ここで、上記ピッチは、目的とする表示用トランジスタアレイパネルの画素ドットの配列ピッチdx,dyを、「2」以上の自然数m,nで除した値dx/m,dy/nである。 Here, the pitch, the arrangement pitch dx of pixel dots of the display transistor array panel for the purpose, the dy, is "2" or larger natural number m, the value dx / m divided by n, dy / n. また、形成するTFT素子1 Further, TFT elements 1 to form
35は、例えばTFTと周辺電極配線の一部を含むものであるが、画素電極は含まない。 35 is, for example, those comprising a part of the TFT and the peripheral electrode wiring, not including the pixel electrode. 尚、形成するTFTの構造は、上述の順スタガTFT,逆スタガTFTおよびコプレーナTFTの何れかである。 The structure of the formed TFT is above a staggered TFT, either inverted staggered TFT and coplanar TFT.

【0066】次に、図9(b)に示すように、上記TFT Next, as shown in FIG. 9 (b), the TFT
素子135側にUV剥離樹脂137を塗布し、第2の基板である光透過性基板としてのガラス基板138を張り付ける。 Applying a UV peelable resin 137 on the device 135 side, pasting glass substrate 138 as a light-transmitting substrate is a second substrate. 次に、図9(c)に示すように、例えばバッファフッ酸等のSiとの選択比が大きな選択エッチング液1 Next, as shown in FIG. 9 (c), for example, selectivity is greater selective etching solution with Si, such as buffer hydrofluoric acid 1
39を、真空吸入法によってTFT素子分離溝136に均一に充填する。 39, uniformly filling the TFT element isolation trenches 136 by a vacuum suction method. こうして、犠牲層134におけるSi In this way, Si in the sacrificial layer 134
窒化膜(あるいはSi酸化膜)133のみを選択エッチングして除去する。 Only nitride film (or Si oxide film) 133 is removed by selective etching.

【0067】次に、図9(d)に示すように、上記ガラス基板(第1の基板)131を取り外して、各TFT素子1 Next, as shown in FIG. 9 (d), remove the glass substrate (first substrate) 131, the TFT elements 1
35をガラス基板(第2の基板)138上に孤立した状態にする。 35 placed in a state in which it is isolated on a glass substrate (second substrate) 138.

【0068】以下、第1実施の形態における図1(d)〜 [0068] Hereinafter, FIG. 1 in the first embodiment (d) ~
図2(f)に示す手順によって、TFTパネル用の第3の基板であるガラス基板の張り合わせ、ガラス基板(第2 By the procedure shown in FIG. 2 (f), bonding of the glass substrate which is a third substrate for TFT panels, a glass substrate (second
の基板)138上のTFT素子135の第3の基板(パネル用基板)上への選択転写を行うのである。 Substrate) third substrate (substrate panels of TFT elements 135 on 138) is performed to select transfer onto.

【0069】上述のように、本実施の形態においては、 [0069] As described above, in this embodiment,
上記ガラス基板(第1の基板)131上に、Si膜132 On the glass substrate (first substrate) 131, Si layer 132
とSi窒化膜(またはSi酸化膜)133とで成る犠牲層1 Sacrificial layer 1 composed of a Si nitride film (or Si oxide film) 133 and
24を介してTFT素子135を素子分離溝136を隔てて、ピッチdx/m,dy/nで形成する。 Separating the element isolation trenches 136 a TFT element 135 via the 24, pitch dx / m, formed at dy / n. ここで、dx, Here, dx,
dyは画素ドットの配列ピッチであり、m,nは「2」以上の自然数である。 dy is an array pitch of the pixel dots, m, n is a natural number greater than or equal to "2". そして、TFT素子135側にUV剥離樹脂137で第2の基板138を張り付けた後、Si After the pasting of the second substrate 138 by UV peelable resin 137 to TFT device 135 side, Si
との選択比が大きな選択エッチング液139を真空吸入法でTFT素子分離溝136に充填して犠牲層134のSi窒化膜(あるいはSi酸化膜)133のみを選択エッチングし、ガラス基板(第1の基板)131を除去する。 Select ratio select only Si nitride film (or Si oxide film) 133 of the sacrificial layer 134 to fill the TFT element isolation trenches 136 a large selective etching solution 139 in a vacuum inhalation etching the glass substrate (first removing the substrate) 131. そうした後、第1実施の形態と同様にして、転写対象の Thereafter, the program in the same manner as in the first embodiment, the transfer object
(つまり、画素を構成する)TFT素子135のみを第3 (I.e., forming a pixel) only the 3 TFT element 135
の基板に選択転写するのである。 Than is selectively transferred to the substrate.

【0070】したがって、第1実施の形態と同じ効果を奏する表示用トランジスタアレイパネルの形成方法を、 [0070] Thus, a method of forming a display transistor array panel to achieve the same effect as the first embodiment,
ガラス基板を上記第1の基板とする場合にも適用できる。 The glass substrate can be applied to the case where the above first substrate. ところで、第1の基板131としてガラス基板を用いた場合には、通常は基板サイズに制限は無く大型の基板を形成できる。 Incidentally, in the case of using a glass substrate as the first substrate 131 it is usually possible to form a large substrate without limit to substrate size. したがって、dx/m,dy/nのピッチでTFT素子135が形成された大型のガラス基板(第1の基板)131を形成することによって、大型の表示用トランジスタアレイパネルを容易に形成できるのである。 Therefore, by forming the dx / m, large glass substrate of the TFT element 135 at a pitch of dy / n is formed (first substrate) 131 is the display transistor array panel of large can be easily formed .

【0071】そして、本実施の形態においても、1枚の第2の基板138を用いて、この第2の基板138から第3の基板(パネル用基板)への選択転写を、第2の基板138をx方向へdx/mあるいはy方向へdy/nだけ移動させながら(m×n)枚の第3の基板に対して行うことによって、第1の基板131を1枚作成すれば、(m× [0071] Then, also in the present embodiment, by using the second substrate 138 of one, a selection transfer from the second substrate 138 to the third substrate (substrate panels), a second substrate by performing 138 against (m × n) pieces of third substrate while moving the x-direction to dx / m or y direction by dy / n, the first substrate 131 by creating one, ( m ×
n)枚のパネル用基板に同一の選択転写を行うことができる。 To n) panels for the substrate can be performed the same selection transcription. すなわち、本実施の形態によれば、第1の基板1 That is, according to this embodiment, the first substrate 1
31上にTFT素子135を形成するコストを概略1/ The cost of forming the TFT elements 135 on the 31 schematically 1 /
(m×n)にできるのである。 It can be in the (m × n).

【0072】例えば、13.3インチXGA(Extended G [0072] For example, 13.3 inches XGA (Extended G
raphics Array)−LCD(液晶ディスプレイ)パネルに適用した場合には、パネルサイズ203×270=54, raphics Array) -LCD (when applied to a liquid crystal display) panel, panel size 203 × 270 = 54,
810mm 2の中にRGB合計で768×1024=2,3 In RGB total in the 810mm 2 768 × 1024 = 2,3
59,300個のTFT素子を内蔵しており、TFT素子135の縦横夫々の配列ピッチnは、概略88μm,2 Incorporates a 59,300 pieces of TFT elements, the arrangement pitch n of vertical and horizontal respective TFT elements 135, outline 88 .mu.m, 2
64μmである。 It is 64μm. ここで、m=4,n=12を選択して第1の基板131上へのTFT素子135の配列ピッチを22μmとした場合には、TFT素子135が全体転写された第2の基板138上のTFT素子135の配列ピッチは、表示用LCDパネルに比して縦4倍,横12倍であるために、1枚の第2の基板128から4×12= Here, m = 4, n = when 12 was 22μm and the arrangement pitch of the TFT element 135 selects the first substrate 131 above the the second substrate 138 on which the TFT elements 135 are entire transcribed the arrangement pitch of the TFT elements 135, four vertical fold compared to the LCD panel for display, because it is 12 times the horizontal, one of the second substrate 128 from 4 × 12 =
48枚の表示用LCDパネルを形成できる。 It can form a 48 sheet display LCD panel of. したがって、プロセスコストの大幅な削減を図ることができるのである。 Therefore, it is possible to achieve a significant reduction in process cost.

【0073】こうして、本実施の形態においても、第1 [0073] Thus, also in this embodiment, the first
実施の形態と同様に、表示用トランジスタアレイパネル製造設備におけるイニシャルコストの約30%を占める成膜工程設備および約26%を占めるフォト工程設備のスループットを、実質的に10倍〜100倍程度向上させることができる。 Similarly, the film formation process equipment and throughput of the photo process equipment, which accounts for about 26% account for about 30% of the initial cost of the display transistor array panel manufacturing equipment, substantially increased 10 times to 100 times that of the embodiment it can be. また、TFT素子43の形成に要する材料費も1/10〜1/100に低減できる。 Moreover, material costs required for forming the TFT element 43 can be reduced to 1 / 10-1 / 100. 結果として、表示用トランジスタアレイパネルの製造コストの大幅な削減が可能となるのである。 As a result, it become possible to greatly reduce the manufacturing cost of the display transistor array panel.

【0074】<第3実施の形態>上記各実施の形態においては、一つの基板上のTFT素子の他の基板への選択転写を、第2の基板45,138から第3の基板47への転写に適用している。 [0074] In the <Third Embodiment> In the above respective embodiments, the selection transfer to other substrates one TFT devices on the substrate, from the second substrate 45,138 to the third substrate 47 It is applied to the transfer. しかしながら、上記選択転写は、第1の基板から第2の基板への転写に適用することも可能である。 However, the selective transfer can also be applied from the first substrate to the transfer to the second substrate.

【0075】すなわち、第1実施の形態における図1 [0075] That is, FIG. 1 in the first embodiment
(a)あるいは第2実施の形態における図9(a)と同様にして、第1の基板上に、画素の一方向への配列ピッチdx (A) or in the same manner as in FIG. 9 (a) in the second embodiment, on the first substrate, the array pitch dx in one direction of the pixel
および他方向への配列ピッチdyを「2」以上の自然数m, And the arrangement pitch dy "2" or greater natural number m in the other direction,
nで除した値dx/m,dy/nのピッチで第1の基板上にTFT素子を1枚形成する。 The value dx / m divided by n, a TFT element on a first substrate at a pitch of dy / n to form one. そして、上記1枚の第1の基板から上記第2の基板上へのTFT素子の選択転写を、アライメントを行って(m×n)回繰り返す。 Then, the selected transfer of the TFT element from the first substrate of one said to said second substrate, repeatedly performs alignment (m × n) times. こうして、上記TFT素子の上記一方向への配列ピッチがdx Thus, the arrangement pitch to the one direction of the TFT element is dx
であり、他方向への配列ピッチがdyであり、且つ、上記第1の基板の大きさの(m×n)倍の大きさの第2の基板を得るのである。 , And the a arrangement pitch in the other direction is dy, and is to obtain the second substrate of the magnitude of the first substrate (m × n) times the size. 以後は、この第2の基板上のTFT It is hereinafter this second TFT on the substrate
素子を第3の基板上に全体転写すればよい。 The element may be a whole transferred to the third substrate.

【0076】こうすることによって、上記第1の基板が基板サイズに制限のあるSi基板である場合でも、上記制限を越えた大きさの表示用トランジスタアレイパネルの形成が可能となるのである。 [0076] By so doing, even when the first substrate is a Si substrate with limited substrate size is the formation of the display transistor array panel of magnitude beyond the limits becomes possible. 上記第1の基板は、Si Said first substrate, Si
基板に限らずガラス基板であっても差し支えない。 No problem even in the glass substrate is not limited to the substrate.

【0077】尚、本実施の形態を適用する場合には、上記第1の基板とTFT素子との間に形成される透明絶縁膜下に、例えば、紫外線照射で接着力が低下するUV硬化型粘着剤等を形成して、上記第1の基板からTFT素子を選択的に剥離可能にする必要がある。 [0077] Incidentally, in the case of applying the present embodiment, under a transparent insulating film formed between the first substrate and the TFT element, eg, UV-curable adhesive force decreases in ultraviolet radiation to form an adhesive or the like, it is necessary to make the TFT element from the first substrate selectively strippable. また、場合によっては、第3の基板への全体転写は無くとも構わない。 In some cases, the entire transfer to the third substrate may even without.

【0078】 [0078]

【発明の効果】以上より明らかなように、請求項1に係る発明の表示用トランジスタアレイパネルの形成方法は、画素の一方向への配列ピッチdx及び他方向への配列ピッチdyを2以上の自然数m,nで除したdx/m,dy As apparent from foregoing description, the method of forming the display transistor array panel according to the invention of claim 1, the arrangement pitch dy two or more of the array pitch dx and the other direction of the one direction of the pixel dx / m obtained by dividing the natural number m, n, dy
/nのピッチで基板上に素子を設ける工程と、上記基板上に設けられた素子のうち上記画素の配列ピッチdx,d / N the step of providing an element on a substrate at a pitch of the arrangement pitch dx of the pixel of the element provided on the substrate, d
yに対応する素子のみを選択的に他の基板に転写する工程を備えたので、転写元の基板上には、表示用トランジスタアレイパネルに形成される画素数の(m×n)倍の素子が設けられている。 Since with the process of transferring selectively to other substrates only elements corresponding to y, the transfer source substrate, the number of pixels formed in the display transistor array panel (m × n) times the element It is provided. したがって、上記転写元の1枚の基板から(m×n)枚の表示用トランジスタアレイパネルを形成することができる。 Therefore, it is possible to form from one substrate of the transfer source of (m × n) Like the display transistor array panel.

【0079】すなわち、この発明によれば、基板上への素子形成コストを、基板上に形成される素子数と上記画素数とが同数である従来の表示用トランジスタアレイパネルの形成方法に比較して1/(m×n)に低減できる。 [0079] That is, according to the present invention, the device forming cost on a substrate, the number of elements formed on the substrate and the number of the pixel is compared with the conventional method of forming a display transistor array panel is equal It can be reduced to 1 / (m × n) Te.
したがって、表示用トランジスタアレイパネル製造設備におけるイニシャルコストの約30%を占める成膜工程設備および約26%を占めるフォト工程設備のスループットを、実質的に(m×n)倍に向上させることができる。 Therefore, it is possible to improve the throughput of the photo process equipment occupying the deposition process equipment and about 26% account for about 30% of the initial cost of the display transistor array panel manufacturing equipment, substantially (m × n) times . また、上記素子の形成に要する材料費を1/(m× Moreover, material costs required for forming the element 1 / (m ×
n)に低減できる。 Can be reduced to n). 結果として、表示用トランジスタアレイパネルの製造コストの大幅な削減が可能となるのである。 As a result, it become possible to greatly reduce the manufacturing cost of the display transistor array panel.

【0080】さらに、上記素子が設けられた1枚の基板から他の基板上への素子の選択転写を(m×n)回繰り返すことによって、上記素子の一方向への配列ピッチがd [0080] Further, by repeating the selection transfer elements from one substrate to the elements are provided to other substrates (m × n) times, the arrangement pitch in one direction of the device is d
xであり、他方向への配列ピッチがdyであると共に、上記転写元の基板の大きさの(m×n)倍の大きさの表示用トランジタアレイパネルを得ることができる。 Is x, the arrangement pitch in the other direction, together with a dy, can be obtained of the transfer source substrate size of the (m × n) times the size of the display transitional capacitor array panel. したがって、この場合には、上記従来の表示用トランジスタアレイパネルの形成方法によって同じ大きさの表示用トランジスタアレイパネルを形成する場合に比較して、上記素子の形成に要する材料費を低減できる。 Therefore, in this case, as compared with the case of forming a display transistor array panel of the same size by the above conventional method of forming a display transistor array panel may reduce material costs required for forming the above device.

【0081】また、請求項2に係る発明の表示用トランジスタアレイパネルの形成方法は、画素の一方向への配列ピッチdxおよび他方向への配列ピッチdyを2以上の自然数m,nで除した値dx/m,dy/nのピッチで第1の基板上に素子を形成する工程と、上記第1の基板上に形成された素子を第2の基板上に全体転写する工程と、上記第1の基板を除去して上記素子を第2の基板上に孤立配列させる工程と、記第2の基板上に転写された素子のうち上記画素の配列ピッチdx,dyに対応する素子のみを選択的に表示用トランジスタアレイ用の第3の基板に転写する工程を備えたので、上記第1の基板上には、表示用トランジスタアレイ用の第3の基板に形成される画素数の(m×n)倍の素子が形成されている。 [0081] The formation method for a display transistor array panel according to the invention of claim 2, obtained by dividing the arrangement pitch dy to the arrangement pitch dx and the other direction in one direction of the pixel 2 or more natural number m, with n forming an element on the first substrate with the value dx / m, a pitch of dy / n, a step of whole transferring the first element formed on a substrate on a second substrate, said first select the element to remove the first substrate and the step of isolating arranged on the second substrate, the serial arrangement pitch dx of the pixel of the second transcribed elements on a substrate, only the elements corresponding to dy since with the process of transferring to the third substrate for a display transistor array, said the first substrate, the number of pixels formed on the third substrate for a display transistor array (m × n) times the element is formed. したがって、上記素子が形成された1枚の第1の基板から(m× Therefore, (m × from the first substrate 1 Like the element is formed
n)枚の第3の基板を形成することができる。 n) pieces of third substrate can be formed.

【0082】すなわち、この発明によれば、第1の基板上への素子形成コストを、上記第1の基板上に形成される素子数と上記第3の基板に形成される画素数とが同数である従来の表示用トランジスタアレイパネルの形成方法に比較して1/(m×n)に低減できる。 [0082] That is, according to the present invention, the device forming cost to the first substrate, and the number of pixels formed on said first number of elements formed on the substrate and the third substrate equal in it compared to conventional method of forming a display transistor array panel can be reduced to 1 / (m × n). 特に、上記第1の基板がSi基板である場合には、上記第1の基板上に従来の10倍〜100倍の素子を形成することができ、表示用トランジスタアレイパネルの製造コストの大幅な削減が可能となるのである。 In particular, the when the first substrate is a Si substrate, the first can be formed of conventional 10 to 100 times of the element on the substrate, a significant cost of manufacturing the display transistor array panel reduction is the is possible.

【0083】また、請求項3に係る発明の表示用トランジスタアレイパネルの形成方法は、上記素子が選択転写される基板上の位置には上記素子が嵌合される凹部が形成されているので、上記凹部に接着剤層を形成することによって、上記素子の選択転写を更に容易に行うことができる。 [0083] The formation method for a display transistor array panel according to the invention of claim 3, since the position on the substrate where the element is selected transfer is a recess in which the element is fitted, by forming the adhesive layer in the recess, it is possible to further facilitate the selection transcription of said element.

【0084】また、請求項4に係る発明の表示用トランジスタアレイパネルの形成方法は、上記素子が選択転写される基板上の位置に接着剤層が選択的に形成されているので、上記素子の選択転写を更に容易に行うことができる。 [0084] The formation method for a display transistor array panel according to the invention of claim 4, since the adhesive layer is selectively formed at a position on the substrate where the element is selected transferred, the elements it can be more easily make a selection transfer.

【0085】また、請求項5に係る発明の表示用トランジスタアレイパネルの形成方法における上記素子は順スタガ型のTFTであるので、基板上への上記順スタガ型TFTの形成コストを1/(m×n)に低減できる。 [0085] Further, since the element in the formation method of a display transistor array panel according to the invention of claim 5 is a staggered TFT, and the above-mentioned order staggered 1 / formation cost TFT (m onto a substrate can be reduced to × n).

【0086】また、請求項6に係る発明の表示用トランジスタアレイパネルの形成方法における上記素子は逆スタガ型のTFTであるので、基板上への上記逆スタガ型TFTの形成コストを1/(m×n)に低減できる。 [0086] Further, since the element in the formation method of a display transistor array panel according to the invention of claim 6 is a reverse stagger TFT, and the the inverse stagger type 1 / formation cost TFT (m onto a substrate can be reduced to × n).

【0087】また、請求項7に係る発明の表示用トランジスタアレイパネルの形成方法における上記素子はコプレーナ型のTFTであるので、基板上への上記コプレーナ型TFTの形成コストを1/(m×n)に低減できる。 [0087] Further, since the element in the display transistor array panel forming method of the invention according to claim 7 is a coplanar type TFT, the formation cost of the coplanar type TFT on the substrate 1 / (m × n It can be reduced to).

【0088】また、請求項8に係る発明の表示用トランジスタアレイパネルの形成方法における上記素子は配線交差部をも含んでいるので、基板上への上記配線交差部をも含むTFTの形成コストを1/(m×n)に低減できる。 [0088] Further, since the element in the formation method of a display transistor array panel according to the invention of claim 8 includes also a wiring intersection portion, the formation cost of the TFT including also the wiring intersection on a substrate It can be reduced to 1 / (m × n).

【0089】また、請求項9に係る発明の表示用トランジスタアレイパネルの形成方法における上記第1の基板はシリコン基板であるので上記素子を高密度に形成できる。 [0089] Also, the first substrate of the display transistor array panel forming method of the invention according to claim 9 the element can be formed at a high density because it is a silicon substrate. したがって、上記自然数m,nを容易に大きくすることが可能となり、上記第1の基板上への素子形成コストを大幅に低減できる。 Therefore, it is possible to increase the natural number m, the n easily, it is possible to significantly reduce the element formation cost to the first substrate.

【0090】また、請求項10に係る発明の表示用トランジスタアレイパネルの形成方法における上記第1の基板はガラス基板であるので、上記第1の基板を大型に形成できる。 [0090] Also, the first substrate of the display transistor array panel forming method of the invention according to claim 10 Since the glass substrate can form the first substrate large. したがって、この発明によれば、上記第1の基板上への素子形成コストを1/(m×n)に低減でき、 Therefore, according to the present invention, it is possible to reduce the element formation cost to the first substrate to 1 / (m × n),
且つ、大型の表示用トランジスタアレイパネルを容易に形成できる。 And, a display transistor array panel of large can be easily formed.

【0091】また、請求項11に係る発明の表示用トランジスタアレイパネルの形成方法では、上記第1の基板上の素子の上記第2の基板上への全体転写を、光で接着力が低下する接着剤によって行い、上記第2の基板上の素子の上記第3の基板上への選択転写を、上記第2の基板の裏面から転写対象の素子の箇所への選択的な光照射によって行うので、上記接着剤の塗布および上記第2の基板の裏面からの光の選択照射という簡単な方法によって、上記第2の基板上の素子の上記第3の基板上への選択転写を行うことできる。 [0091] In the method for forming the display transistor array panel of the invention according to claim 11, the entire transfer to the first element on the substrate of the second substrate, adhesion with light is reduced performed by an adhesive, the selection transfer to the said third substrate of the second element on the substrate, is performed by selective irradiation of the portion of the element to be transcribed from the back surface of the second substrate , by a simple method that the light of the selected irradiation from the back surface of the coating and the second substrate of the adhesive can be carried out selectively transfer to the said third substrate of the second element on the substrate.

【0092】また、請求項12に係る発明の表示用トランジスタアレイパネルの形成方法では、上記第1の基板上にフッ化水素酸に対して耐性を有する透明絶縁膜を形成しているので、上記第1の基板の除去に際してエッチャントとしてフッ化水素酸を使用する場合に、上記透明絶縁膜の存在によって上記素子を保護できる。 [0092] In the method for forming the display transistor array panel according to the invention of claim 12, since a transparent insulating film having resistance to hydrofluoric acid on the first substrate, the when using hydrofluoric acid as an etchant when removing the first substrate, it can protect the device by the presence of the transparent insulating film.

【0093】また、請求項13に係る発明の表示用トランジスタアレイパネルの形成方法では、上記フッ化水素酸に対して耐性を有する透明絶縁膜は酸化タンタル膜あるいはダイヤモンド膜の何れ一方であるので、上記第1 [0093] In the method for forming the display transistor array panel according to the invention of claim 13, since the transparent insulating film having a resistance to the hydrofluoric acid is while either tantalum oxide film or a diamond film, the first
の基板除去用のエッチャントとしてフッ化水素酸が使用する場合に、酸化タンタル膜あるいはダイヤモンド膜の何れ一方の存在によって上記素子を確実に保護できる。 When hydrofluoric acid is used as an etchant for the substrate removal can reliably protect the device by the presence of any one of the tantalum oxide film or a diamond film.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】この発明の表示用トランジスタアレイパネルの形成方法における手順を示す図である。 1 is a diagram showing a procedure in the method of forming a display transistor array panel of the present invention.

【図2】図1に続く表示用トランジスタアレイパネルの形成方法における手順を示す図である。 Is a diagram illustrating a procedure in FIG. 2 displays transistor array panel forming method subsequent to FIG.

【図3】図2に続く受動素子部形成プロセスの説明図である。 3 is an explanatory view of a passive element portion forming process subsequent to FIG.

【図4】図1〜図3に示す形成方法によって形成された表示用トランジスタアレイパネルの外観図である。 4 is an external view of a display transistor array panel formed by the forming method shown in FIGS.

【図5】順スタガTFTの構造を示す図である。 FIG. 5 is a diagram showing the structure of a staggered TFT.

【図6】逆スタガTFTの構造を示す図である。 6 is a diagram showing a structure of a reverse stagger TFT.

【図7】コプレーナTFTの構造を示す図である。 7 is a diagram showing a structure of a coplanar TFT.

【図8】逆スタガTFTにおけるソース電極配線とゲート電極配線との交差部の断面図である。 8 is a cross-sectional view of the intersection between the source electrode wiring and the gate electrode wiring in a reverse stagger TFT.

【図9】図1とは異なる表示用トランジスタアレイパネルの形成方法における手順の一部を示す図である。 The 9 1 is a diagram showing a part of steps in the formation process of different displays transistor array panel.

【図10】従来の表示用トランジスタアレイパネルの形成方法において剥離層をエッチング除去して第1の基板全体を除去する方法の手順を示す図である。 10 is a diagram illustrating a procedure of a method of removing the entire first substrate a separation layer is removed by etching in the conventional method of forming a display transistor array panel.

【図11】従来の表示用トランジスタアレイパネルの形成方法においてエッチバック工程によって第1の基板全体を除去する方法の手順を示す図である。 11 is a diagram illustrating a procedure of a method of removing the entire first substrate by an etch-back process in the conventional method of forming a display transistor array panel.

【図12】従来の表示用トランジスタアレイパネルの形成方法において中間エッチストップ層を用いたシリコン薄膜転写法の手順を示す図である。 12 is a diagram showing a procedure of a silicon thin film transfer method using an intermediate etch stop layer in the conventional method of forming a display transistor array panel.

【図13】従来の表示用トランジスタアレイパネルの形成方法においてUV剥離両面テープを用いた転写方法の手順を示す図である。 It is a diagram illustrating a procedure of a transfer method using a UV peelable double-sided tape in [13] conventional method of forming a display transistor array panel.

【図14】従来の表示用トランジスタアレイパネルの形成方法において基板上に密に形成したディバイスを粗に配置し直す転写方法の手順を示す図である。 14 is a diagram showing a procedure of transfer process rearrange devices 60 densely formed on the substrate roughness in forming process of a conventional display transistor array panel.

【符号の説明】 DESCRIPTION OF SYMBOLS

41…Si基板(第1の基板)、 42…Si酸化膜、43,125…TFT素子、 44,126 41 ... Si substrate (first substrate), 42 ... Si oxide film, 43, 125 ... TFT element, 44,126
…素子分離溝、45,128…ガラス基板(第2の基板)、46,127…UV剥離樹脂、 47,55… ... isolation trench, 45,128 ... glass substrate (second substrate), 46,127 ... UV peeling resin, 47 and 55 ...
ガラス基板(第3の基板)、48,57…接着樹脂、 Glass substrate (third substrate), 48,57 ... adhesive resin,
50,62…紫外線、66…ソース電極配線、 50, 62 ... ultraviolet, 66 ... source electrode wiring,
68…ゲート電極配線、69…ドレイン電極配線、 70…画素電極、131…ガラス基板(第1の基板)、 132…Si膜、133…Si窒化膜 68 ... gate electrode wiring, 69 ... drain electrode wiring, 70 ... pixel electrode, 131 ... glass substrate (first substrate), 132 ... Si film, 133 ... Si nitride film
(あるいはSi酸化膜)、134…犠牲層。 (Or Si oxide film), 134 ... sacrificial layer.

Claims (13)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 基板上に、画素の一方向への配列ピッチdxを2以上の自然数mで除したdx/mのピッチ、および、他方向への配列ピッチdyを2以上の自然数nで除したdy/nのピッチで素子を設ける工程と、 上記基板上に設けられた素子のうち、上記画素の配列ピッチdx,dyに対応する素子のみを選択的に他の基板に転写する工程を備えたことを特徴とする表示用トランジスタアレイパネルの形成方法。 To 1. A substrate, the pitch of the arrangement pitch dx two or more dx / m obtained by dividing the natural number m in one direction of pixels and, dividing the array pitch dy in the other direction more natural number n provided with a step of providing the element at a pitch of dy / n was, among elements provided on the substrate, the arrangement pitch dx of the pixel, the step of transferring selectively to other substrates only elements corresponding to dy method of forming a display transistor array panel, characterized in that the.
  2. 【請求項2】 第1の基板上に、画素の一方向への配列ピッチdxを2以上の自然数mで除したdx/mのピッチ、および、他方向への配列ピッチdyを2以上の自然数nで除したdy/nのピッチで素子を形成する工程と、 上記第1の基板上に形成された素子を第2の基板上に全体転写する工程と、 上記第1の基板を除去して、上記素子を上記第2の基板上に孤立配列させる工程と、 上記第2の基板上に転写された素子のうち、上記画素の配列ピッチdx,dyに対応する素子のみを選択的に表示用トランジスタアレイ用の第3の基板に転写する工程を備えたことを特徴とする表示用トランジスタアレイパネルの形成方法。 To 2. A first substrate, the pitch of the dx / m to the arrangement pitch dx divided by a natural number of 2 or more m in one direction of pixels and, two or more natural number array pitch dy in the other direction forming an element with a pitch of dividing the dy / n by n, the first element formed on a substrate comprising the steps of overall transfer onto the second substrate, and removing the first substrate a step to isolate arranging the element on said second substrate, of the elements which have been transferred to the second substrate, for selectively displaying only elements corresponding to the arrangement pitch dx, dy of the pixel method of forming a display transistor array panel comprising the step of transferring the third substrate for transistor array.
  3. 【請求項3】 請求項1あるいは請求項2に記載の表示用トランジスタアレイパネルの形成方法において、 上記素子が選択転写される基板上の位置には、上記素子が嵌合される凹部が形成されていることを特徴とする表示用トランジスタアレイパネルの形成方法。 3. A method of forming a display transistor array panel of claim 1 or claim 2, the position on the substrate where the element is selected transferred, recess the device is fitted is formed method of forming a display transistor array panel, characterized by that.
  4. 【請求項4】 請求項1あるいは請求項2に記載の表示用トランジスタアレイパネルの形成方法において、 上記素子が選択転写される基板上の位置には、接着剤層が選択的に形成されていることを特徴とする表示用トランジスタアレイパネルの形成方法。 4. A method of forming a display transistor array panel of claim 1 or claim 2, the position on the substrate where the element is selected transferred, the adhesive layer is selectively formed method of forming a display transistor array panel, characterized in that.
  5. 【請求項5】 請求項1あるいは請求項2に記載の表示用トランジスタアレイパネルの形成方法において、 上記素子は、順スタガ型の薄膜トランジスタであることを特徴とする表示用トランジスタアレイパネルの形成方法。 5. A method of forming a display transistor array panel of claim 1 or claim 2, said element forming method of a display transistor array panel, which is a staggered type thin film transistor.
  6. 【請求項6】 請求項1あるいは請求項2に記載の表示用トランジスタアレイパネルの形成方法において、 上記素子は、逆スタガ型の薄膜トランジスタであることを特徴とする表示用トランジスタアレイパネルの形成方法。 6. A method of forming a display transistor array panel of claim 1 or claim 2, said element forming method of a display transistor array panel, which is a inverted staggered thin film transistor.
  7. 【請求項7】 請求項1あるいは請求項2に記載の表示用トランジスタアレイパネルの形成方法において、 上記素子は、コプレーナ型の薄膜トランジスタであることを特徴とする表示用トランジスタアレイパネルの形成方法。 7. A method of forming a display transistor array panel of claim 1 or claim 2, said element forming method of a display transistor array panel, which is a coplanar type thin film transistor.
  8. 【請求項8】 請求項5乃至請求項7の何れか一つに記載の表示用トランジスタアレイパネルの形成方法において、 上記素子は、配線交差部をも含んでいることを特徴とする表示用トランジスタアレイパネルの形成方法。 8. A method of forming a display transistor array panel according to any one of claims 5 to 7, the device may display a transistor, characterized in that also includes the wiring intersection portion the method of forming the array panel.
  9. 【請求項9】 請求項2に記載の表示用トランジスタアレイパネルの形成方法において、 上記第1の基板はシリコン基板であることを特徴とする表示用トランジスタアレイパネルの形成方法。 9. A method of forming a display transistor array panel of claim 2, the method of forming the display transistor array panel, wherein said first substrate is a silicon substrate.
  10. 【請求項10】 請求項2に記載の表示用トランジスタアレイパネルの形成方法において、 上記第1の基板はガラス基板であることを特徴とする表示用トランジスタアレイパネルの形成方法。 10. A method of forming a display transistor array panel of claim 2, the method of forming the display transistor array panel, wherein said first substrate is a glass substrate.
  11. 【請求項11】 請求項2に記載の表示用トランジスタアレイパネルの形成方法において、 上記第1の基板上の素子の上記第2の基板上への全体転写は、光によって接着力が低下する接着剤によって行い、 上記第2の基板上の素子の上記第3の基板上への選択転写は、上記第2の基板の裏面から上記画素の配列ピッチdx,dyに対応する素子の箇所への光照射によって転写の対象となる素子のみを選択的に上記第2の基板から剥離することによって行うことを特徴とする表示用トランジスタアレイパネルの形成方法。 11. A method of forming a display transistor array panel of claim 2, the overall transfer to the first element on the substrate of the second substrate, the adhesive force by light is reduced adhesion performed by agents, the selective transfer to the third substrate of the second element on the substrate, the light from the back surface of the second substrate to the portion of the element corresponding to the arrangement pitch dx, dy of the pixel method of forming a display transistor array panel and performing by peeling only selectively from said second substrate element to be transferred by radiation.
  12. 【請求項12】 請求項2に記載の表示用トランジスタアレイパネルの形成方法において、 上記第1の基板上にフッ化水素酸に対して耐性を有する透明絶縁膜を形成し、この透明絶縁膜上に上記素子を形成することを特徴とする表示用トランジスタアレイパネルの形成方法。 12. A method of forming a display transistor array panel of claim 2, said transparent insulating film is formed that is resistant to hydrofluoric acid on a first substrate, on the transparent insulating film method of forming a display transistor array panel and forming the element.
  13. 【請求項13】 請求項12に記載の表示用トランジスタアレイパネルの形成方法において、 上記フッ化水素酸に対して耐性を有する透明絶縁膜は、 13. A method of forming a display transistor array panel of claim 12, a transparent insulating film having a resistance to the hydrofluoric acid,
    酸化タンタル膜あるいはダイヤモンド膜の何れ一方であることを特徴とする表示用トランジスタアレイパネルの形成方法。 Method of forming a display transistor array panel, characterized in that it is either one of a tantalum oxide film or a diamond film.
JP31029997A 1997-11-12 1997-11-12 Method of forming a display transistor array panel Expired - Fee Related JP3406207B2 (en)

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