JPH11121721A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area occupied by memory cells by a method wherein the common data latching means are provided with read-out data and verified data detected by the bit line current running through memory transistor selected from a power supply by reading-out operation and program verifying operation. SOLUTION: The latches PBk-1-PBk-256 comprising data registers otherwise called page buffers are provided between contacts 42 and 46. These page buffers fill not only the temperary storage of the data to be written in at one time through respectively corresponding BLk-1-BLk-256 but also fill the role of a verifying detector to make a judgement if the programming operation is performed correctly or not by the programming verification also filling the role of a sensing amplifier for sensing and amplifying the data on the BL lines read out of the memory cells. Accordingly, the area occupied by the memory cells can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable and programmable non-volatile semiconductor memory device, and more particularly to an electrically erasable and programmable non-volatile semiconductor memory device.
The present invention relates to an electrically erasable and programmable non-volatile semiconductor memory device having cells of a NAND structure.

[0002]

2. Description of the Related Art Recent developments in various devices controlled by computers or microprocessors require the development of high density electrically erasable and programmable non-volatile memory devices (EEPROMs). For example, in a computer system such as a portable computer or a notebook-type personal computer that uses battery power, a hard disk device having a rotating magnetic disk as an auxiliary memory device occupies a considerable portion. Want a more compact, high-density, high-performance EEPROM.

In order to obtain a high density EEPROM, it is important to reduce the area occupied by memory cells. To solve this, the number of select transistors per cell and the contact holes (co
An EEPROM having a cell having a NAND structure capable of reducing the number of ntact holes has been developed. This NAND structure cell is described in, for example, "IEDM", pp. 412 to 415, "NEW D" issued in 1988.
EVICE TECHNOLOGIES FOR 5V
-ONLY 4Mb EEPROM WITH NAN
D STRUCTURE CELL ".

A cell having such a NAND structure (hereinafter referred to as "cell")
A “NAND cell unit” or “NAND cell”) includes a first selection transistor having a drain connected to a corresponding bit line through a contact hole, a second selection transistor having a source connected to a common source line,
8. A channel is connected in series between the source of the first select transistor and the drain of the second select transistor.
And memory transistors. NA
The ND cell unit is formed on a P-type semiconductor substrate. Each memory transistor has a floating gate formed on a channel region between its source and drain regions via a gate oxide film, and an intermediate insulating film formed on the floating gate. And a control gate formed through the control gate. The program operation of the memory transistor in the NAND cell unit is performed after erasing all the memory transistors in the NAND cell unit at a time.

[0005] Simultaneous erase operation (commonly called "flash erase") of all memory transistors is performed by applying 0 V to the bit line and applying 17 V to the gate of the first selection transistor and the control gate of all the memory transistors. Will be That is, all the memory transistors are enhancement type transistors. Assume this is a transistor programmed to a binary "1". Then, in order to select a memory transistor and program it to binary "0", the bit line, the gate of the first selection transistor, and the control gate of the memory transistor between the first selection transistor and the memory transistor to be programmed are used. , And 0 V is applied to each of the control gate of the memory transistor to be programmed, the control gate of the memory transistor between the memory transistor and the source line, and the gate of the second selection transistor. Thereby, the selected memory transistor is programmed to “0” by a Fowler-Nordheim current (FN current) between the drain and the floating gate, that is, a tunnel current.

However, in such a programming method, a stress is applied to a tunnel portion of a gate oxide film of a memory transistor for programming "0" due to a high voltage applied to its drain, so that a partial voltage is applied every time a program is performed. There is a problem that a gate oxide film subjected to stress causes a leakage current. That is, the data retention capability of the memory cell gradually decreases as the number of times of erasing and programming overlaps,
The reliability of the EPROM is reduced. In order to solve such a problem, an improved device structure in which a NAND cell unit is formed in a P-type well region formed in an N-type semiconductor substrate, and improved erasing and writing using this device structure. The programming technology is described in “Symposium on VLSI Technology” published in 1990, pp. 129-130, “A NAND Structured”.
CELL WITH A NEW PROGRAMM
ING TECHNOLOGY FOR HIGHLY
RELIABLE 5V-ONLY FLASH E
EPROM ". This technique will be briefly described below.

The erasing operation of all the memory transistors in the NAND cell unit, that is, the memory cell, is performed by applying 0 V to all the control gates and applying a high voltage of 20 V to the P-type well region and the N-type substrate. Done. Thereby, electrons are uniformly emitted from the floating gates of all the memory transistors to the P-type well. As a result, the threshold voltage of each memory transistor becomes a negative voltage of about -4 V, and becomes a depletion type state where it is assumed that binary logic "0" is stored. From this state, the memory transistor in the NAND cell unit is selected and programming is performed. In this case, a high voltage of 20 V is applied to the gate of the first selection transistor and the control gate of the selected memory transistor, 0 V is applied to the gate of the second selection transistor, and 7 V is applied to each control gate of the unselected memory transistors. An intermediate voltage is applied.

When programming (or writing) the selected memory transistor to binary logic "1", 0 V is applied to the bit line connected to the NAND cell unit. As a result, electrons are injected into the floating gate of the selected memory transistor, and the state becomes an enhancement type. On the other hand, when programming the selected memory transistor to the binary logic "0", an intermediate voltage 7V which is a program prevention voltage is applied to the corresponding bit line. Thus, the program operation of the selected memory transistor is prevented. In such a programming operation, since electrons injected into the floating gate through the gate oxide film are uniformly injected from the P-type well, the above-described partial stress on the gate oxide film does not occur. Therefore, it is possible to prevent generation of leakage current from the gate oxide film.

However, in the above-described memory device, the following problem occurs as the memory capacity increases.

A normal EEPROM has a page program mode for high-speed programming. The page program operation includes a data loading operation and a program operation. The data loading operation is an operation of sequentially latching and storing byte-sized data in a data register from an input / output terminal. This data register is provided so as to correspond to each bit line. The program operation is an operation of writing data stored in a data register to a memory transistor of a selected word line at a time through a bit line. A page programming technique for an EEPROM having a NAND cell unit is described in IEEE, issued in April 1990.
JOURNAL OF SOLID-STATE CIRCUITS 』VOL. 25 ・
NO. 2, pages 417 to 423.

Further, in a normal EEPROM, a program verification technique is used to improve reliability. Program verification checks whether a programmed cell has been programmed to have a desired threshold voltage. This program verification technology includes an external verification technology controlled by a microprocessor and an internal verification technology performed by a verification circuit inside a chip.
Regarding external verification technology, please refer to V of “IEEE JOURNAL OF SOLID-STATE CIRCUITS” issued in April 1991.
OL. 26 NO. 4, pages 492 to 495, and 1
US Pat. No. 5,05, issued Oct. 1, 991
No. 3,990. This external verification technology
A disadvantage is that it takes a long time to determine whether a programmed cell is correctly programmed. In addition, it is necessary to perform the data loading operation again every time reprogramming is performed after a program failure.

On the other hand, the internal verification technique has an advantage that program verification can be performed at a relatively high speed. The internal verification technology is disclosed in Korean Published Patent No. 91-17445 issued on Nov. 5, 1991 and U.S. Pat. No. 4,811,294 issued on Mar. 5, 1989. These internal verification techniques are performed by a method in which data read from a memory cell through a sense amplifier through a page and data stored in a data register are compared by a comparator. However, as described above, in order to perform program verification, a technique using a comparison circuit that compares data from a sense amplifier that senses and amplifies data read from a memory cell with program data stored in advance in a data register is not known. However, there is a problem that the area occupied by the peripheral circuit in the chip is increased.

[0013]

SUMMARY OF THE INVENTION Therefore, the first object of the present invention is to provide a nonvolatile semiconductor memory device having cells of a NAND structure that can reduce the chip area.

A second object of the present invention is to provide a nonvolatile semiconductor memory device capable of reducing the area occupied by peripheral circuits in a chip.

A third object is to provide a nonvolatile semiconductor memory device capable of preventing over-programming.

[0016]

According to the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a well region formed on the surface of the semiconductor substrate; and a plurality of memory blocks formed in the well region. A memory cell array,
A plurality of bit lines formed parallel to each other on a semiconductor substrate, and in particular, each of the memory blocks has a drain connected to a corresponding one of the bit lines. A plurality of NAND cell units each including a predetermined number of memory transistors connected in series between a source of the selection transistor and a drain of a second selection transistor whose source is connected to a common source line; The memory transistor includes a source and a drain region formed on the surface of the well region so as to be separated from each other, a floating gate formed on a channel region between the source and the drain, and a floating gate. And a control gate formed above the gate. For memory devices, it is primarily providing the characteristic parts such as the following.

That is, a current mirror circuit connected to each bit line for providing a read current to each bit line in a read operation, and a current mirror circuit provided corresponding to the bit line, and a data load from an input / output terminal in a data loading operation. And latch means for latching and storing data, providing data stored on the bit line in a program operation, and sensing and storing data on the bit line read from a memory cell in a program verify and read operation.

In addition, the present invention is connected to the sensing and storing means, and determines whether data on the bit line sensed by the sensing and storing means in a program verify operation is predetermined logical data. It has verification sensing means.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The same reference numerals or reference numerals are used for the same components as much as possible. Also, in the following description, many specific specifications, such as the number of memory cells, the number of NAND cells, the number of bit lines, voltage values, circuit configurations, and components, are shown for a more general understanding of the present invention. .
However, it will be understood by those having ordinary skill in the art that the present invention can be practiced without these specific specifications.

"Memory transistor" as used herein
Is a floating gate MOSFET having a source, drain, floating gate, and control gate
Means “Program” means writing data to the selected memory transistor. Further, "charging the NAND cell unit" means charging the junction capacitor of the channel and the source and drain of each memory transistor constituting the memory cell of the NAND structure to a predetermined voltage. In addition, “k” and “i” in the following description are used as codes indicating portions related to the k-th column block and the i-th memory block, respectively. “J” is a code related to the j-th word line.

The EEPROM of this embodiment has a C
Depletion type N-channel MOS fabricated using MOS fabrication technology and having a threshold voltage of -2 to -3V
Transistor (hereinafter referred to as "D-type transistor"), an enhancement N-type transistor having a threshold voltage of about 0.7V.
A channel MOS transistor (hereinafter “N-channel transistor”) and a P-channel MOS transistor having a threshold voltage of about −0.9 V (hereinafter “P-channel transistor”) are used.

FIG. 1 is a schematic block diagram of the EEPROM of this embodiment. FIGS. 2 and 3 are continuous drawings at the lower end of FIG. 2 and the upper end of FIG. 3.
Memory cell array 10 (FIG. 2), input buffer 26, output buffer 28, column decoder 30, column selection circuit 32, latches PBk-1 to PBk-256, sense amplifier 12
(FIG. 3) and connected to the memory cell array 10,
The circuit examples of the transfer transistor arrays 34-i (BT1 to BT10: FIG. 2) forming a part of the block selection control circuit 18 (FIG. 1) are shown. The remaining portion related to the input / output terminal is the same as the component related to the k-th input / output terminal I / Ok.

The memory cell array 10 is composed of NAND cell units NU arranged in a matrix of 1,024 rows and 2,048 columns. Memory blocks (row blocks) BK1 to BK1024 are divided. Then, each memory block BK has 2,048 rows arranged in the same row.
It has NAND cell units. Each NAND cell unit has memory transistors M1 to M8 whose drain-source paths are connected in series between the source of the first select transistor ST1 and the drain of the second select transistor ST2. The gates of the first and second selection transistors ST1, ST2 and the memory transistor M
The control gates of 1 to M8 are bit lines BLk-1 to BLk
, 256 (k = 1, 2,..., 8) and the first and second selection lines SL1 and SL2 and the word line WL
1 to WL8, respectively. Thus, each memory transistor M1 to M8 of the memory transistor group of each row (each group includes 2,048 transistors)
Are word lines WL1 to WL8 and bit lines BLk-1 to BLk-1
It is located at each intersection with Lk-256. The drains of the first selection transistors ST1 are connected to corresponding bit lines, respectively, and the sources of the second selection transistors ST2 are connected to a common source line CSL.

That is, the memory cell array 10 has a total number of row blocks × NAND scale × number of columns = 1,024 × 8
× 2,048 (= 16,777,216) memory cells, and each memory block BK is 8 × 2,048
It has (= 16,384) memory cells. Further, the memory cell array 10 has input / output terminals I / O1 to I / O
8 column blocks CBk (k = 8
, 8), and each column block CB includes 256 bit lines (or column lines) BLk arranged in the column direction.
-1 to BLk-256. Therefore, each column block CB has 256 kilobits (= 1,024 × 25).
6), which are arranged in each row block BK1
Includes a portion (256 bits) of BK1024.

The memory cell array 10 shown in FIG. 2 is formed in a P-type well region formed on a semiconductor substrate. FIG.
And FIG. 5 shows a NAND constituting the memory cell array 10.
A plan view and a cross-sectional view of one of the cell units NU are shown, respectively.

The semiconductor substrate 72 is a P-type silicon semiconductor substrate having a <100> crystal plane and an impurity concentration of 7 × 10 14 / cm 3. A P-type well region 76 having an impurity concentration of about 2.times.10@16 / cm @ 3
The second main surface 78 is formed at a depth of about 4 μm.
This P-type well region 76 has a depth of 10 μm and an impurity concentration of about 5 × 10 15 / cm 3.
It is surrounded by four. N + regions 80, 82 doped with a high concentration of N-type impurities
84, 86, 88, 90, 92 are formed so as to be separated from each other via a channel region 94 of the main surface 78. N
+ Region 80 is a contact region connected to bit line BL made of a metal material such as aluminum through contact hole 96, and is also a drain region of first select transistor ST1. N + regions 82, 84, 86, 88, 90
Are the selection transistor ST1, the memory transistor M1
To M8, which are common source and drain regions of two adjacent transistors among the select transistors ST2. The N + region 92 is a source region of the second select transistor ST2 and also serves as a buried common source line CSL. Incidentally, the common source line CSL is
And a resistance connection through a contact hole.
2 may be a conductor layer embedded so as to be insulated.

First and second selection transistors ST1, ST
Gate layers 98 and 100 of a metal silicide material having a high melting point, such as tungsten silicide, having a thickness of about 1500 ° are formed on the upper portion of the channel region 2 via a gate insulating film 102 of about 300 °. . On the other hand, the channel regions 94 of the memory transistors M1 to M8
A floating gate layer 104 of polycrystalline silicon material having a thickness of about 1500
Through a gate insulating film 106 having a thickness of Further, the floating gate layer 1
On top of this is a control gate layer 108 of a refractory metal silicide material having a thickness of about 1500 ° and an intermediate insulating film 110 (eg SiO 2 -Si) having a thickness of about 250 °.
3N4 -SiO2 ONO insulating film). First and second selection transistors ST1, S
T2 gate layers 98 and 100 and memory transistor M1
The control gate layers 108 to M8 are connected to the first and second selection lines SL1 and SL2 and the word lines WL1 to WL8 formed of the same material as these materials, respectively. The gate layers 98 and 100 and the control gate layer 10
8, the floating gate layer 104, the first and second selection lines SL1, SL2, and the word lines WL1 to WL8 are BP
They are insulated from each other by an insulating layer 112 of an insulating material such as SG, PSG, or silicon oxide.

N + region 8 through contact hole 96
The bit lines BL connected to 0 are arranged on the insulating layer 112 in the column direction. P-type well region 76 and N-type well region 74 are connected together to well electrode 114 through a contact hole (not shown). At the time of the erasing operation, a positive erasing voltage is applied to the well electrode 114, and at the time of operations other than the erasing operation, that is, at the time of programming, program verification, and reading operation, a reference potential, for example, a ground voltage of 0 V is applied. The semiconductor substrate 72 is grounded. Note that the memory cell array 10 can be formed in a P-type well region formed in an N-type semiconductor substrate.

The block selection control circuit 18 shown in FIGS. 1 and 2 selects a predetermined memory block from the memory blocks BK1 to BK1024 and controls the control gate lines CGL1 to CGL8 received from the control gate drive circuit 20. Signals can be sent in various operating modes, such as erase, program,
According to the program verification and read mode, the word lines are provided to the word lines WL1 to WL8 in the selected memory block, respectively. FIG. 2 shows a transfer transistor array 34-i that forms a part of the block selection control circuit 18. In response to the control signal on the block selection control line BSCi, the transfer transistor array 34-i sets the first and second selection gate lines SGLi-1, SGLi-2 and the control gate lines CGL1 to CGL8 to the corresponding first. , And transmission transistors BT1 to BT10 for connecting to the second selection lines SL1 and SL2 and the word lines WL1 to WL8, respectively.

The block selection control circuit 18 causes the word line WL in the unselected memory block BK to float by turning off the transfer transistor BT associated with the unselected memory block BK in the erasing operation. In the program operation, the second selection transistor ST2 in the selected memory block BK is turned ON, and the program prevention voltage V
pi is charged to the source and drain junctions and channels of the memory transistors M1 to M8 in the selected memory block BK.

FIG. 6 shows a circuit example of the block selection control circuit 18 having the transfer transistor array 34-i shown in FIG. For example, when i = 2, the selection gate line S in FIG.
GL2-1, SGL2-2, and block selection control line BS
C2 is a select gate line SG of the transfer transistor array 34-2 associated with the second memory block BK2 shown in FIG.
L2-1, SGL2-2 and block selection control line BSC
2 respectively. Therefore, the block selection control circuit 18 shown in FIG. 6 corresponding to each of the memory blocks BK1 to BK1024 exists as a peripheral circuit on the chip substrate of the EEPROM.

Row decoder 120 using a NAND gate shown in FIG.
1, Q1, R1 and a control signal Xd are input.
The row address signals Pl, Ql and Rl are used as row address signals A1 from an address buffer (not shown) for latching and storing the row addresses a11 to a20 from the external address input terminals.
1. Signals generated by pre-decoding bars A11 to A20 and bar A20 through a predecoder. Then, the row decoder 120 selects 0 V logic “low” at the time of selection.
(“L” level or “L” level), and when not selected, the 5 V logic “high” state (“H” state or “H” level) is output from the signal line 122.
Output to

One input terminal of the NAND gate 124;
This signal line 122 is connected, and the other input terminal of the NAND gate 124 receives a control signal / BLK. The control signal BLK is a signal for setting the word lines WL1 to WL8 to a reference potential of 0 V before or after each operation, as described later. NAND
The output of the gate 124 is sent to the first selection gate line SGLi-1 and is sent to the block selection control line BSCi through the current path of the D-type transistor 126 for preventing high voltage transmission, that is, the channel. The gate of this D-type transistor 126 receives a program control signal PGM that maintains the "L" state in the program operation, and a charge pump circuit 128 is connected to the block selection control line BSCi. . The charge pump circuit 128 supplies a program voltage Vpgm to the selected block selection control line BSCi by a pumping operation using a clock signal φR during a program operation.
Such a charge pump circuit 128 includes N-channel transistors 130 and 132 and a MOS capacitor 134
A known circuit composed of the following is used.

One input terminal of the NAND gate 136 receives the erase control signal / ERA, and the other input terminal is connected to the signal line 122. NAND gate 1
A transmission gate 148 including an N-channel transistor 140 and a P-channel transistor 142 is provided between the output line 36 and the connection point 146. The gate of N-channel transistor 140 receives control signal φ 6, and the gate of P-channel transistor 142 receives control signal φ via inverter 138.
6 A current path of the N-channel transistor 144 is formed between the connection point 146 and the reference potential terminal, and its gate receives a control signal φ7. Further, between the connection point 146 and the second selection gate line SGLi-2, the source-drain path of the D-type transistor 150 for preventing high voltage transmission is connected, and its gate receives the control signal / WE. ing. The second selection gate line SGLi-2 has a charge pump circuit 1 substantially similar to the charge pump circuit 128 described above.
52 are connected. This charge pump circuit 152
During the program operation, the selected second selection gate line SG
The pass voltage Vpas is provided to Li-2.

FIG. 11 shows the control signal φ6 shown in FIG.
An example of the circuit configuration for generating φ7 is shown. In the erase operation mode, the control signals φ6 and φ7 are both in the “L” state.
φ7 is an “H” state and an “L” state, respectively, and control signals φ6 and φ7 are “L” state and “H” in a program operation, respectively.
The state, and the control signals φ6 and φ7 become “H” state and “L” state in the program verification and read operation.

FIG. 7 shows one of the eight control gate drive circuits 20 connected to each of the word lines WL1 to WL8 via the transfer transistor array 34-i, that is, the circuit of the j-th control gate drive circuit. Here is an example. From the viewpoint of reducing the chip area, this control gate drive circuit 20
Is preferably provided commonly to the peripheral circuits of the chip so as to drive the word lines WL of the memory block BK selected according to various operation modes.

Row decoder 154 using NAND gate
Inputs row address signals A8 / A8, A9 / A9, and A10 / A10 from an address buffer (not shown). Row decoder 154 outputs an “L” state when control gate line CGLj is selected, and outputs an “H” state when not selected. The output of row decoder 154 is used as one input of NOR gate 173, and control signal PVF is input to the other input terminal of NOR gate 173. An output signal .phi.V of the NOR gate 173 and an inverted signal .phi.V obtained by inverting the output signal .phi.
te) controls the NAND gate 158 (see FIG. 10 for details) and the verification voltage generation circuit 164.

The control signal PVF is maintained at "L" level only during the program verification operation, and becomes "H" level except during the program verification operation. When control signal PVF is at the "H" level, signal .phi.V is at the "L" state and inverted signal .phi.V is at the "H" state regardless of the output of row decoder 154. When the control gate line CGLj is selected in the program verifying operation, the signal φV is in the “H” state, and the inverted signal φV is in the “L” state. On the other hand, when control gate line CGLj is not selected, signal .phi.V is in the "L" state and inverted signal .phi.V is in the "H" state.

The NAND gate 156 is connected to the row decoder 15
4, the control signal bar DS and the erase control signal bar E
RA is input. The output line 160 of the NAND gate 156 is connected to one input terminal of the NAND gate 158. The other input terminal of the NAND gate 158 receives the program control signal PGM. FIG. 10 shows a circuit example of such a three-state logic NAND gate 158. NA shown in the figure
ND gate 158 is enabled to output when signal .phi.V is at "L" state and inverted signal .phi.V is at "H" state. On the other hand, when the signal φV is in the “H” state and the inverted signal φV is in the “L” state, the impedance becomes high. That is, the control gate line CG is
Only when Lj is selected, NAND gate 158 goes into a high impedance (output point floating) state. The output of NAND gate 158 is sent to node 162. The connection point 162 has a verification voltage generation circuit 164
Is connected.

The verification voltage generation circuit 164 includes a P-channel transistor 166 and N-channel transistors 168, 170 and 172 whose current paths are connected in series between the power supply voltage Vcc terminal and the reference potential terminal. P
The gate of the channel transistor 166 receives the chip enable signal / CE,
8 and 170 are output signals φ of NOR gate 173.
V. The N-channel transistor 172 has a structure in which a drain and a gate are connected, and a source of the N-channel transistor 168 and a drain of the N-channel transistor 170 are connected to a connection point 162. Verification voltage generating circuit 1 having such a configuration
64 is a signal φ of “H” state only in the program verification operation.
V connects to the connection point 162 to generate a verification voltage, for example, about 0.8 V at the connection point 162. This connection point 162
Between source and control gate line CGLj, there is provided a source-drain path of D-type transistor 176 for preventing high voltage transmission, and a gate thereof receives program control signal PGM.

The NAND gate 178 shown in the upper part of FIG.
Receive the output of the NAND gate 156 and a clock signal φR from a ring oscillator (not shown). A charge pump circuit 180 substantially similar to that described above is provided between the output terminal of the NAND gate 178 and the gate of the driving N-channel transistor 182.
Is provided. Driving N-channel transistor 182
Has a program voltage Vpgm and a source connected to the control gate line CGLj. Inverter 1
Reference numeral 90 designates a program control signal PGM as an input. A current path of a D-type transistor 192 for preventing high voltage transmission is provided between the output terminal of the inverter 190 and the gate of the driving N-channel transistor 182. . A program control signal PGM is input to the gate of the D-type transistor 192. As described later, the NAND gate 178 and the charge pump circuit 18
0 and a driving N-channel transistor 182 are connected to the control gate line CG in the program mode.
Lj is the row address signal A8 / bar A8, A9 / bar A
9 and means for supplying the program voltage Vpgm to the control gate line CGLj when selected by A10 / bar A10.

Two input terminals of a NOR gate 188 shown in the lower part of FIG. 7 receive the output of the NAND gate 156 and the clock signal φR, respectively. The output terminal of the NOR gate 188 and the driving N-channel transistor 184
And a charge pump circuit 186 substantially similar to that described above. The drain of the driving N-channel transistor 184 receives the pass voltage Vpas,
The source is connected to the control gate line CGLj. The D-type transistor 1 for preventing high voltage transmission is connected between the connection point 202 between the inverter 190 and the D-type transistor 192 and the gate of the driving N-channel transistor 184.
The current path 94 is connected, and the gate of the D-type transistor 194 receives the program control signal PGM. As will be described later, the circuit 200 including the NOR gate 188, the charge pump circuit 186, and the driving N-channel transistor 184 has the control gate line CGLj in the program mode in which the row address signals A8 / A8, A9 / A9, and A10 / Bar A10
Is a means for supplying the pass voltage Vpas to the control gate line CGLj when not selected.

FIG. 8 shows a common source line CSL shown in FIG.
1 shows a configuration example of a source line driving circuit 22 commonly connected to the first and second embodiments. The source line drive circuit 22 includes an inverter 204 having an input terminal receiving the program control signal PGM, a current path provided between the output terminal of the inverter 204 and the common source line CSL, and a gate connected to the program control signal bar PGM.
A D-type transistor 206 adapted to receive GM;
Charge pump circuit 2 connected to common source line CSL
08. Charge pump circuit 20
Numeral 8 is for boosting the common source line CSL to the program prevention voltage Vpi in the program mode.

The input / output buffer 16 shown in FIG. 1 includes an input buffer 26 and an output buffer 28 connected to each input / output terminal.
(See FIG. 3). Input / output terminals I / O1 to I
Input buffers 26 connected to / O8 respectively convert 1-byte data (8-bit data) input from input / output terminals I / O1 to I / O8 into CMOS level data and temporarily store them. This is a normal circuit. Also,
Output buffer 28 is a normal circuit that outputs 8-bit data read from corresponding column block CB to input / output terminals I / O1 to I / O8 at a time.

The column decoder and selection circuit 14 comprises a column decoder 30 and a column selection circuit 32, as shown in FIG. Selection circuit 32 associated with each column block CB
Comprises transmission transistors T1 to T256 whose source-drain paths are connected between the common bus line CBLk and the data lines DLk-1 to DLk-256, respectively.
Each gate of these transmission transistors T1 to T256 is
The signal lines TL1 arranged in parallel with each other from the column decoder 30
To TL256. Column decoder 3
0 selects one of the signal lines TL1 to TL256 in response to a column address signal from an address buffer (not shown), and sets the transmission transistor T connected to the selected signal line TL to Set to ON.

The data register and sense amplifier 12
As shown in FIG. 3, bit lines BLk-1 to BLk-256 and data line DLk associated with a corresponding column block CB.
-1 to DLk-256. Bit line B
The drain-source paths of the D-type transistors 38 and 40 are connected in series between Lk-1 to BLk-256 and the connection point 36. The power supply voltage Vcc is input to the gate of the D-type transistor 38. The D-type transistor 38 is connected to the bit line BL in the block erase operation.
The transmission of high voltage induced in k-1 to BLk-256 is prevented. The gate of the D-type transistor 40 is adapted to receive a control signal φ1 which is maintained at a 5V "H" state during programming. Further, a drain-source path of the N-channel transistor 44 is provided between the connection point 36 and the connection point 42. The gate of the N-channel transistor 44 is connected to a control line SBL which is turned to “H” during programming.

Further, between the connection point 42 and the connection point 46, latches PBk-1 to PBk-256 constituting a data register also called a page buffer are provided, respectively. These latches PBk-1 to PBk-25
6 comprises two inverters connected in parallel in opposite directions. These latches PBk-1 to PBk-256
Is a program operation, and each corresponding bit line BLk-1
Not only as a page buffer for temporarily storing data so that data can be written to a memory cell at a time through BLk-256, but also as a verification detector for determining whether or not a program has been correctly performed in a program verification operation. In the read operation, it also functions as a sense amplifier for sensing and amplifying data on the bit line BL read from the memory cell.

A three-state logic inverter 48 and an N-channel transistor 49 are connected in parallel between each connection point 42 and each of the corresponding data lines DLk-1 to DLk-256. Clock control (cloc
ked) The three-state logic inverter 48, also called a CMOS inverter, can be output by the "H" state of the control signal φ4, and has a high impedance by the "L" state. Each of the inverters 48 functions as a buffer amplifier that can be output in a program verification operation and a read operation. On the other hand, N receives the control signal φ5 at the gate.
Channel transistor 49 is a transmission transistor for transmitting input data to corresponding latches PBk-1 to PBk-256 in a program operation. FIG. 9 shows a configuration example of the inverter 48 used in this embodiment.

The current paths of the N-channel transistors 50 and 52 are connected in series between the connection points 46 and the reference potential terminal. The gate of the N-channel transistor 52 receives the control signal φ2 which is set to the “H” state during the verify sensing period in the program verify mode and the read sensing period in the read operation. The gates of the N-channel transistors 50 are respectively connected to the connection points 36, and the drain-source paths of the N-channel transistors 37 are provided between the connection points 36 and the reference potential terminals. A control signal is applied to the gate of the N-channel transistor 37 to discharge the bit line BL after the end of the erase and program operations, and to reset the data register to an “L” state, for example, data “0”, immediately before the read operation. Connected to the common signal line DCB.

The data register and the sense amplifier 12 of this example include a constant current circuit 33 called a current mirror. The constant current circuit 33 has a drain-source path between the reference portion 64 which is enabled in the program verify and read operations and disabled in the erase and program operations, and the gate of the N-channel transistor 50 and the power supply voltage Vcc terminal. , A current source unit 66 composed of a P-channel current source transistor 54 connected to each other.
And The reference section 64 functions as a reference for the current source transistor 54, and includes P-channel transistors 56 and 58 and N-channel transistors 60 and 62. P
The source-drain paths of the channel transistors 56 and 58 are connected in parallel between the power supply voltage Vcc terminal and the signal line 68, and the gate of the P-channel transistor 58 is connected to the signal line 68. N-channel transistors 60 and 6 are connected between the signal line 68 and the reference potential terminal.
Two drain-source paths are connected in series. N
The gate of the channel transistor 60 is connected to the reference voltage Vre
f (for example, about 2 V). The control signal φ3 is input to each gate of the P-channel transistor 56 and the N-channel transistor 62, and the gate of the current source transistor 54 is connected to the signal line 68.

In the constant current circuit 33 having such a configuration, in the program verifying operation and the reading operation, the bit lines BLk-1 to BLk are connected by the current source transistor 54 connected to the reference portion 64 enabled according to the control signal φ3.
-256 provides a constant current (eg, about 4 μA).

The program judging circuit 24 shown in FIG. 1 judges whether or not all of the programmed memory transistors have a desired threshold voltage in the program verifying operation. The data judging circuit 24 shown in FIG. ~ D
Lk-256 are connected through signal line groups 70 respectively connected thereto.

FIGS. 12 and 13 show circuit examples of the program judging circuit 24. FIG. The circuit shown in FIG. 12 includes a program decision circuit 24 associated with the k-th column block CBk.
Is a representative example of such a circuit.
Each one of the column blocks CB is provided as a peripheral circuit in a one-chip EEPROM. The circuit 236 shown in FIG. 13 includes output signals FP1 to FP1 of the circuit shown in FIG.
This is an AND circuit that outputs an “L” level if any one of the FPs 8 is at the “L” level.

As shown in FIG. 12, the gates of N-channel transistors 212, 214,... It is connected. The current paths of the P-channel transistor 218 and the D-type transistor 220 are connected in series between the power supply voltage Vcc and the signal line 210. P-channel transistor 21
The gate of 8 receives the control signal SUP which is set to the “L” state at the time of the program verification operation, and the gate of the D-type transistor 220 is connected to the signal line 210. These N-channel transistors 212, 214,.
6, the P-channel transistor 218 and the D-type transistor 220 constitute the NOR gate 234. On the other hand, one of the two input terminals of the NOR gate 222 is connected to the signal line 210, and the other receives the control signal / SFP which becomes "L" only at the time of the verification check. The input terminal of the inverter 224 is the NOR gate 2
22 and the output of which is the signal FPk
Becomes

The AND circuit 236 shown in FIG.
It comprises a NAND gate 226 having P1 to FP4 as inputs, a NAND gate 228 having signals FP5 to FP8 as inputs, and a NOR gate 230 receiving each output of these NAND gates 226, 228.

Next, the operation and features of this embodiment (FIGS. 1 to 13) will be described in detail with reference to timing charts shown in FIGS.

Block erase mode

In the block erase mode, the data register and sense amplifier 12, column decoder and selection circuit 1
4, input / output buffer 16, and program determination circuit 24
Are all in the OFF state. More specifically, the column decoder 30 shown in FIG. 3 is reset, and turns off the transfer transistors T1 to T256. Control signal φ
1 to φ5 and the signals on the signal lines DCB and SBL are all maintained in the "L" state, and the data register and the sense amplifier 12 are turned off. The control signal SUP shown in FIG.
Is also turned off. Source line drive circuit 2 shown in FIG.
2 provides an "L" state, that is, a reference potential of 0 V to the common source line CSL by a program control signal PGM in an "H" state.

It is assumed that data stored in the memory transistors M1 to M8 in the memory block BK1 are simultaneously erased, and the operation will be described with reference to the timing chart of FIG.

The period from t1 to t2 is a period during which all the word lines WL1 to WL8 are discharged to the reference potential. During this period, the NAND gate 124 shown in FIG. 6 outputs the “H” level by the control signal BLK in the “L” state, and the D-type transistor 126 is turned ON by the program control signal PGM in the “H” state. State. Therefore, block selection control line BSCi attains the "H" state, that is, 5V. At this time, the charge pump circuit 128 is in a non-operating state. That is, during this period, all the block selection control lines BSC1 to BSC10
24 maintains 5V. On the other hand, during this period, the control signals PVF and PGM are in the “H” state, and the erase control signal ERA is in the “L” state. Therefore, as can be seen from FIG. 7, the output of the NAND gate 156 is “H”. "In the state,
The output of the NAND gate 158 of the three-state logic is in the “L” state. At this time, the verification voltage generation circuit 164, which is a three-state logic inverter, is in a high impedance state. Therefore, the control gate line CGLj is
Through the D-type transistor 176 turned ON, the state becomes “L”, that is, 0V, and all the control gate lines CGL
1 to CGL8 maintain the “L” state. And said 5
The transfer transistors BT1 to BT10 are all turned on by the V block selection control lines BSC1 to BSC1024, and the word lines WL1 to WL8 are all discharged to the reference potential.

The period from t2 to t3 is a period for erasing all the memory cells only in the selected memory block BK1. At t2, the address signals P1, Q1, R1 in the "H" state for selecting the memory block BK1 are input to the row decoder 120, and the output of the row decoder 120 goes to the "L" state.
4 is maintained at the "H" state. That is, the block selection control line BSC1 corresponding to the selected memory block BK1 is at 5 V during the period from t2 to t3. On the other hand, unselected memory blocks BK2 to BK1024
Row decoder 120 associated with address signals Pl, Q
Since at least one of l and Rl is in the "L" state, all output "H" levels. Therefore, the control signal / BLK attains the "H" state at t2, and the NAND
The outputs of the gates 124 all go to the "L" state. As a result, unselected memory blocks BK2 to BK1024
Block selection control lines BSC2 to BSC102 associated with
4 are all 0V. As described above, the transfer transistor array 3 connected to the selected memory block BK1
All the transfer transistors BT1 to BT10 in 4-1 are O
N and the word line WL1 in the memory block BK1.
WL8 receive a reference potential. On the other hand, since the transfer transistor arrays 34-2 to 3-1024 connected to the unselected memory blocks BK2 to BK1024 are all in the OFF state, all the word lines WL related thereto are in the floating state.

Further, at t 2, the erase voltage Vera
(For example, 20 V) is applied to the P-type well region 76 and the N-type well region 74 through the well electrode 114 shown in FIG. The period from t2 to t3 (for example, about 10 ms
During c), the floating gates of all the memory transistors M1 to M8 in the selected memory block BK1 have erase voltages Vera applied to their channel regions, sources and drains, and 0 applied to the control gate.
The holes are accumulated by the FN current generated by the V voltage. Thereby, the memory transistor M1
ＭM8 are all D-type transistors having a threshold voltage of about −3V. That is, all the memory transistors M1 to M8 in the memory block BK1 are binary logic "0".
Is erased.

On the other hand, when the erase voltage Vera is applied to the P-type well region 76 and the N-type well region 74 through the well electrode 114 at t 2, the unselected memory block B
Since the word lines WL in K2 to BK1024 are in a floating state, these word lines WL have almost the well voltage due to the total capacitance coupling between the semiconductor substrate portion, the well portion, the floating gate, the control gate, and the bit line. That is, it is charged to the erase voltage Vera. Therefore, the unselected memory blocks BK2-B
Each of the memory transistors (M1 to M1) is such that the voltage charged in the word line WL in
8) The electric field between the channel region and the control gate is sufficiently reduced.

That is, the inventor of the present invention has proposed that the word line in the unselected memory block is set to the erase voltage V
It has been discovered that if charged to about 80% to 90% of era, the data of the programmed memory transistor in the memory block will not be destroyed or attenuated. Therefore, in the block erasing according to the present example utilizing this, it is not necessary to apply the program prevention voltage from the voltage boosting circuit to the word lines in the unselected memory blocks, so that not only the power consumption is suppressed but also the chip is occupied. Area reduction can also be effectively achieved. That is, according to the present example, the area occupied by the peripheral circuit can be reduced on a chip having a limited size, so that there is an advantage that the range for use in the memory cell array can be further expanded.

Incidentally, in such a block erase operation, the erase voltage Ver applied to the well electrode 114 is
a affects not only the floating word line WL but also the floating bit line BL. That is, the bit line BL is also subjected to the erase voltage Ver by the block erase operation.
It is charged to about a. Therefore, in order to prevent the D-type transistor 40 shown in FIG. 3 from being stressed by the charged voltage, the D-type transistor 38 whose gate receives the power supply voltage Vcc is connected to the bit line B.
It is provided between Lk-1 to BLk-256 and the D-type transistor 40, respectively.

During the block erase operation during the period from t2 to t3,
The first selection line SL1 of the selected memory block BK1 maintains about 4.3 V, and the control signals φ6 and φ7 are set to the “L” state, whereby the N-channel transistors 140 and 144 and the P-channel transistor of FIG. Since 142 is turned off, the second selection line SL2 of the memory block BK1 is in a floating state. Second selection line SL
The floating state of 2 prevents a current from flowing from the well electrode 114 via the second selection line SL2 when one of the second selection transistors ST2 connected to the second selection line SL2 fails.

Table 1 below summarizes the voltage relationship of the main parts of the selected memory block and the non-selected memory block in the block erase operation.

[0068]

[Table 1]

The period from t3 to t5 shown in FIG.
This is a period for discharging the voltage charged in the word line WL and the bit line BL. At t3, the block erase operation is completed, the erase voltage Vera becomes 0 V, the control signals WE and ERA
Becomes "H" state. And between t3 and t4,
The output of the NAND gate 156 shown in FIG. 7 changes to the "H" state due to the control signal DS which changes to the "L" state. Therefore, the output of the 3-state logic NAND gate 158 attains the "L" state in response to the program control signal PGM at the "H" state. That is, during the period from t3 to t4, the control gate lines CGL1 to CGL8 are all "L".
State. Further, the output of the NAND gate 124 shown in FIG. 6 is set to the "H" state by the control signal BLK which is set to the "L" state between t3 and t4. Thereby, the block selection control lines BSC1 to BSC1024 are all 5V
And therefore all of the transfer transistors BT1-
BT10 is turned ON, and all word lines WL1 to WL8 are discharged to 0V. At the same time, the first and second selection lines SL
1, SL2 is also set to 5V.

At t3, the signal line DCB and the control signal φ1
Changes to the "H" state, the erase voltage Vera charged in the bit line BL is discharged via the N-channel transistor 37 shown in FIG. 3, and changes to the "L" state.

On the other hand, at time t4, the control signals BLK and D
S goes to the “H” state, and the control signal Xd goes to the “L” state. As a result, the row decoder 120, which is a NAND gate shown in FIG. 6, outputs "H" level, and the first and second selection gate lines SGLi-1, SGLi-2 and the block selection control line BSCi become 0V.

Program mode

In the EEPROM of this embodiment, data input through the input / output terminal I / O is latched by the latches PBk-1 to PBk-1.
A data loading operation for storing data in the PBk-256 is performed before a program operation.

This data loading operation is performed before t1 shown in FIG. During data loading operation,
The control signals Xd, φ2, φ3, φ4, the program voltage Vpgm, the pass voltage Vpas, the P-type well region 76, the program prevention voltage Vpi, and the signal lines SBL, DCB all maintain the "L" state. Bar W
E, bar PGM, bar SLE, bar BLK, bar DS,
ERA, PVF, SUP, .phi.1, .phi.5, and the clock signal .phi.R are in the "H" state. Further, the control signal Xd is in the “L” state and the control signal BL
Since K, bar ERA, bar SLE, bar WE, and bar PGM are all in the "H" state, as can be seen from FIG. 6, all the block select gate lines BSC1 to BSC1024 are in the "L" state. Thus, the transfer transistor arrays 34-1 to 34-1024 are all turned off. Also, the latch P is supplied by the signal line SBL in the “L” state.
Bk-1 to PBk-256 and bit lines BLk-1 to BLk
Communication with k-256 is prevented. The control signals φ3 and φ4 in the “L” state disable the constant current circuit 33 and the three-state logic inverter 48 shown in FIG. 3, respectively.

An address inputted to an external address input terminal (not shown) is composed of row addresses a8 to a20 and column addresses a0 to a7. The row addresses a8 to a20 are set so that the data of all the bit lines BL are written to the memory cells (M1 to M8) at a time in the program operation performed after the data loading operation, that is, the page program is performed. , To select one of the memory blocks BK and one of the word lines WL during the data loading operation. The column addresses a0 to a7 are address signals having 256 cycles during the data loading operation. The column decoder 30 shown in FIG. 3 performs toggling of the external write enable signal WEx (not shown).
, The transfer transistors T1 to T256 are sequentially turned on in response to the column addresses a0 to a7 of 256 cycles. Further, the input buffer 26 corresponding to each column block CB sequentially outputs data input to the input / output terminal I / O in response to the toggling of the external write enable signal WEx. Therefore, output data from each of these input buffers 26 is sequentially stored in latches PBk-1 to PBk-256 from transmission transistors T1 to T256 which are sequentially turned on, through corresponding N-channel transistors 49.

After such a data loading operation, a program operation (or a write operation) is started. According to this example, the program operation includes the NAND cell unit charging operation. In order to better understand the program operation of this example, for convenience of explanation, the latches PBk-1 to PBk-2 are used in the previous data loading operation.
256 data stored in the memory block B
It is assumed that the memory transistors M4 connected to the word line WL4 in K1 are programmed simultaneously.

The program operation is performed during the period from t1 to t3 after the data loading operation shown in FIG. During this period, the P-type well region 76 and the control signal bar W
E, PGM, φ2, φ3, φ4, φ5, and the signal line DCB are all in the “L” state, and the control signals Xd, BLK, DS, ERA, φ1, and S
BL are all in the "H" state. During this period, the clock signal φR and the program voltage Vpgm (for example, 18
V), a pass voltage Vpas (for example, 10 V), and a program prevention voltage Vpi (for example, 7 V) are supplied. On the other hand, the row addresses a8 to a20 input during the aforementioned data loading operation have already been latched in an address buffer (not shown). The address signals P11, Q1, R1 generated by pre-decoding the address signals A11, A11 to A20, and A20 in the latched address are
The address signal A8 and the bar A8 input to the row decoder 120 shown in FIG.
A10 and A10 are input to a row decoder 154 which is a NAND gate shown in FIG.

At time t1, control signal Xd attains the "H" state, and address signal P for selecting memory block BK1 is set.
l, Ql, and Rl are input to the row decoder 120. Then, the output of row decoder 120 attains an “L” state, and NA
The outputs of the ND gates 124 and 136 go to the “H” state.
Therefore, the first selection gate line SGL1-1 becomes 5V, and the block selection control line BSC1 changes the program voltage Vpg by the pumping operation of the charge pump circuit 128.
m. On the other hand, the second select gate lines SGL1-2
Is boosted to the pass voltage Vpas by the “H” state transmitted through the N-channel transistor 140, the P-channel transistor 142, and the D-type transistor 150 and the pumping operation of the charge pump circuit 152.
At this time, the unselected memory blocks BK2 to BK1
The output of each row decoder 120 associated with H.024 goes to the “H” state, and the output of each NAND gate 124 goes to the “L” state. Therefore, all the block selection control lines BSC2 to BSC1024 which are not selected become 0V.

At time t1, the program control signal PG
Since M is in the “L” state, the common source line CSL receiving the output of the source line driving circuit 22 shown in FIG. 8 is boosted to the program prevention voltage Vpi. That is, when the program control signal PGM goes to the “L” state, the common source line CSL becomes the absolute value (for example, 2 to 3 V) of the threshold voltage of the D-type transistor 206, and the charge pump circuit 208 By the pumping operation, the voltage is increased to the program prevention voltage Vpi.

As described above, in the data loading operation before the program operation, since the address signals A8, A8 to A10, and A10 for selecting the word line WL4 have already been input to the row decoder 154 shown in FIG. The output of row decoder 154 associated with control gate line CGL4 is in the "L" state, while the unselected word line WL1
Row decoder 15 associated with .about.WL3, WL5.about.WL8.
4 is in the "H" state. Therefore, the output of NAND gate 156 associated with selected word line WL4 is at the "H" state, while the unselected word line WL4 is
Is in the "L" state. Then, when a pulse of the clock signal φR is generated at t1, the NAND gate 178 related to the selected word line WL4 outputs a signal corresponding to the clock signal φR,
NOR gate 188 outputs an “L” level, and provides program voltage Vpgm to selected control gate line CGL4. On the other hand, each NOR gate 188 associated with the unselected word line WL outputs a signal corresponding to the clock signal φR, and the unselected control gate lines CGL1 to CGL are output.
3. Provide the pass voltage Vpas on CGL5 to CGL8.

Further, at time t1, the signal line SBL attains the "H" state, whereby the N-channel transistors 44 shown in FIG. 3 are all turned on, and the latches PBk-1 to PBk-
The data stored in 256 corresponds to the corresponding bit line BLk
-1 to BLk-256. In the previous block erase mode, all the memory transistors in the selected memory block BK1 have been erased to the “L” state, that is, the logic “0”. After the block erase mode, in the data loading operation, the latch corresponding to the memory transistor to which "H" level, that is, the logic "1" is written stores the logic "0", and the memory transistor to which the logic "0" is written is stored. The corresponding latch stores a logic "1". For easy explanation, the first column block CB1 (k = 1) of the column blocks CB as shown in FIG.
Connected to the selected word line WL4 in the memory block BK1 in the memory cell, and writes logic "1" only to the memory transistor 240 associated with the bit line BL1-2, and all other connected to the word line WL4. The logic "0" is written in the memory transistor of the above. In this case, in the data loading operation, only the latches PB1-2 already store the logic "0", that is, the "L" level, and the remaining latches PB1-1 and PB
1-3 to PB1-256 all store logic "1", that is, "H" level. Therefore, after t1, N
When the channel transistor 44 is turned on, only the bit line BL1-2 becomes the "L" state, that is, 0V, and the remaining bit lines BL1-1, BL1-3 to BL1-
256 start to be charged to the "H" state, that is, 5V.

As a result, during the period from t1 to t2 shown in FIG. 15, the transfer transistor array 3 shown in FIG.
4-1 is in an ON state, the first selection line SL1 in the selected memory block BK1 is 5V, and the second selection line SL2 is
Is Vpas (for example, 10 V), and the selected word line WL4 is V
pgm (eg, 18 V), unselected word line WL1
WL3 and WL5 to WL8 are set to Vpas. During this period, the common source line CSL is connected to the program prevention voltage Vpi.
(For example, 7 V), the second selection transistor ST2 and the memory transistors M1 to M8 in the selected memory block BK1 all become conductive. And
The first selection transistors 242 (ST1) connected to the bit lines BL1-2 in the memory block BK1 are turned on, and all the remaining first selection transistors ST1 are turned off. Thereby, NAND cell unit N including memory transistor 240 for writing logic "1"
The current paths of the memory transistors M1 to M8 in U are connected to the bit lines BL1-2, and the junction capacitors of the channels and the sources and drains of the memory transistors M1 to M8 are discharged to 0V. On the other hand, since the first select transistor ST1 associated with the memory transistors M1 to M8 for writing logic "0" is non-conductive, the channels and the source and drain of the memory transistors M1 to M8 in the NAND cell unit NU associated therewith are non-conductive. Each junction capacitor is charged to the program prevention voltage Vpi. Therefore, the period from t1 to t2 (for example, about 1
00 μsec), the NAND cell unit NU relating to the memory transistor programmed to logic “0”
Is charged.

The period from t2 to t3 (for example, 2 msec) shown in FIG. 15 is a period in which the program is substantially performed. At t2, the control signal SLE changes to the "H" state, and as can be seen from FIG. 11, the control signal φ6 changes from the "H" state to the "L" state, and the control signal φ7 changes from the "L" state to the "H" state. become. Thereby, the N-channel transistor 144 shown in FIG. 6 is turned ON, and all the second selection gate lines SGLi-2 are connected to the reference potential of 0 V. Therefore, all the second selection transistors ST2 in the selected memory block BK1 are connected. Becomes OFF. During this period, 1 is applied to the word line WL4 in the selected memory block BK1.
An 8 V program voltage Vpgm is applied.
Since the channel, drain and source of the memory transistor 240 shown in FIG. 4 are charged to 0 V, electrons are accumulated in the floating gate of the memory transistor 240 by an FN current due to a control gate-substrate voltage of 18 V. 240 is an enhancement type MOS transistor having a threshold voltage of about 0.8V. On the other hand, the memory transistors M4 other than the memory transistor 240 connected to the word line WL4
Source and drain junction capacitors and their channels are charged to the program prevention voltage Vpi,
Since the control gate-substrate voltage is as low as 11 V, injection of electrons into the floating gates of these transistors M4 is prevented, and the transistors M4 remain as depletion type transistors storing logic "0". That is, each NAND cell unit NU associated with the memory transistor programmed to the “L” state, that is, the logic “0”,
The connection to the corresponding bit line BL is cut off by charging the cell unit, thereby preventing writing during the program operation.

Table 2 below summarizes the voltage relationships of the main parts during the NAND cell unit charging period and the programming period described above.

[0085]

[Table 2]

In the period from t3 to t5 (for example, 500 nsec) shown in FIG. 15, the word line WL and the bit line BL
Is a period in which each boosted voltage is discharged. At t3, the control signals / WE, / PGM and the signal line DCB are set to the "H" state, and the control signals / BLK, / DS and the voltage Vpg are set.
m, Vpas, Vpi, and the signal line SBL enter the “L” state. The clock signal .phi.R stops generating pulses at t3 and maintains the "H" state. During this period, the control signal φ1 maintains the “H” state, and the control signals φ2 and φ3 maintain the “L” state. Therefore, the source line driving circuit 22 shown in FIG. 8 outputs the reference potential to the common source line CSL. Further, as can be seen from FIG. 7, the control gate line C
GL1 to CGL8 all become 0 V, and as can be seen from FIG. 6, the block selection control lines BSC1 to BSC1024
Are all 5V, so the boosted voltage of the word line WL is discharged to 0V. At t4, the control signal bar Xd
Becomes "L" state, and control signals / BLK and / DS go to "H" state. Accordingly, during the period from t4 to t5, the block selection control line BSCi and the first and second selection gate lines SGLi-1 and SGLi-2 all become 0V. On the other hand, since the signal line DCB and the control signal φ1 are in the “H” state during the period from t3 to t5, the boosted voltage of the bit line BL is discharged to 0 V through the N-channel transistor 37. Thereafter, at t5, the control signal φ1 goes to the "L" state.

Program verification mode

The program verification mode is performed immediately after the program mode. The program verify operation according to the present invention is similar to the read operation. The difference from the read operation is that the voltage applied to the selected word line is the minimum threshold voltage in the enhancement mode of the memory transistor. This minimum threshold voltage is called a program verification voltage, and the program verification voltage in the present embodiment is 0.8V.

The program verifying operation is performed immediately after t5 shown in FIG. 15, and each signal timing has a waveform between t2 and t4 shown in FIG. At the beginning of the program verification operation, that is, at time t5 shown in FIG. 15 or at time t2 shown in FIG.
And the signal line DCB is in the “L” state. During the program verification operation, the control signals WE, PGM, SLE, Xd, BLK, DS, ER
A, φ3, φ4, and the clock signal φR maintain the "H" state, and the voltages Vpgm, Vpas, Vpi, and the signal line SB are maintained.
L, DCB, control signals φ1, φ5, PVF, and SUP all maintain the "L" state.

The memory transistor 24 in the selected memory block BK1 in the first column block CB1 (FIG. 2) in which the logic "1" has been written in the program mode described above.
Assume that a program verify operation is performed to determine if the desired minimum threshold voltage has been written to zero.

After the program operation, when a command for performing the program verification is input from the microprocessor to the EEPROM through the input / output terminal I / O (or another terminal), or the program verification operation is automatically performed after the program operation. When the data is stored in the latches PBk-1 to PBk-256 in the program operation, the data is inherited by the program verify operation without being reset. Therefore, at the beginning of the program verify operation, the latch PB1-2 stores data "0", and the remaining latches PB1-1, PB1-3 to PB1-256 all store data "1". .

When control signal Xd attains an "H" state at t2 shown in FIG. 16, row decoder 120 shown in FIG.
Address signals Pl and Q specifying memory block BK1
1 and outputs an “L” state in response to Rl. Then, since the control signal φ6 is in the “H” state and the control signal φ7 is in the “L” state, the first and second selection lines SGL1-1 and SGL1-2 and the block selection control line BSC1 are all set to the “H” state of 5V. Become.

Further, at time t2, control signal PVF attains the "L" state, and address signals A8 / A8 to A10 / A10 designating word line WL4 are input to row decoder 154 shown in FIG. The NAND gate 158 has a high impedance, and the verification voltage generation circuit 164 provides a verification voltage of 0.8 V to the control gate line CGL4. At this time, the unselected word lines WL1 to WL3,
Each row decoder 154 associated with WL5 to WL8 is "H".
The state is output, the verification voltage generation circuit 164 becomes high impedance, and the NAND gate 158 outputs the “H” state. Thereby, the control gate lines CGL1 to CGL
3. CGL5 to CGL8 have a read voltage of 5V. On the other hand, since the program control signal PGM is in the "H" state at t2, the source line drive circuit 22 shown in FIG. 8 provides a reference potential to the common selection line CSL.

As a result, the transmission transistor array 34-1 shown in FIG. 2 is turned ON, and the first and second selection lines SL1 and SL2 in the selected memory block BK1 and the unselected word lines WL1 to WL3 and WL5 are selected. To WL8 are all 5V, and the selected word line WL4 is 0.8V. Therefore, the first and second selection lines SL1, SL2,
And unselected word lines WL1 to WL3, WL5 to W
The transistor connected to L8 is turned on. At t2, the control signal .phi.3 becomes "H" and the constant current circuit 33 shown in FIG. 3 is enabled, so that the current source transistor 54 supplies a constant current (for example, 4 .mu.A) to
It is supplied to the bit line BL through the transistors 40 and 38.

At this time, the programming of the memory transistor 240 fails, that is, the memory transistor 2
Assuming that the threshold voltage of 40 is lower than the program verification voltage of 0.8 V, the memory transistor 240 becomes conductive, and the bit lines BL1-2 connected to this transistor 240 become the reference potential, that is, 0V. Bit lines BL1-1 and BL1 other than the bit lines BL1-2
Block BK connected to -3 to BL1-256
Since all the transistors in the NAND cell unit NU in 1 are ON, the bit lines BL other than the bit lines BL1-2 also become 0V. The period in which the word lines WL1 to WL8 and the bit line BL are set to a predetermined voltage by such a method is a period from t2 to t3 shown in FIG. 16, for example, a period of about 2 μsec.

The period from t3 to t4 (for example, about 500 nsec) shown in FIG. 16 is a verification sensing period. At time t3, the control signal .phi.2 becomes "H", and the N-channel transistor 52 shown in FIG. 3 is turned on. The reference potential on the bit line BL1-2 turns off the N-channel transistor 50 whose gate is connected to the bit line BL1-2 through the D-type transistors 38 and 40, and the data in the latch PB1-2 is logic "0". Will be maintained. Similarly, other bit lines BL
Are also at the reference potential, the N-channel transistor 50 associated with these bit lines BL is also turned off, and the latch P
Latches PB1-1 other than B1-2, PB1-3 to PB1
-256 data is maintained at the previous logic "1". In this manner, the latch PBk-1 is operated by the verification sensing operation.
The verification sensing data stored in ~ PBk-256 is ON
1 through the inverter 48 and the signal line group 70 in the state shown in FIG.
, N-channel transistors 212, 214,.
216 to each gate.

Therefore, the verification sensing data of logic "0" (or "L" state) stored in the latches PB1-2 is as follows:
NOR gate 234 connected to first column block CB1
The gate of the N-channel transistor 214 (FIG. 12) is inverted and provided in the “H” state. The N-channel transistor 214 is turned on, and the signal line 210 is discharged to the reference potential. At this time, the control signal bar SFP
Is a signal which becomes “L” only at the time of verification check,
Signal FP1 attains an "L" state. On the other hand, the latches PBk-1 to PBk-256 in the other column blocks CB2 to CB8
Store the "H" state, so that each column block C
The N-channel transistors 212, 214,... 216 of the NOR gate 234 corresponding to B are turned off. Therefore, each signal line 210 is connected to the P-channel transistor 2
18. The "H" state is maintained by the D-type transistor 220, and the signals FP2 to FP8 are all in the "H" state. Thereby, the output line 232 of the AND circuit 236 shown in FIG.
Changes from the “H” state to the “L” state. This indicates that the memory transistor 240 was not correctly programmed. That is, the memory transistor 240
Have not reached the set minimum threshold voltage. Then, the program discrimination signal PDS on the output line 232 is sent to a timing circuit (not shown), and this timing circuit responds to the program discrimination signal PDS in the “L” state to execute reprogramming in FIG. A timing signal between t1 and t5 is generated. That is, the reprogram operation is automatically performed.

Such a reprogram operation can be automatically performed by an internal circuit of the EEPROM without requiring control of the microprocessor or a request for reloading data. The program discrimination signal PDS may be input through one of the input / output terminals of the EEPROM to control the reprogram operation.

When the memory transistor 240 reaches a desired threshold voltage (for example, 0.8 V) by the repetitive program operation as described above, the memory transistor 2 is subjected to a program verification operation performed after the program operation.
40 becomes non-conductive. Therefore, bit line BL1
-2 is charged to about 2-3 V by a constant current supplied through the current source transistor 54, and the bit line BL1-
The N-channel transistor 50 connected to 2 turns ON. That is, the verification sensing data of the latches PB1-2 is changed from logic "0" to logic "1". As described above, since the other latches store the logic "1" verification sensing data, all the latches PBk-1 to PBk-256 store the logic "1" verification sensing data. That is, assuming that all the memory transistors M1 to M8 are correctly programmed in the page program operation, the verification sensing data stored in the latches PBk-1 to PBk-256 are all set to logic "1". As a result, all the N-channel transistors 212, 214,..., 216 constituting the NOR gate 234 shown in FIG.
Signals FP1 to FP8 all become "H" in response to control signal SFP which becomes "L" at the time of the program verification check. Then, an AND circuit 236 shown in FIG. 13 outputs a program discrimination signal PDS in the “H” state.
This indicates that the program operation was successful.

It is assumed that some of the memory transistors (M1 to M8) that are to be programmed to logic "1" through programming and subsequent program verification succeed in programming, and others fail in programming. At this time,
The latch (PBk) corresponding to the successful memory transistor
-1 to PBk-256) is changed from logic "0" to logic "1", and the data in the latch corresponding to the failed memory transistor maintains logic "0". If successful, the data in the latch is stored at a logic "1", so that in subsequent reprogram operations, their corresponding bit lines BL are charged to 5V. The first selection line SL1 selected by the reprogram operation as in the above-described program operation is at 5V, and the junction and channel of the source and drain of the memory transistor constituting each NAND cell unit NU are 7V. , The selected first selection transistor ST1 connected to the charged bit line BL is turned off. In other words, the memory transistor that has been successfully programmed by the reprogram operation is
The program is prevented by the charged program prevention voltage Vpi. Therefore, excessive writing to a cell to which writing has already been successfully performed is prevented, and as a result, the threshold voltage of the enhancement type is made uniform, and cell deterioration due to unnecessary application of a tunnel electric field can be prevented. On the other hand, in the case of a memory transistor that has failed in programming, the corresponding latch stores data of logic "0", so that reprogramming is performed only on those data. By such repetitive operation, when all the memory transistors programmed to the logic “1” for the selected word line WL have been successfully programmed, the program determination signal PDS is output in the “H” state in the program verification, The reprogram operation ends.

The circuit according to the present invention used in the program verification is an EE having a NOR type memory cell array.
PROM is applicable.

The program verification technique has various advantages as follows. First, the program verification operation can be automatically performed by the internal circuit of the chip without being controlled by the microprocessor outside the chip. Second, the data register can be commonly used as a data latch in a data loading operation, as a verification sensing circuit in a program verification operation, and as a sense amplifier in a read operation described later, so that peripheral circuits can be simplified. become. Third, the threshold voltage of the memory transistor to be programmed can be reduced within a narrow range equal to or higher than a set minimum threshold voltage, and over-programming can be prevented. A threshold voltage with little variation can be obtained by performing the program operation in a shorter time. Further, the memory transistor that has been successfully programmed is automatically prohibited from being programmed thereafter by changing the data of the corresponding latch, so that over-programming can be prevented.

Read mode

FIG. 16 is a timing chart of the read operation of this embodiment. During the period from t1 to t2 shown in FIG. 16, the word lines WL1 to WL8 and all the bit lines BLk-
1 to BLk-256 are discharged to the reference potential, and the latch PBk is discharged.
This is a reset period in which data of logic "0" is stored in -1 to PBk-256. During this period, since the control signal φ1 and the signal lines SBL and DCB are in the "H" state, the bit lines BLk-1 to BLk-256 are discharged to the reference potential through the N-channel transistor 37, and the latches PBk-1 to Pkk-1.
PBk-256 is reset to logic "0". At this time, the timings of the control signals WE, PGM, SLE, Xd, BLK, DS, ERA, the clock signal φR, and the voltages Vpgm, Vpas, Vpi are between t3 and t5 in FIG. Same as timing. The control signals PVF and SUP are always in the “H” state in all operations except the program verification operation.

The period from t2 to t4 shown in FIG.
Sense data read from a memory cell, and latch
This is a period for storing the sensed data in k-1 to PBk-256. During this period, the control signals WE, P
GM, bar SLE, bar Xd, bar BLK, bar DS,
The signals ERA, φ3, φ4, and the clock signal φR maintain the "H" state, and the voltages Vpgm, Vpas, Vp
i, the signal lines SBL and DCB, and the control signals φ1 and φ5 all maintain the “L” state.

In the aforementioned program mode, the word line WL of the page-programmed memory block BK1 is set.
The description will be made on the assumption that the read operation is performed from the transistor M4 connected to the transistor M4.

The operation between t2 and t3 is performed in a manner similar to the program verification operation described above. In brief, the block selection control circuit 18 shown in FIG. 6 associated with the selected memory block BK1 responds to the address signals Pl, Ql, Rl specifying the memory block BK1 in response to the first and second selections. Gate lines SGL1-1, SGL1
-2 and the block selection control line BSC1 are maintained at 5V.
Since the control signal PVF is in the “H” state, the verification voltage generation circuit 164 shown in FIG.
The 3-state logic NAND gate 158 is enabled. Therefore, the selected word line WL4
The control gate line CGL4 corresponding to the address signal A8 / bar A8 to A10 / bar A10 for designating the word line WL4.
To 0V in response to On the other hand, the unselected word line W
The control gate lines CGL1 to CGL3 and CGL5 to CGL8 corresponding to L1 to WL3 and WL5 to WL8 are set to 5V. Then, the source line driving circuit 22 shown in FIG. 8 outputs 0 V to the common source line CSL. That is, the transmission transistor array 34-1 shown in FIG. 2 is turned ON, and the first and second selection lines SL1 and SL2 in the memory block BK1 and the unselected word lines WL1 to WL3 and WL5 to WL8.
Is set to 5V, and the selected word line WL4 is set to 0V.

When the control signal φ3 goes high at t2, the constant current circuit 33 (FIG. 3) is enabled. As a result, the current source transistor 54 is connected to the bit line BLk- from the connection point 36 through the D-type transistors 40 and 38.
A current of about 4 μA is supplied to 1 to BLk-256. Since only the memory transistor 240 connected to the word line WL4 in the memory block BK1 is programmed to logic "1", it is inactive and the bit lines BL1-2 are charged to about 2-3V and the other bit lines are charged. BL becomes 0V. When the control signal φ2 changes to the “H” state at t3 in FIG. 16, all the N-channel transistors 52 in FIG. 3 are turned on. Then, of the N-channel transistor group 50,
Only those associated with bit lines BL1-2 conduct, and latches PB1-2 sense and store a logic "1". On the other hand, other latches PB1-1, PB1-3 to PB1-256
Since the corresponding N-channel transistor 50 is off, the logic "0" based on the previous reset operation is continuously stored. That is, page reading is performed.

The data stored in the latches PBk-1 to PBk-256 is transferred via the inverter 48 to the transfer transistor T1 which is sequentially turned on in response to the 256-cycle column address and toggling of the read enable signal WEx. Through T256 and the output buffer 28, the input / output terminals I / O1 to I / O1 corresponding to the respective column blocks CB1 to CB8.
The data is output to the I / O 8 in byte (8 bit) units.

Other Embodiments (see FIGS. 17 to 21)

The EEPROM of the above embodiment described with reference to FIGS. 1 to 16 has a memory cell array 10 having 1024 memory blocks BK each constituted by NAND cell units NU arranged in the same row. In order to charge the NAND cell unit NU with the program prevention voltage Vpi, there is provided a source line drive circuit 22 for generating the program prevention voltage Vpi substantially before the program or reprogram operation. However, the present invention is not limited to the above embodiment. For example, the memory cell array used in the present invention can be configured by a memory block having a shared word line as described later. Further, a capacitive coupling method from a control gate can be applied without using the source line driving circuit 22 for charging the NAND cell unit with the program prevention voltage. Such another embodiment will be described with reference to FIGS.

FIG. 17 shows shared word lines WL1 to WL8.
1 shows a circuit example of a memory cell array 10 constituted by a memory block SBK having the following. As a peripheral circuit of the memory cell array 10 shown in FIG. 17, the same circuit as that of the circuit example of the previous embodiment shown in FIG. 3 is used.

To avoid complicating the drawing, FIG.
Only the arrangement of memory cells associated with the k-th column block CBk in the i-th memory block SBKi and only the shared word lines are shown. The memory cell array 10 having 16-megabit memory cells shown in FIG. 17 has the same configuration as the memory cell array 10 shown in FIG. 2 except for the shared word line WL.

Each memory block SBKi (i = 1, 2,
, 512) are two sub memory blocks, that is, an upper memory block (first sub memory block) U
SBKi and a lower memory block (second sub-memory block) LSBKi. The upper and lower memory blocks USBKi and LSBKi are substantially the same as the memory blocks BK1 and BK2 shown in FIG. 2, respectively. However, the word lines WL1 to WL8 in the upper memory block USBKi are connected to the lower memory block LSB.
It is connected to word lines WL1 to WL8 in Ki. That is, the upper memory block USBKi and the lower memory block LSBKi are connected to the word lines WL1 to WL8.
Sharing.

Word lines WL1 to WL8 are connected to control gate lines C through current paths of transfer transistors BT2 to BT9.
They are connected to GL1 to CGL8, respectively. Further, the first upper selection line USL1 and the first lower selection line LSL1 are connected to the upper and lower selection gate lines USGLi and LSGLi through the current paths of the transfer transistors BT1 and BT11, respectively. Further, the second upper selection line USL2 and the second lower selection line LSL2 are connected to the transfer transistor BT1.
0, BT12 are connected to upper and lower ground selection lines UGSL, LGSL, respectively, through current paths. Each source of the second upper select transistor UST2 and the second lower select transistor LST2 is connected to a common source line CSL. This common source line CSL is at a reference potential, that is, grounded. Each drain of the first upper select transistor UST1 and the first lower select transistor LST1 is
Each is connected to a corresponding bit line BL.

The control gate lines CGL1 to CGL8 are
Is connected to the control gate drive circuit 20 as shown in FIG. The upper and lower select gate lines USGLi and LSGLi are shown in FIG.
8 is connected to the block selection control circuit 318 shown in FIG. Each block selection control circuit 318 has a function of selecting one of the upper and lower memory blocks USBKi and LSBKi in the memory block SBKi selected by specifying an address according to each operation mode. A block selection control circuit 318 corresponding to each of the memory blocks SBKi is provided in the EEPROM. As described above, since each block selection control circuit 318 controls one memory block SBKi composed of the upper and lower memory blocks USBKi and LSBKi, two memory blocks are substantially one. The configuration can be such that one block selection control circuit 318 is shared. According to such a configuration, the area occupied by the peripheral circuit can be reduced, so that the area of the memory cell array on a substrate having a limited size can be relatively increased, and thus the memory capacity can be increased. become able to.

The upper ground selection line UGSL and the lower ground selection line LGSL are connected to a ground line drive circuit 320 shown in FIG. The ground line drive circuit 320 is connected to upper and lower ground selection lines UGSL, LGSL in the memory block SBKi.
Connected to both. Then, the ground line driving circuit 320
Provides an appropriate voltage to the upper and lower ground selection lines UGSL, LGSL according to the respective operation modes.

The ith memory block S shown in FIG.
A configuration example of the block selection control circuit 318 that controls BKi will be described. The decoder 322 outputs the address signals Pl, Q
1 and Rl and a control signal Xd are input. These address signals Pl, Ql, Rl are addresses obtained by pre-decoding the address signals A12 / A12-A20 / A20 in the row address signals A11 / A11-A20 / A20 from an address buffer (not shown). Signal. A row address signal A11 / bar A11 from the address buffer is input to a timing circuit (not shown), and a control signal A11U for selecting the upper memory block USBKi or the lower memory block LSBKi according to each operation mode.
Bar A11U, A11l, Bar A11l, A11j, Bar A11j
Used to generate The logical state of this control signal for the operation mode is as shown in Table 3 below. still,
“H” indicates a 5V “H” state, and “L” indicates a 0V “L” state.

[0119]

[Table 3]

The output of the decoder 322 becomes one input of the NAND gate 324 and the input of the inverter 326. The other input of NAND gate 324 is used as erase control signal ERA. And the NAND gate 32
The output of 4 is sent from the CMOS transmission gate 328 composed of the N-channel transistor 350 and the P-channel transistor 352 to the upper select gate line USGLi through the current path of the D-type transistor 330. CMO
A current path of the N-channel transistor 332 is connected between a connection point 358 between the S transmission gate 328 and the D-type transistor 330 and a reference potential terminal. These N
Control signals A11U, A11j, A11U, and WEm are input to the gates of the channel transistors 350 and 332, the P-channel transistor 352, and the D-type transistor 330, respectively. The control signal bar WE
m is in the “L” state only in the block erase operation, and is in the “H” state in the other operations.

The output of NAND gate 324 is N
The signal is sent from the CMOS transmission gate 334 including the channel transistor 354 and the P-channel transistor 356 to the lower select gate line LSGLi through the current path of the D-type transistor 336. A connection point 360 between the CMOS transmission gate 334 and the D-type transistor 336
Between the N-channel transistor 33 and the reference potential end.
Eight current paths are connected. Then, N-channel transistors 354 and 338 and P-channel transistor 3
The control signals A11l, A11j, A11l, and WEm are input to the gate of the transistor 56 and the gate of the D-type transistor 336, respectively.

The output of the inverter 326 is connected to the current path of the D-type transistor 340 and the N-channel transistor 342 and the D-type transistor 344 connected in parallel.
And to the block selection control line BSCi. The gate of the D-type transistor 340 is connected to the decoder 3
22 and a D-type transistor 34
4 and each gate of the N-channel transistor 342 receive the power supply voltage Vcc (for example, 5 V). NOR gate 346 receives clock signal φR at one input terminal and receives the output of decoder 322 at the other input terminal. A charge pump circuit 348 is provided between the output terminal of the NOR gate 346 and the block selection control line BSCi.

When an address for selecting the memory block SBKi is input to the block selection control circuit 318, the block selection control line BSCi becomes about 4.3 V in the erase, program verification, and read modes, and the block selection control line BSCi in the program mode. Is the program voltage Vp of 18V
gm. On the other hand, the unselected memory block SBK
The block selection control line BSC connected to each of the block selection control circuits 318 associated with と becomes 0 V in those modes.

If the memory block SBKi is specified by an address and the address signal A11 is in the "H" state,
The upper select gate line USGLi is 5 V and the lower select gate line LSGLi is in program, program verify, and read mode.
Becomes 0 V when the N-channel transistor 338 is turned on. If the memory block SBKi is specified by an address and the address signal A11 is in the “L” state, the lower select gate line LSGLi is set to 5 V and the upper select gate line USGLi is set to the N-channel transistor 332 in the program, program verify, and read modes. It becomes 0V by ON. Further, in the block erase mode, the upper and lower select gate lines USGLi and LSGLi are all in a floating state of about 2-3V.

As shown in FIG. 19, the ground line driving circuit 32
0 indicates inverters 362, 364, 366, 368, 3
70, 372 and 374 and NOR gates 376 and 378. In the program mode, the ground line drive circuit 320 operates in the upper and lower ground selection lines UGSL and LG.
0V is output to SL. When the upper memory block USBKi is selected in the read mode and the program verification mode, the upper ground selection line UGSL is set to the “H” state, that is, 5V, and the lower ground selection line LGSL is set to 0V. Conversely, when the lower memory block LSBKi is selected in the read mode and the program verification mode, the lower ground selection line L
GSL is set to 5V, and the upper ground selection line UGSL is set to 0V. On the other hand, in the block erase mode, the upper and lower ground selection lines UGSL and LGSL are set to 5V.

The operation of this embodiment is different from the previous embodiment in that the operation of selecting the upper and lower memory blocks USBKi and the operation of charging the NAND cell unit by the capacitive coupling technique in the program operation are different from those of the previous embodiment. Is almost the same as in the previous embodiment. Therefore, description will be made with emphasis on different parts, and duplicate description will be appropriately omitted.

FIG. 20 is a timing chart in the block erase mode. The period from t1 to t2 is a period during which all word lines in the memory cell array 10 are discharged to 0V. During this period, the control gate lines CGL1 to CGL
8 is 0 V as described in connection with FIG. During this period, the control signal / BLK maintains the "L" state, and the predecoder (not shown) responds to the "L" state of the control signal / BLK to set the address signal to the "H" state. Generates Pl, Ql, Rl. Thereby,
The output of the decoder 322 shown in FIG. 18 is in the “L” state. Therefore, block selection control lines BSC1 to BSC
All the transmission transistors 512 have a voltage of about 4.3 V, the transmission transistors BT2 to BT9 in the transmission transistor arrays 34-1 to 34-512 shown in FIG. 17 are all turned on, and all the word lines WL1 to WL8 are grounded.

The period from t2 to t3 shown in FIG.
This is a period during which the selected memory block SBKi is erased. During this period, the control gate lines CGL1 to CGL8 are
0V is maintained as in the period from t1 to t2. The block selection control circuit 318 associated with the selected memory block SBKi outputs the selected block selection control line BS
Provide about 4.3V to Ci. On the other hand, the block selection control circuit 31 associated with the unselected memory block SBK
8 outputs 0 V to the unselected block selection control line BSC. Then, at t2, the upper and lower memory blocks USBKi, L in the selected memory block SBKi are set.
All word lines WL of SBKi are at 0 V, and all word lines WL in unselected memory blocks SBK are in a floating state. At this time, at time t2, the erase voltage Vera of 20 V is applied to the well electrode 114 shown in FIG. Memory block SB
Erasure of all the memory transistors M1 to M8 in K is prevented. On the other hand, between t2 and t3, each of the memory transistors M1-M in the selected memory block SBKi is
8 is changed to a D-type transistor having a threshold voltage of about -2 to -3 V by an erase voltage applied between the channel and the control gate. That is, the “L” state (or data “0”) is stored.

Further, during the block erase period from t2 to t3, the selected block selection control line BSCi
Is about 4.3V, upper and lower select gate lines USGLi, L
SGLi is about 2-3V, upper and lower ground selection line UGS
Since L and LGSL are set to 5V, the first upper and lower selection lines USL related to the selected memory block SBKi are set.
1, LSL1 is about 2-3V, and the second upper and lower select lines USL associated with the selected memory block SBKi.
2 and LSL2 are both in a floating state. Therefore, these second upper and lower selection lines USL2, LSL2
Upper and lower select transistors UST connected to
2 and LST2, the second upper and lower select lines USL2, L
Leakage current through SL2 is prevented.

Table 4 below summarizes the voltage relationship of the main parts in the above-described block erase operation.

[0131]

[Table 4]

The period from t3 to t4 shown in FIG.
This is a period during which the word lines WL in the unselected memory blocks SBK are discharged to 0V. As described in connection with FIG. 7, all of the control gate lines CGL1 to CGL8 maintain 0 V by the control signal / DS in the "L" state. During this period, as described above, the control signal / BLK in the “L” state
As a result, all the block selection control lines BSC1 to BSC5
12 is maintained at about 4.3V, and all word lines WL
Discharged to V. Then, during the period from t4 to t5, "L"
The upper and lower select gate lines USGLi and LSGLi are all maintained at 0 V by the control signal Xd in the state. On the other hand, during the period from t2 to t5, the signal line D in the "H" state
The bit line BL is discharged to 0 V by CB.

FIG. 21 is a timing chart in the program mode in this embodiment. The data loading operation is performed before t1 shown in FIG. This data loading operation is performed in the same manner as the data loading operation described in the previous embodiment with reference to FIG.

The period from t1 to t2 shown in FIG.
This is a period for writing data to the selected memory transistors (M1 to M8). As described in the data loading operation of the previous embodiment, the bit line BL corresponding to the memory transistor to which the logic "1" is written is in the "L" state, that is, 0V, and the memory to which the logic "0" is written. The bit line BL corresponding to the transistor is in the “H” state, that is, at 5V. As already explained in connection with FIG.
After one, the selected control gate lines CGL become the program voltage Vpgm (for example, 18 V), and all the unselected control gate lines CGL become the pass voltage Vpas (for example, 10 V).
V). That is, the fourth control gate line CGL4
Is specified by the address, the control gate line CGL4 becomes the program voltage Vpgm, and the control gate lines CGL1 to CGL3 and CGL5 to CGL8 all become the pass voltage Vpas.

The third memory block SBK3 is specified by an address, and the address signal A11 is set to "H".
Assuming the state, the corresponding decoder 32 shown in FIG.
2 goes to the "L" state and the block selection control line BS
C3 becomes the program voltage Vpgm after t1. Therefore, the transfer transistor array 34-3 (FIG. 17) is in the ON state. At this time, the upper selection gate line USG
L3 becomes 5V, and the lower select gate line LSGL3 becomes 0V. On the other hand, the ground line driving circuit 320 shown in FIG.
In the period from t2 to t2, the upper and lower ground selection lines UGS
0V is provided to L and LGSL. Thereby the upper part,
The second upper and lower select transistors UST2 and LST2 in the lower memory blocks USBBK3 and LSBK3 are all O
It becomes FF. Further, the first lower selection line LSL1 in the lower memory block LSBK3 is connected to the transmission transistor BT1.
1 becomes 0V through the first lower selection transistor LS
T1 is all turned off. On the other hand, the first upper selection line USL1 in the upper memory block USBK3 becomes 5 V through the transfer transistor BT1.

Table 5 below summarizes the voltage relationship of the main parts in the above program operation.

[0137]

[Table 5]

During program operation, word lines WL1 to WL
8, the NAND cell unit NU of the upper and lower memory blocks USBK3 and LSBK3
Charging occurs. Therefore, the first upper selection line USL1
Is 5V and is in an "L" state, that is, a bit line BL associated with a memory transistor to which data of logic "0" is written.
Is a 5V, "H" state, that is, the bit line BL associated with the memory transistor to which the data of logic "1" is written is 0V, so the upper memory block connected to the memory transistor to which the logic "1" is written The first upper select transistor UST1 in USBK3 is turned on,
The first upper select transistor UST1 in the upper memory block USBK3 connected to the memory transistor to which the logic "0" is written is turned off. Then, the source, drain and channel of the memory transistors M1 to M8 in the NAND cell unit NU in the upper memory block USBK3 having the memory transistor having the logic "1" become 0V, and the upper memory having the memory transistor having the logic "0" N in block USBK3
AND cell unit NU is charged to a high voltage. Therefore, during the program period from t1 to t2, the floating gate of the memory transistor M5 connected to the upper word line WL4 and having a logic "1"
The electrons are accumulated by the FN current, and are converted into an enhancement type transistor having a threshold voltage of about 0.8V. That is, data of logic "1" is stored. On the other hand, since the junction capacitor of the channel and the source and the drain of the memory transistor which becomes logic "0" is charged to a high voltage, programming of these memory transistors is prevented.

At this time, the first lower select line LSL1 and the second lower select line LSL2 of the unselected lower memory block LSBK3 are at 0V, whereby the first
The first connected to the second lower selection lines LSL1 and LSL2,
The second lower select transistors LST1 and LST2 are all O
The state becomes FF. Therefore, the lower memory block L
The junction capacitors of the channels and the sources and drains of the memory transistors M1 to M8 in the NAND cell unit NU in the SBK3 are also charged to a high voltage, thereby preventing programming.

At time t2 shown in FIG. 21, the program operation ends, and the generation of the pulse of clock signal φR is stopped.
The charge pump circuit 348 is disabled, and the block selection control line BSC3 drops to 5V. And t
During the period from 2 to t3, the control signal D in the "L" state is
S controls the control gate lines CGL1 to CGL8 to ground,
Thereby, the word line WL1 in the memory block SBK3 is
ＷＬWL8 are discharged to 0V. Further, during the period from t3 to t4, the block selection control lines BSC1 to BSC51
2 and the upper select gate lines USGL1 to USGL512,
Discharged to 0V.

The program verification operation can be performed from t4 shown in FIG. The program verification operation is almost the same as in the previous embodiment. The difference from the previous embodiment lies in the operation of the block selection control circuit 318 for selecting the upper memory block USBKi or the lower memory block LSBKi in the selected memory block SBKi.

The block selection control circuit 318 shown in FIG.
, The upper memory block USBKi in the memory block SBKi selected by the program verification operation.
Is selected, the selected block selection control line BSC
i becomes about 4.3V, and the upper select gate line USGLi becomes 5V. Then, the ground line driving circuit 32 shown in FIG.
0 provides an “H” state, ie, 5V, to the upper select gate line UGSL, and an “L” state, ie, 0V, to the lower select gate line LGSL. As described in the previous embodiment with reference to FIG. 7, in the program verification operation, the selected control gate line CGL is set to the program verification voltage, for example, 0.8 V
, And the unselected control gate line CGL becomes 5V. Therefore, the block selection control line BSCi of about 4.3 V connected to the transfer transistor array 34-i shown in FIG. 17 is connected to the unselected control gate line CGL.
Is transmitted through the capacitance coupling from the drain to the gate of the transmission transistor BT, so that the voltage is about 7V. This operation is the same in the read operation. That is, the selected word line WL in the upper memory block USBKi is maintained at the verification voltage of 0.8 V, and the unselected word lines WL are maintained at 5 V. In addition, the first and second upper selection lines USL1 and USL2 in the upper memory block USBKi become 5V. Therefore, the second selection transistor US in the upper memory block USBKi
T2 is turned ON, and the NAND cell unit NU in the upper memory block USBKi is connected to the grounded common source line CSL. On the other hand, the lower memory block LSBK
The first and second lower selection lines LSL1 and LSL2 in i are 0 V
, And the lower memory block LSBKi is not selected.

The subsequent program verifying operation and reprogramming operation are the same as those described in the previous embodiment with reference to the timing chart of the period from t2 to t4 shown in FIG.

In the programming and reprogramming technique of this embodiment, the program-preventing memory transistor,
In other words, a program prevention voltage generation circuit connected to each bit line can be dispensed with in order to prevent programming and reprogramming of a cell programmed to logic "0" and a cell successfully programmed to logic "1". Therefore, simplification of the peripheral circuit and reduction of the chip area can be achieved. In addition, during the program and reprogram operations, the program prevention voltage is automatically generated by the capacitive coupling, so that the program and reprogram operations can be performed at high speed. That is, since the self-program prevention technology is used, such an advantage can be obtained.

In the read operation of this embodiment, 0 V is applied to the selected word line WL to which 0.8 V is applied in the above-described program verification operation. The operation of selecting a memory transistor in a read operation is the same as that in the case of the above-described program verification operation. The operation is the same.

FIG. 22A shows the connection relationship between the circuits shown in FIGS. 2 and 3, and FIG. 22B shows the connection relationship between the circuits shown in FIGS. 3 and 17.

[0147]

As described above, according to the present invention,
The EPROM can be designed so as to have a program verification capability which is more improved than before and to have high reliability. Further, the peripheral circuit related to program verification and reading according to the present invention can also be used for a nonvolatile semiconductor memory device having a NOR type memory cell array.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an embodiment of an EEPROM according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a memory cell array shown in FIG.

FIG. 3 is a circuit diagram showing a configuration example of an input / output buffer, a column decoder and a selection circuit, a data register, and a sense amplifier shown in FIG.

FIG. 4 is a plan view showing an example of a layout pattern of a NAND cell unit forming a memory cell array.

FIG. 5 is a sectional view taken along line IV-IV in FIG. 4;

FIG. 6 is a circuit diagram showing a configuration example of a block selection control circuit used for the memory cell array shown in FIG. 2;

FIG. 7 is a circuit diagram showing a configuration example of a control gate drive circuit used for the memory cell array shown in FIG. 2;

8 is a circuit diagram showing a configuration example of a source line driving circuit used for the memory cell array shown in FIG.

FIG. 9 is a circuit diagram showing a configuration example of a three-state logic inverter shown in FIG. 3;

FIG. 10 is a circuit diagram showing a configuration example of a three-state logic NAND gate shown in FIG. 7;

11 is a circuit diagram showing a configuration example of a timing circuit that generates control signals φ6 and φ7 used in the block selection control circuit shown in FIG. 6;

FIG. 12 is a circuit diagram of a main part showing a configuration example of a program judging circuit shown in FIG. 1;

FIG. 13 is a circuit diagram of a main part showing a configuration example of a program judging circuit shown in FIG. 1;

FIG. 14 is a timing chart of control signals used in the block erase mode of the memory cell array shown in FIG. 2;

FIG. 15 is a timing chart of each control signal used in the program mode of the memory cell array shown in FIG. 2;

16 is a timing chart of control signals used in a program verification mode and a read mode of the memory cell array shown in FIG. 2;

FIG. 17 is a circuit diagram showing another configuration example of the memory cell array shown in FIG. 1;

18 is a circuit diagram showing a configuration example of a block selection control circuit used for the memory cell array shown in FIG.

19 is a circuit diagram showing a configuration example of a ground line driving circuit used for the memory cell array shown in FIG.

20 is a timing chart of each control signal used in the block erase mode of the memory cell array shown in FIG.

21 is a timing chart of each control signal used in the program mode of the memory cell array shown in FIG.

22A is a block diagram showing a connection relationship between the circuit in FIG. 2 and the circuit in FIG. 3, and FIG. 22B is a block diagram showing a connection relationship between the circuit in FIG. 3 and the circuit in FIG.

[Explanation of symbols]

 Reference Signs List 10 memory cell array 12 data register and sense amplifier 14 column decoder and selection circuit 16 input / output buffer 18, 318 block selection control circuit 20 control gate drive circuit 22 source line drive circuit 24 program determination circuit 26 input buffer 28 output buffer 30 column decoder 32 Column selection circuit 33 Constant current circuit 64 Reference section 66 Current source section 320 Ground line drive circuit 164 Verification voltage generation circuit

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (1)

[Claims] 1. A semiconductor device comprising a plurality of bit lines and a plurality of cell units, each cell unit comprising at least one memory transistor, wherein each of the memory transistors has a floating gate electric field having a floating gate and a control gate. One end of each cell unit is connected to a corresponding bit line, and the other end receives a reference potential. The control gate of the memory transistor selected during the read operation Non-volatile semiconductor memory device having control means for applying a read voltage to a memory cell and applying a program voltage during a data program operation and a program verify voltage during a program verify operation to a control gate of a selected memory transistor In the data read operation and program verification operation Current source means for supplying a small amount of current to a bit line, and storing write data for providing write data to a selected memory transistor through the bit line during a data programming operation, and performing a read operation. Common data latch means for storing read data during the program and verify data during the program verify operation, and depending on the bit line current flowing through the memory transistor selected from the current source means during the read and program verify operations. And a data sensing means for detecting the read data and the verification data and providing the data to the common data latch means, respectively.