JPH1098075A - 半導体実装方法、半導体実装装置および半導体実装構造 - Google Patents

半導体実装方法、半導体実装装置および半導体実装構造

Info

Publication number
JPH1098075A
JPH1098075A JP25003696A JP25003696A JPH1098075A JP H1098075 A JPH1098075 A JP H1098075A JP 25003696 A JP25003696 A JP 25003696A JP 25003696 A JP25003696 A JP 25003696A JP H1098075 A JPH1098075 A JP H1098075A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
wiring board
electrode
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25003696A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1098075A5 (enrdf_load_stackoverflow
Inventor
Michiko Ono
美智子 小野
Tetsuo Komatsu
哲郎 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP25003696A priority Critical patent/JPH1098075A/ja
Publication of JPH1098075A publication Critical patent/JPH1098075A/ja
Publication of JPH1098075A5 publication Critical patent/JPH1098075A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Wire Bonding (AREA)
JP25003696A 1996-09-20 1996-09-20 半導体実装方法、半導体実装装置および半導体実装構造 Pending JPH1098075A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25003696A JPH1098075A (ja) 1996-09-20 1996-09-20 半導体実装方法、半導体実装装置および半導体実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25003696A JPH1098075A (ja) 1996-09-20 1996-09-20 半導体実装方法、半導体実装装置および半導体実装構造

Publications (2)

Publication Number Publication Date
JPH1098075A true JPH1098075A (ja) 1998-04-14
JPH1098075A5 JPH1098075A5 (enrdf_load_stackoverflow) 2004-09-09

Family

ID=17201882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25003696A Pending JPH1098075A (ja) 1996-09-20 1996-09-20 半導体実装方法、半導体実装装置および半導体実装構造

Country Status (1)

Country Link
JP (1) JPH1098075A (enrdf_load_stackoverflow)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006339524A (ja) * 2005-06-03 2006-12-14 Shinko Electric Ind Co Ltd 電子装置及びその製造方法
JP2007273563A (ja) * 2006-03-30 2007-10-18 Toshiba Corp 部品内蔵プリント配線板、部品内蔵プリント配線板の製造方法および電子機器
JP2009212186A (ja) * 2008-03-03 2009-09-17 Nec Corp 半導体装置の製造方法および装置
JP2010278480A (ja) * 2010-09-14 2010-12-09 Rohm Co Ltd 半導体装置
JP2012109507A (ja) * 2010-11-16 2012-06-07 Stats Chippac Ltd 半導体素子およびフリップチップ相互接続構造を形成する方法
US8405227B2 (en) 2004-09-28 2013-03-26 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US11842972B2 (en) 2004-09-28 2023-12-12 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10388626B2 (en) 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
US9831204B2 (en) 2004-09-28 2017-11-28 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US9721865B2 (en) 2004-09-28 2017-08-01 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US11842972B2 (en) 2004-09-28 2023-12-12 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US11355462B2 (en) 2004-09-28 2022-06-07 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US8405227B2 (en) 2004-09-28 2013-03-26 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US8754535B2 (en) 2004-09-28 2014-06-17 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US9117774B2 (en) 2004-09-28 2015-08-25 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US10818628B2 (en) 2004-09-28 2020-10-27 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
US10522494B2 (en) 2004-09-28 2019-12-31 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
JP2006339524A (ja) * 2005-06-03 2006-12-14 Shinko Electric Ind Co Ltd 電子装置及びその製造方法
JP2007273563A (ja) * 2006-03-30 2007-10-18 Toshiba Corp 部品内蔵プリント配線板、部品内蔵プリント配線板の製造方法および電子機器
JP2009212186A (ja) * 2008-03-03 2009-09-17 Nec Corp 半導体装置の製造方法および装置
JP2010278480A (ja) * 2010-09-14 2010-12-09 Rohm Co Ltd 半導体装置
JP2012109507A (ja) * 2010-11-16 2012-06-07 Stats Chippac Ltd 半導体素子およびフリップチップ相互接続構造を形成する方法

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