JPH1096963A - Liquid crystal display device and manufacturing method therefor - Google Patents
Liquid crystal display device and manufacturing method thereforInfo
- Publication number
- JPH1096963A JPH1096963A JP9244796A JP24479697A JPH1096963A JP H1096963 A JPH1096963 A JP H1096963A JP 9244796 A JP9244796 A JP 9244796A JP 24479697 A JP24479697 A JP 24479697A JP H1096963 A JPH1096963 A JP H1096963A
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- crystal display
- layer
- display device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133357—Planarisation layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133512—Light shielding layers, e.g. black matrix
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、液晶表示装置及び
その製造方法に関する。特に、本発明は薄膜トランジス
タを有する液晶表示装置の基板及びその製造方法に関す
る。The present invention relates to a liquid crystal display device and a method for manufacturing the same. In particular, the present invention relates to a substrate of a liquid crystal display device having a thin film transistor and a method of manufacturing the same.
【0002】[0002]
【従来の技術】従来の液晶表示装置の構造について、図
1を参照して説明する。液晶表示装置は、画素がマトリ
クス状に配列された第1基板3を有する。前記第1基板3
上には画素電極4が形成されており、該各々の画素電極4
はゲートバス配線17及びデータバス配線15によって囲ま
れている。又、前記ゲートバス配線17から分岐するゲー
ト電極17aと、前記データバス配線15から分岐するソー
ス電極15aが形成されている。薄膜トランジスタ8は、前
記ゲートバス配線17と前記データバス配線15との交差点
に形成されている。前記薄膜トランジスタのドレイン電
極15bは、前記画素電極4に電気的にコンタクトするよう
に形成されている。ブラックマトリクス(光遮断層)
は、前記薄膜トランジスタ8、ゲートバス配線17及びデ
ータバス配線15を覆うように形成されている。配向膜
(配向層)は、前記ブラックマトリクスを含む前記基板
の全面上に形成されている。2. Description of the Related Art The structure of a conventional liquid crystal display device will be described with reference to FIG. The liquid crystal display device has a first substrate 3 on which pixels are arranged in a matrix. The first substrate 3
On the pixel electrodes 4 are formed, and each of the pixel electrodes 4 is formed.
Are surrounded by the gate bus wiring 17 and the data bus wiring 15. Further, a gate electrode 17a branched from the gate bus wiring 17 and a source electrode 15a branched from the data bus wiring 15 are formed. The thin film transistor 8 is formed at an intersection of the gate bus line 17 and the data bus line 15. The drain electrode 15b of the thin film transistor is formed so as to be in electrical contact with the pixel electrode 4. Black matrix (light blocking layer)
Are formed so as to cover the thin film transistor 8, the gate bus wiring 17, and the data bus wiring 15. An alignment film (alignment layer) is formed on the entire surface of the substrate including the black matrix.
【0003】カラーフィルタ層37を有する第2基板2
は、ギャップを持って前記第1基板3と対向するように
配置されている。第1基板と第2基板とのギャップに液
晶物質40が封入されている。前記第1基板及び第2基板
の外側面に偏光板1、1aが付着されることで、従来の液
晶表示装置のパネルが完成される。The second substrate 2 having the color filter layer 37
Are arranged so as to face the first substrate 3 with a gap. A liquid crystal material 40 is sealed in a gap between the first substrate and the second substrate. By attaching the polarizing plates 1 and 1a to the outer surfaces of the first and second substrates, a panel of a conventional liquid crystal display device is completed.
【0004】従来の液晶表示装置の第1基板の構造につ
いて、図2、図3を参照して詳しく説明する。図2、図
3は、図1のI−I´線に沿った断面図である。従来の液
晶表示装置の第1基板3の製造方法及び構造について
は、図2を参照して説明する。A structure of a first substrate of a conventional liquid crystal display device will be described in detail with reference to FIGS. 2 and 3 are cross-sectional views taken along the line II ′ of FIG. The manufacturing method and structure of the first substrate 3 of the conventional liquid crystal display will be described with reference to FIG.
【0005】ゲートバス配線17から分岐するゲート電極
17aは、透明基板3上に形成されている。陽極酸化膜35
は、絶縁特性の向上及びヒロックの防ぎのために、前記
ゲート電極17a上に形成されている。SiNx、又はSiO2の
ような無機物質から成るゲート絶縁膜23は、前記ゲート
電極17aを含む基板の全面に形成されている。アモルフ
ァスシリコン(a-Si)から成る半導体層22は、前記ゲー
ト電極17a上のゲート絶縁膜23上に形成されている。そ
の上に不純物が添加されたアモルファスシリコン(n+ a
-Si)のような不純物半導体層25が形成されている。デ
ータバス配線15から分岐するソース電極15a及びドレイ
ン電極15bは、前記不純物半導体層25上に一定の間隔を
隔てて形成されている。それで、前記ソース電極15a及
び前記ドレイン電極15bは、前記不純物半導体層25とオ
ーミックコンタクトになっている。SiNxのような無機保
護膜26は、前記ソース電極15a及び前記ドレイン電極15b
を含む前記基板の全面を覆うように形成されている。画
素電極4は、前記ドレイン電極15b上の前記保護膜26に形
成されたコンタクトホールを通して前記ドレイン電極15
bに電気的なコンタクトを成し、前記保護膜26上に形成
されている。そして、ブラックマトリクス10は、前記薄
膜トランジスタ8、前記ゲートバス配線17及び前記デー
タバス配線15を覆うように形成されている(図4及び図
5)。続いて、その上に例えば、ポリイミドから成る配
向膜11がコーティングによって形成されている。Gate electrode branched from gate bus line 17
17a is formed on the transparent substrate 3. Anodized film 35
Is formed on the gate electrode 17a in order to improve insulation properties and prevent hillocks. A gate insulating film 23 made of an inorganic substance such as SiNx or SiO 2 is formed on the entire surface of the substrate including the gate electrode 17a. A semiconductor layer 22 made of amorphous silicon (a-Si) is formed on a gate insulating film 23 on the gate electrode 17a. Amorphous silicon (n + a
-Si) is formed. The source electrode 15a and the drain electrode 15b branched from the data bus line 15 are formed on the impurity semiconductor layer 25 at a constant interval. Thus, the source electrode 15a and the drain electrode 15b are in ohmic contact with the impurity semiconductor layer 25. The inorganic protective film 26 such as SiNx includes the source electrode 15a and the drain electrode 15b.
The substrate is formed so as to cover the entire surface of the substrate. The pixel electrode 4 is connected to the drain electrode 15b through a contact hole formed in the protective film 26 on the drain electrode 15b.
An electrical contact is made to b and is formed on the protective film 26. The black matrix 10 is formed so as to cover the thin film transistor 8, the gate bus wiring 17, and the data bus wiring 15 (FIGS. 4 and 5). Subsequently, an alignment film 11 made of, for example, polyimide is formed thereon by coating.
【0006】又、従来の液晶表示装置の第1基板3の他
の構造については、図2の構成要素と等しい図3を参照
して説明する。この場合は、前記ブラックマトリクスの
近傍の配向膜11にラビング不良が生ずることを防ぐため
に、ブラックマトリクス10の形成の前に配向膜11が形成
されている。Further, another structure of the first substrate 3 of the conventional liquid crystal display device will be described with reference to FIG. 3, which is the same as the component of FIG. In this case, the alignment film 11 is formed before the formation of the black matrix 10 in order to prevent rubbing defects from occurring in the alignment film 11 near the black matrix.
【0007】しかし、図2、又は図3の構造を有する前
記液晶表示装置は、次の如く問題を有する。第一に、図
2に示すように、第1基板の構造において前記配向膜
は、前記画素電極4及びブラックマトリクス10によって
形成された段差部を有する。その結果、配向膜の段差部
分でラビング不良が発生し、光が漏れる。従って、液晶
表示装置のコントラスト特性が低下する。配向膜のラビ
ング工程及び構造の理解のために、図6及び図7を参照
して以下に詳しく説明する。However, the liquid crystal display device having the structure shown in FIG. 2 or FIG. 3 has the following problems. First, as shown in FIG. 2, in the structure of the first substrate, the alignment film has a step formed by the pixel electrode 4 and the black matrix 10. As a result, rubbing failure occurs at a step portion of the alignment film, and light leaks. Therefore, the contrast characteristics of the liquid crystal display device deteriorate. In order to understand the rubbing process and the structure of the alignment film, a detailed description will be given below with reference to FIGS.
【0008】図6は、図5のIII−III´線に沿った断面
図である。図2に示す前記配向膜11は、印刷ローラーに
ポリアミド、ポリイミド及び酸化シリコンのような配向
膜の物質を印刷し、前記ブラックマトリクス10を含む前
記第1基板3の全表面上に転写することによって形成さ
れる。そして、前記配向膜を固化させた後、液晶が一定
の方向で配向されるようにラビング工程を実施する。前
記ラビング工程は、図7に示すようにラビングドラム13
1を使用して前記配向膜上に一定方向の溝(図の波形の
ような部分)を形成させる。前記ラビングドラム131
は、ラビング布130で覆われており、B方向に一定の圧
力で押しながらA方向に回転し、C方向に移動する。図
5の斜線によって示されたD0部分(図7の133部分)
は、前記ブラックマトリクス10によって生じた段差のた
めに、ラビング不良が発生する。前記ブラックマトリク
スの厚さが1〜2.5μmである時、図4のD0の幅は1
〜2μmである。このような領域は、ポリビニルシンナ
メイト(polyvinylcinnamate(PVCN))、ポリビニルフル
オロシンナメイト(polyvinylfluorocinnamate(PVCN-
F))、ポリシロキサン(polysiloxanes)、又はポリ塩
化ビニル(polyvinylchloride(PVC))を配向膜で使用
し、光配向することによって無くすことが出来る。しか
し、セルギャップの不良の問題は、解消できない。FIG. 6 is a sectional view taken along the line III-III 'of FIG. The alignment film 11 shown in FIG. 2 is formed by printing an alignment film material such as polyamide, polyimide and silicon oxide on a print roller and transferring the printed material onto the entire surface of the first substrate 3 including the black matrix 10. It is formed. After the alignment film is solidified, a rubbing process is performed so that the liquid crystal is aligned in a certain direction. In the rubbing step, as shown in FIG.
1 is used to form a groove in a certain direction (portion like a waveform in the figure) on the alignment film. The rubbing drum 131
Is covered with a rubbing cloth 130, rotates in the direction A while being pressed at a constant pressure in the direction B, and moves in the direction C. D 0 portion indicated by hatching in FIG. 5 (133 parts of FIG. 7)
In the case, a rubbing defect occurs due to a step caused by the black matrix 10. When the thickness of the black matrix is 1 to 2.5 μm, the width of D 0 in FIG.
22 μm. Such regions include polyvinylcinnamate (PVCN), polyvinylfluorocinnamate (PVCN-
F)), polysiloxanes, or polyvinylchloride (PVC) can be used in the alignment film and removed by photoalignment. However, the problem of the defective cell gap cannot be solved.
【0009】第二に、図2及び図3に示すように、従来
の液晶表示装置において前記第1基板3は、ブラックマ
トリクス10を含む多層構造によって表面に段差がある。
これは液晶表示装置において、不均一なセルギャップを
招く。従って、不均一なセルギャップは、液晶の注入を
不安定にさせるために、液晶表示装置の表示品質及び歩
留まりを低下させる。さらに、図3に示すように、前記
液晶が前記ブラックマトリクスに直接接触すると、液晶
表示装置の画質特性が維持されない。前記ブラックマト
リクス、又は顔料が液晶を汚染させる。一般に、ブラッ
クマトリクスは黒色顔料を含むネガフォトレジストから
成る。Second, as shown in FIGS. 2 and 3, in the conventional liquid crystal display device, the first substrate 3 has a step on the surface due to a multilayer structure including a black matrix 10.
This causes a non-uniform cell gap in the liquid crystal display device. Therefore, the non-uniform cell gap destabilizes the injection of liquid crystal, thereby lowering the display quality and yield of the liquid crystal display device. Further, as shown in FIG. 3, when the liquid crystal directly contacts the black matrix, the image quality characteristics of the liquid crystal display device are not maintained. The black matrix or pigment contaminates the liquid crystal. Generally, the black matrix consists of a negative photoresist containing a black pigment.
【0010】第三に、従来の液晶表示装置において、第
1基板の表面に段差が形成され、配向膜のラビング不良
が発生し、無機絶縁膜(保護膜26)の低い誘電率のため
に、画素電極はデータ及びゲートバス配線等に重畳して
形成することは不可能であった。もし、画素電極が無機
絶縁膜の下に位置したデータバス配線と重畳されるよう
に形成すると、前記データバス配線の電圧と前記画素電
極の電圧間の干渉のために画面表示にちらつきが生じ
る。又、前記重畳部分では、ラビング不良による光の漏
れが発生する。従って、一般に前記画素電極は、データ
バス配線から一定間隔を隔てて位置させられる。この場
合、図8に示すように、高い開口率を得ることは、不可
能である。図8においてSiNx、又はSiO2のような無機絶
縁膜26は、段差があるデータバス配線15を覆い、又画素
電極4は前記データバス配線15からD2だけ離れた位置に
形成されている。前記D1は、前記第1基板と前記第2
基板との貼り合わせマージンを考慮して形成された領域
である。従って、従来の液晶表示装置において前記開口
率は、D3=(D1+D2)分だけの損失がある。Third, in the conventional liquid crystal display device, a step is formed on the surface of the first substrate, rubbing failure of the alignment film occurs, and the dielectric constant of the inorganic insulating film (protective film 26) is low. It was impossible to form the pixel electrode so as to overlap the data and the gate bus wiring. If the pixel electrode is formed so as to overlap with the data bus line located below the inorganic insulating film, a screen display flickers due to interference between the voltage of the data bus line and the voltage of the pixel electrode. Further, in the overlapping portion, light leakage occurs due to rubbing failure. Therefore, the pixel electrode is generally located at a certain distance from the data bus line. In this case, as shown in FIG. 8, it is impossible to obtain a high aperture ratio. In FIG. 8, an inorganic insulating film 26 such as SiNx or SiO 2 covers the data bus line 15 having a step, and the pixel electrode 4 is formed at a position separated from the data bus line 15 by D 2 . D 1 is the first substrate and the second substrate
This is a region formed in consideration of a bonding margin with the substrate. Therefore, in the conventional liquid crystal display device, the aperture ratio has a loss of D 3 = (D 1 + D 2 ).
【0011】以上の説明のように、前記第1基板は、ブ
ラックマトリクスによって表面に段差が形成され、前記
ブラックマトリクスは液晶物質と直接に接触する。従っ
て、前記ブラックマトリクスの近傍で光の漏れが生じ、
セルギップの不均一の不良、液晶の汚染及び低い開口率
を招く。As described above, the first substrate has a step formed on the surface by the black matrix, and the black matrix is in direct contact with the liquid crystal material. Therefore, light leakage occurs near the black matrix,
This results in non-uniform failure of the cell gap, contamination of the liquid crystal, and a low aperture ratio.
【0012】[0012]
【発明が解決しようとする課題】本発明は、均一なセル
ギャップを有する液晶表示装置を提供することを目的と
する。又、本発明は、液晶表示装置においてブラックマ
トリクス、又はその顔料による液晶の汚染を防ぐことを
他の目的とする。又、本発明は、液晶表示装置において
配向膜のラビング不良のため、ブラックマトリクスの段
差部分で生じる光の漏れを防ぐことを他の目的とする。
又、本発明は、開口率が向上された液晶表示装置を提供
することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display having a uniform cell gap. Another object of the present invention is to prevent liquid crystal contamination of a liquid crystal display device with a black matrix or a pigment thereof. It is another object of the present invention to prevent light leakage at a step portion of a black matrix due to a rubbing defect of an alignment film in a liquid crystal display device.
Another object of the present invention is to provide a liquid crystal display device having an improved aperture ratio.
【0013】[0013]
【課題を解決するための手段】前述した問題点を解決す
るための本発明による液晶表示装置の第1基板の製造方
法は、透明基板上にデータバス配線及びゲートバス配線
を形成する段階と、前記データバス配線及びゲートバス
配線に連結されるスイッチング素子を形成する段階と、
前記スイッチング素子を覆うブラックマトリクスを形成
する段階と、前記データバス配線、前記ゲートバス配線
及び前記ブラックマトリクスを覆う平坦化膜を形成する
段階と、前記平坦化膜上に配向膜を形成する段階とを含
む。According to the present invention, there is provided a method of manufacturing a first substrate of a liquid crystal display device, comprising the steps of: forming a data bus line and a gate bus line on a transparent substrate; Forming a switching device connected to the data bus line and the gate bus line;
Forming a black matrix covering the switching element, forming a flattening film covering the data bus wiring, the gate bus wiring and the black matrix, and forming an alignment film on the flattening film. including.
【0014】本発明による液晶表示装置の第1基板の構
造は、基板と、前記透明基板上に形成されたゲートバス
配線及びデータバス配線に連結されたスイッチング素子
と、前記スイッチング素子を覆うブラックマトリクス
と、前記ブラックマトリクス、前記データバス配線、前
記ゲートバス配線及び前記透明基板を覆う平坦化膜と、
前記平坦化膜を覆う配向膜と、から構成される。The structure of the first substrate of the liquid crystal display device according to the present invention comprises a substrate, switching elements connected to gate bus lines and data bus lines formed on the transparent substrate, and a black matrix covering the switching elements. And a flattening film covering the black matrix, the data bus wiring, the gate bus wiring and the transparent substrate,
An alignment film that covers the flattening film.
【0015】又、本発明による液晶表示装置の第1基板
の他の構造は、基板と、前記基板上のゲート電極、ソー
ス電極、及びドレイン電極を有するトランジスタと、前
記トランジスタ上の保護層と、前記トランジスタ上の前
記保護層の一部に形成された光遮断層と、前記光遮断層
及び前記保護層上に形成され、前記ソース電極、又は前
記ドレイン電極上にコンタクトホールを有する平坦化膜
と、前記平坦化膜の前記コンタクトホールを通して前記
ソース電極、又は前記ドレイン電極に接触する画素電極
と、前記画素電極上の配向膜とから構成される。Further, another structure of the first substrate of the liquid crystal display device according to the present invention includes a substrate, a transistor having a gate electrode, a source electrode, and a drain electrode on the substrate, a protective layer on the transistor, A light blocking layer formed on a part of the protection layer on the transistor, and a planarization film formed on the light blocking layer and the protection layer and having a contact hole on the source electrode or the drain electrode; A pixel electrode contacting the source electrode or the drain electrode through the contact hole of the planarization film, and an alignment film on the pixel electrode.
【0016】本発明による液晶表示装置の第1基板の他
の製造方法は、基板上にゲート電極、ドレイン電極及び
ソース電極を有するトランジスタを形成する段階と、前
記トランジスタ上に光遮断層を形成する段階と、前記光
遮断層を含む前記基板の全表面上に平坦化膜を形成する
段階と、前記平坦化膜上に配向膜を形成する段階とから
構成される。According to another method of manufacturing a first substrate of a liquid crystal display device according to the present invention, a transistor having a gate electrode, a drain electrode and a source electrode is formed on a substrate, and a light blocking layer is formed on the transistor. And a step of forming a planarization film on the entire surface of the substrate including the light blocking layer, and a step of forming an alignment film on the planarization film.
【0017】本発明による液晶表示装置の第1基板の他
の構造は、基板と、前記基板上にゲート電極、ソース電
極及びドレイン電極を有するトランジスタと、前記ソー
ス電極、又はドレイン電極にコンタクトする画素電極
と、前記トランジスタ及び前記画素電極上の保護層と、
前記トランジスタの前記保護層の一部分上の光遮断層
と、前記光遮断層及び前記保護層上の平坦化膜と、前記
平坦化膜上の配向層と、から構成される。Another structure of the first substrate of the liquid crystal display device according to the present invention includes a substrate, a transistor having a gate electrode, a source electrode, and a drain electrode on the substrate, and a pixel contacting the source electrode or the drain electrode. An electrode, a protective layer on the transistor and the pixel electrode,
The transistor includes a light blocking layer on a part of the protective layer of the transistor, a planarizing film on the light blocking layer and the protective layer, and an alignment layer on the planarizing film.
【0018】[0018]
(実施例1)本発明の実施例1による液晶表示装置の第
1基板の製造方法を図9〜図18を参照して説明する。
第1透明基板103上にアルミニウムの金属が堆積され
る。その上にフォトレジストをコーティングし、パター
ニングする。図9に示すように前記アルミニウム膜は、
ゲート電極117a及びゲートバス配線を形成するために例
えば、ウエットエッチング法でエッチされる。前記ゲー
ト電極117aは、段差を解消するためにテーパの形状で形
成するのが望ましい。又、図10に示すように前記ゲー
ト電極117aは、ヒロックを防ぎ、又絶縁を向上させるた
めに陽極酸化し、陽極酸化膜135が形成される。その上
にSiNx、又はSiO2から成るゲート絶縁膜123、a−Si 122
及びn+a-Si 125が連続的に堆積される。前記表面上にフ
ォトレジストをコーティングし、パターニングする。図
12に示すように、前記パターニングされたフォトレジ
ストに従って前記a-Si及びn+a-Siをエッチングし、半導
体層122及び不純物半導体層125を形成する。Embodiment 1 A method for manufacturing a first substrate of a liquid crystal display according to Embodiment 1 of the present invention will be described with reference to FIGS.
Aluminum metal is deposited on the first transparent substrate 103. A photoresist is coated thereon and patterned. As shown in FIG. 9, the aluminum film
Etching is performed by, for example, a wet etching method to form the gate electrode 117a and the gate bus wiring. The gate electrode 117a is desirably formed in a tapered shape in order to eliminate a step. Further, as shown in FIG. 10, the gate electrode 117a is anodized to prevent hillocks and to improve insulation, so that an anodic oxide film 135 is formed. The gate insulating film 123 made SiNx, or of SiO 2 thereon, a-Si 122
And n + a-Si 125 are continuously deposited. A photoresist is coated and patterned on the surface. As shown in FIG. 12, the semiconductor layer 122 and the impurity semiconductor layer 125 are formed by etching the a-Si and the n + a-Si according to the patterned photoresist.
【0019】続いて、金属膜を形成するために基板の全
面にCr、又はAlから成る金属が堆積される。前記ゲート
電極の形成方法と同じ方法によってソース電極115a、デ
ータバス配線及びドレイン電極 115bが形成される。前
記ソース電極115a及び前記ドレイン電極115bをエッチン
グマスクとして前記不純物半導体層125の中央部をエッ
チングして除去する(図13)。不純物半導体層125は
それぞれ前記ソース電極115a及び前記ドレイン電極115b
にオーミックコンタクトされた二つの分離された部分を
形成する。そして、図14に示すように、保護膜126
(厚さ200〜500Å)は、SiNx又はSiO2のような無機物質
の蒸着によって形成される。一般に、前記半導体層122
上部に形成されるこの絶縁膜は、薄膜トランジスタ108
を保護するために、そしてブラックマトリクス110から
の汚染を防止するために形成される。しかし、前記ブラ
ックマトリクスの汚染があまり問題にならない場合は、
前記保護膜126を省略してもよい。Subsequently, a metal made of Cr or Al is deposited on the entire surface of the substrate to form a metal film. A source electrode 115a, a data bus wiring, and a drain electrode 115b are formed by the same method as the method of forming the gate electrode. Using the source electrode 115a and the drain electrode 115b as an etching mask, the central portion of the impurity semiconductor layer 125 is removed by etching (FIG. 13). The impurity semiconductor layer 125 includes the source electrode 115a and the drain electrode 115b, respectively.
To form two separate portions that are in ohmic contact. Then, as shown in FIG.
(Thickness 200 to 500 Å) is formed by vapor deposition of an inorganic material such as SiNx or SiO 2. Generally, the semiconductor layer 122
This insulating film formed on the upper part
And to prevent contamination from the black matrix 110. However, when the contamination of the black matrix is not so problematic,
The protective film 126 may be omitted.
【0020】前記保護膜126の表面に黒色樹脂(厚さ1μ
m以上)が堆積される。ポリイミドに黒色顔料を含むネ
ガフォトレジストは、前記黒色樹脂として使用される。
この物質の処理温度は、約260℃である。図15に示す
ように、前記黒色樹脂をパターニングしてブラックマト
リクス110(光遮断層)を形成する。そして、図16に
示すように、基板の全表面にベンゾシクロブテン(BC
B)、PFCB、フッ素が添加されたパリレン(fluorinated
parylene)、テフロン(teflon)、サイトップ(cyto
p)、又はフルオロポリアリールエーテル(fluoropolya
rylether)等のSi基を有する有機物質、又はガラス基板
上にスピン塗布された物質(spin on glass(SOG))から
成る平坦化膜156が形成される。前記平坦化膜156は、下
部の多層構造の段差を解消して平坦な表面を有する。前
記平坦化膜は、前記二つの基板間のセルギャップを均一
にし、前記セルギャップに液晶を注入する時、不安定性
を減少させることによって液晶表示装置の品質を改善さ
せる。又、本発明の前記平坦化膜は、配向膜の均一なラ
ビングを提供することによってブラックマトリクスの段
差近傍からの光の漏れを防ぐことが出来る。The surface of the protective film 126 is coated with a black resin (1 μm thick).
m or more) is deposited. A negative photoresist containing a black pigment in polyimide is used as the black resin.
The processing temperature of this material is about 260 ° C. As shown in FIG. 15, the black resin is patterned to form a black matrix 110 (light blocking layer). Then, as shown in FIG. 16, benzocyclobutene (BC
B), PFCB, fluorinated parylene
parylene), teflon, cytop (cyto
p) or fluoropolyaryl ether (fluoropolya
A flattening film 156 made of an organic material having a Si group such as (rylether) or a material (spin on glass (SOG)) spin-coated on a glass substrate is formed. The flattening film 156 has a flat surface by eliminating a step in the lower multilayer structure. The flattening layer makes the cell gap between the two substrates uniform and improves the quality of the liquid crystal display by reducing instability when injecting liquid crystal into the cell gap. Further, the flattening film of the present invention can prevent light leakage from near the step of the black matrix by providing uniform rubbing of the alignment film.
【0021】続いて、コンタクトホールは、前記平坦化
膜156及び前記保護膜126を通して前記ドレイン電極上に
形成される。そして、図17に示すように、ITO(indiu
m tin oxide)は、基板の全表面上に蒸着され、パター
ニングされて画素電極104になる。Subsequently, a contact hole is formed on the drain electrode through the planarization film 156 and the protection film 126. Then, as shown in FIG. 17, ITO (indiu
m tin oxide) is deposited on the entire surface of the substrate and patterned to become the pixel electrode 104.
【0022】最後に、図18に示すように、ポリイミ
ド、ポリアミド、又は酸化シリコンから成る配向膜111
(配向層)が形成され、その表面に溝(波形のようなパ
ターン)を有するようにラビングされる。又、前記波形
のようなパターンは、例えばポリビニルシンナメイト
(polyvinylcinnamate(PVCN))、ポリビニルフルオロシ
ンナメイト(polyvinylfluorocinnamate(PVCN-F))、ポ
リシロキサン(polysiloxanes)、又はポリ塩化ビニル
(polyvinylchloride(PVC))膜をフォトアライン(光配
向)することによって得ることも出来る。Finally, as shown in FIG. 18, an alignment film 111 made of polyimide, polyamide, or silicon oxide is used.
(Orientation layer) is formed and rubbed so as to have a groove (pattern like a waveform) on its surface. The pattern such as the waveform is, for example, polyvinylcinnamate (polyvinylcinnamate (PVCN)), polyvinylfluorocinnamate (polyvinylfluorocinnamate (PVCN-F)), polysiloxane (polysiloxanes), or polyvinyl chloride (polyvinylchloride (PVC)). It can also be obtained by photoaligning (photo-aligning) the film.
【0023】一般に、本発明の前記平坦化膜156は、従
来の無機絶縁膜より低い誘電率を有する物質を使用す
る。従って、前記画素電極104は、データ、又はゲート
バス配線に重畳するように拡大して形成することも出来
る。前記拡大された画素電極104の構造については、図
19、図20及び図21を参照して説明する。前記ブラ
ックマトリクス110は、前記データバス配線115が不透明
の物質である場合には省略することも可能である。しか
し、光の漏れを完璧に無くすためには、前記データバス
配線115上に前記ブラックマトリクス110を形成すること
が好ましい。図19はI型チャンネルを有する薄膜トラ
ンジスタ108を示す第1基板の平面図であり、図20は
L型チャンネルを有する薄膜トランジスタ108を示す第
1基板の平面図である。図21は、図19のIV−IV´線
に沿った断面図である。この図から分かるように、ブラ
ックマトリクス110は、前記データバス配線115と一致す
るように形成されている。そして、前記画素電極104
は、前記データバス配線115に重畳されるように形成さ
れる。従って、有効画素電極の領域(図21のd幅は含
まない)が増加する。又、有効の画素領域では、ラビン
グ不良も無い。Generally, the planarization film 156 of the present invention uses a material having a lower dielectric constant than a conventional inorganic insulating film. Therefore, the pixel electrode 104 can be formed so as to be enlarged so as to overlap data or a gate bus line. The structure of the enlarged pixel electrode 104 will be described with reference to FIGS. 19, 20 and 21. The black matrix 110 may be omitted when the data bus line 115 is made of an opaque material. However, in order to completely eliminate light leakage, it is preferable to form the black matrix 110 on the data bus wiring 115. FIG. 19 is a plan view of a first substrate showing a thin film transistor 108 having an I-type channel, and FIG. 20 is a plan view of a first substrate showing a thin film transistor 108 having an L-type channel. FIG. 21 is a sectional view taken along the line IV-IV ′ of FIG. As can be seen from this figure, the black matrix 110 is formed so as to coincide with the data bus wiring 115. Then, the pixel electrode 104
Are formed so as to overlap the data bus wiring 115. Therefore, the area of the effective pixel electrode (excluding the d width in FIG. 21) increases. Also, there is no rubbing defect in the effective pixel area.
【0024】本発明を一層詳しく説明するために、本発
明の図21と従来の図7とを比べて説明する。図7のデ
ータバス配線15と、図21のデータバス配線115とは、
同一の幅を有することと仮定する。ここで、図21の前
記画素電極104は、データ配線の両側で図7の画素電極4
よりD3だけ広い。図21において、前記画素電極104の
一部分であるd領域は、前記ブラックマトリクス110に
よって光が遮断されるので、有効の画素電極領域に成ら
ない。In order to explain the present invention in more detail, FIG. 21 of the present invention is compared with FIG. 7 of the related art. The data bus wiring 15 of FIG. 7 and the data bus wiring 115 of FIG.
Assume they have the same width. Here, the pixel electrode 104 in FIG. 21 is connected to the pixel electrode 4 in FIG.
More D 3 just wide. In FIG. 21, a region d, which is a part of the pixel electrode 104, is not an effective pixel electrode region because light is blocked by the black matrix 110.
【0025】又、ブラックマトリクス110が前記薄膜ト
ランジスタ108及びゲートバス配線117と一致するように
形成して、画素電極104のサイズを一層大きくすること
ができる。従って、前記ブラックマトリクス110上の平
坦化膜156の適用は、液晶表示装置の開口率を向上させ
る。しかも、前記平坦化膜はブラックマトリクス110か
ら液晶を隔離するので、前記ブラックマトリクス110、
又はその色顔料による液晶物質の汚染を防ぐことも可能
である。The size of the pixel electrode 104 can be further increased by forming the black matrix 110 so as to match the thin film transistor 108 and the gate bus line 117. Therefore, the application of the planarizing film 156 on the black matrix 110 improves the aperture ratio of the liquid crystal display. In addition, since the flattening film separates the liquid crystal from the black matrix 110, the black matrix 110,
Alternatively, it is possible to prevent contamination of the liquid crystal substance by the color pigment.
【0026】(実施例2)図22は、本発明の実施例2
を示す。実施例1は、画素電極104が保護膜126の上に形
成された場合(ITO on passivation film:IOP)を示し
ているが、実施例2は、図22に示すように前記画素電
極104が保護膜126の下に形成された構造に平坦化膜156
が適用されたものである。(Embodiment 2) FIG. 22 shows Embodiment 2 of the present invention.
Is shown. Embodiment 1 shows a case where the pixel electrode 104 is formed on the protective film 126 (ITO on passivation film: IOP). Embodiment 2 shows that the pixel electrode 104 is protected as shown in FIG. A planarization film 156 is formed on the structure formed under the film 126.
Is applied.
【0027】前記実施例2による本発明の利点は、前記
実施例1と等しい。前記実施例2に関する詳細な説明
は、前記実施例1の説明と等しいので省略する。本発明
による液晶表示装置の第1基板の製造方法は、ブラック
マトリクス等によって段差ができた表面上に平坦化膜を
形成することに関する。前記平坦化膜は、開口率の向
上、前記ブラックマトリクスの近傍領域での光の漏れの
抑制及び液晶の安定的な注入に要求される均一なセルギ
ャップを提供する。さらに、ブラックマトリクス、又は
その顔料から液晶物質の汚染を防ぐことによって高画質
の液晶表示装置が得られる。これは前記平坦化膜が液晶
物質を前記ブラックマトリクスから隔離するからであ
る。The advantages of the present invention according to the second embodiment are the same as those of the first embodiment. A detailed description of the second embodiment will be omitted because it is the same as that of the first embodiment. The method for manufacturing a first substrate of a liquid crystal display device according to the present invention relates to forming a flattening film on a surface having a step formed by a black matrix or the like. The flattening film provides a uniform cell gap required for improving an aperture ratio, suppressing light leakage in a region near the black matrix, and stably injecting liquid crystal. Further, a high-quality liquid crystal display device can be obtained by preventing contamination of the liquid crystal substance from the black matrix or its pigment. This is because the planarizing film separates the liquid crystal material from the black matrix.
【0028】[0028]
【発明の効果】本発明は、第1基板の製造方法に平坦化
膜を利用し、前記平坦化膜は、配向膜を形成する前にブ
ラックマトリクスを含む多層構造の段差を均一に、又平
坦にさせる。従って、前記平坦化膜が平坦な表面を有す
るから、次に形成される配向膜も平坦な表面を有する。
この結果、液晶表示装置の基板間の均一なセルギャップ
が得られる。又、配向膜の全表面に均一な溝を形成する
ことができ、光の漏れを防ぐことが出来る。前記平坦化
膜は前記ブラックマトリクスから液晶を隔離するので、
液晶の汚染を防ぐことも出来る。又、本発明の平坦化膜
の誘電率が従来の無機絶縁膜の誘電率より低いため、画
素電極をデータバス配線に重畳して形成させることも出
来る。従って、開口率が向上される。According to the present invention, a flattening film is used in a method for manufacturing a first substrate, and the flattening film uniformly and uniformly forms a step of a multilayer structure including a black matrix before forming an alignment film. Let Therefore, since the flattening film has a flat surface, the alignment film to be subsequently formed also has a flat surface.
As a result, a uniform cell gap between the substrates of the liquid crystal display device can be obtained. Further, a uniform groove can be formed on the entire surface of the alignment film, and light leakage can be prevented. Since the flattening film separates the liquid crystal from the black matrix,
Liquid crystal contamination can also be prevented. Further, since the dielectric constant of the flattening film of the present invention is lower than that of the conventional inorganic insulating film, the pixel electrode can be formed so as to overlap the data bus wiring. Therefore, the aperture ratio is improved.
【図1】従来の液晶表示装置の構造を示す斜視図。FIG. 1 is a perspective view showing the structure of a conventional liquid crystal display device.
【図2】従来の液晶表示装置において第1基板を示す断
面図。FIG. 2 is a cross-sectional view showing a first substrate in a conventional liquid crystal display device.
【図3】従来の液晶表示装置において第1基板を示す断
面図。FIG. 3 is a cross-sectional view showing a first substrate in a conventional liquid crystal display device.
【図4】従来のブラックマトリクスのパターンを示す平
面図。FIG. 4 is a plan view showing a pattern of a conventional black matrix.
【図5】従来の液晶表示装置において、ブラックマトリ
クスの近傍で光の漏れを示す平面図。FIG. 5 is a plan view showing light leakage near a black matrix in a conventional liquid crystal display device.
【図6】従来の液晶表示装置において、配向膜のコーテ
ィング工程を示す断面図。FIG. 6 is a cross-sectional view showing a process of coating an alignment film in a conventional liquid crystal display device.
【図7】従来の液晶表示装置において、配向膜のラビン
グ工程を説明するための断面図。FIG. 7 is a cross-sectional view illustrating a rubbing step of an alignment film in a conventional liquid crystal display device.
【図8】図3のII−II´線に沿った断面図。FIG. 8 is a sectional view taken along the line II-II ′ of FIG. 3;
【図9】本発明による実施例1の液晶表示装置の第1基
板の製造工程を説明するための断面図。FIG. 9 is a cross-sectional view for explaining a manufacturing process of the first substrate of the liquid crystal display device according to the first embodiment of the present invention.
【図10】本発明による実施例1の液晶表示装置の第1
基板の製造工程を説明するための断面図。FIG. 10 shows a first example of the liquid crystal display device according to the first embodiment of the present invention.
Sectional drawing for demonstrating the manufacturing process of a board | substrate.
【図11】本発明による実施例1の液晶表示装置の第1
基板の製造工程を説明するための断面図。FIG. 11 illustrates a first example of the liquid crystal display device according to the first embodiment of the present invention.
Sectional drawing for demonstrating the manufacturing process of a board | substrate.
【図12】本発明による実施例1の液晶表示装置の第1
基板の製造工程を説明するための断面図。FIG. 12 shows a first example of the liquid crystal display device according to the first embodiment of the present invention.
Sectional drawing for demonstrating the manufacturing process of a board | substrate.
【図13】本発明による実施例1の液晶表示装置の第1
基板の製造工程を説明するための断面図。FIG. 13 illustrates a first example of the liquid crystal display device according to the first embodiment of the present invention.
Sectional drawing for demonstrating the manufacturing process of a board | substrate.
【図14】本発明による実施例1の液晶表示装置の第1
基板の製造工程を説明するための断面図。FIG. 14 illustrates a first example of the liquid crystal display device according to the first embodiment of the present invention.
Sectional drawing for demonstrating the manufacturing process of a board | substrate.
【図15】本発明による実施例1の液晶表示装置の第1
基板の製造工程を説明するための断面図。FIG. 15 shows a first example of the liquid crystal display device according to the first embodiment of the present invention.
Sectional drawing for demonstrating the manufacturing process of a board | substrate.
【図16】本発明による実施例1の液晶表示装置の第1
基板の製造工程を説明するための断面図。FIG. 16 illustrates a first example of the liquid crystal display device according to the first embodiment of the present invention.
Sectional drawing for demonstrating the manufacturing process of a board | substrate.
【図17】本発明による実施例1の液晶表示装置の第1
基板の製造工程を説明するための断面図。FIG. 17 illustrates a first example of the liquid crystal display device according to the first embodiment of the present invention.
Sectional drawing for demonstrating the manufacturing process of a board | substrate.
【図18】本発明による実施例1の液晶表示装置の第1
基板の製造工程を説明するための断面図。FIG. 18 illustrates a first example of the liquid crystal display device according to the first embodiment of the present invention.
Sectional drawing for demonstrating the manufacturing process of a board | substrate.
【図19】本発明による実施例1の液晶表示装置を示す
平面図。FIG. 19 is a plan view showing a liquid crystal display device of Embodiment 1 according to the present invention.
【図20】本発明による実施例1の液晶表示装置を示す
平面図。FIG. 20 is a plan view showing the liquid crystal display device according to the first embodiment of the present invention.
【図21】図19のIV −IV´線に沿った断面図。FIG. 21 is a sectional view taken along the line IV-IV ′ of FIG. 19;
【図22】本発明の実施例2による液晶表示装置を示す
断面図。FIG. 22 is a sectional view showing a liquid crystal display device according to a second embodiment of the present invention.
2 第2基板 3、103 第1基板 4、104 画素電極 8、108 薄膜トランジスタ 10、110 ブラックマトリクス 11、111 配向膜 15、115 データバス配線 15a、115a ソース電極 15b、115b ドレイン電極 17、117 ゲートバス配線 17a、117b ゲート電極 15、115 データバス配線 15a、115a ソース電極 15b、115b ドレイン電極 22、122 半導体層 23、123 ゲート絶縁層 25、125 不純物半導体層 26、126 無機保護膜 37 カラーフィルタ層 40 液晶物質 156 偏光板 2 Second substrate 3, 103 First substrate 4, 104 Pixel electrode 8, 108 Thin film transistor 10, 110 Black matrix 11, 111 Alignment film 15, 115 Data bus wiring 15a, 115a Source electrode 15b, 115b Drain electrode 17, 117 Gate bus Wiring 17a, 117b Gate electrode 15, 115 Data bus wiring 15a, 115a Source electrode 15b, 115b Drain electrode 22, 122 Semiconductor layer 23, 123 Gate insulating layer 25, 125 Impurity semiconductor layer 26, 126 Inorganic protective film 37 Color filter layer 40 Liquid crystal material 156 Polarizing plate
───────────────────────────────────────────────────── フロントページの続き (72)発明者 キム、ジォン ヒュン 大韓民国京機道安養市東安区虎渓洞533番 地 エルジー電子株式会社第1研究団地L CD研究所内 (72)発明者 林 京男 大韓民国京機道安養市東安区虎渓洞533番 地 エルジー電子株式会社第1研究団地L CD研究所内 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kim, Jeon Hyun 533, Hugye-dong, Dong'an-gu, Anyang-si, Gyeonggi-do, Republic of Korea Inside LCD Research Lab. 533 Lou-dong, Donggye-gu, Dongyang-gu, Gyeonggi-do, Korea
Claims (31)
を有するトランジスタと、 前記トランジスタ上の保護層と、 前記トランジスタ上の前記保護層の一部分上の光遮断層
と、 前記光遮断層及び前記保護層上に形成され、前記ソース
電極、又は前記ドレイン電極の上にコンタクトホールを
有する平坦化層と、 前記平坦化層上に形成され、前記コンタクトホールを通
して前記ソース電極、又は前記ドレイン電極に接触され
る画素電極と、 前記画素電極上の配向層と、から構成されることを特徴
とする液晶表示装置。A substrate having a gate electrode, a source electrode, and a drain electrode on the substrate; a protective layer on the transistor; a light blocking layer on a portion of the protective layer on the transistor; A flattening layer formed on the light blocking layer and the protective layer and having a contact hole on the source electrode or the drain electrode; and the source electrode formed on the flattening layer and through the contact hole, or A liquid crystal display device comprising: a pixel electrode that is in contact with the drain electrode; and an alignment layer on the pixel electrode.
バス配線が加えて構成され、前記ゲートバス配線は前記
トランジスタの前記ゲート電極に連結され、前記データ
バス配線は前記ソース電極、又は前記ドレイン電極に連
結され、前記光遮断層は前記ゲートバス配線及び前記デ
ータバス配線を覆うことを特徴とする請求項1記載の液
晶表示装置。2. A gate bus line and a data bus line are additionally provided on the substrate, wherein the gate bus line is connected to the gate electrode of the transistor, and the data bus line is the source electrode or the drain electrode. 2. The liquid crystal display device according to claim 1, wherein the light blocking layer covers the gate bus line and the data bus line.
ス配線及び前記ゲートバス配線に選択的に重畳されるこ
とを特徴とする請求項2記載の液晶表示装置。3. The liquid crystal display device according to claim 2, wherein a part of the pixel electrode is selectively overlapped with the data bus line and the gate bus line.
とを特徴とする請求項1記載の液晶表示装置。4. The liquid crystal display device according to claim 1, wherein the flattening film is made of an organic insulating material.
ンを含むことを特徴とする請求項4記載の液晶表示装
置。5. The liquid crystal display according to claim 4, wherein the organic insulating material includes benzocyclobutene.
塗布された物質を含むことを特徴とする請求項1記載の
液晶表示装置。6. The liquid crystal display device according to claim 1, wherein the flattening film includes a substance spin-coated on a glass substrate.
特徴とする請求項1記載の液晶表示装置。7. The liquid crystal display device according to claim 1, wherein the protective layer includes an inorganic insulating layer.
ることを特徴とする請求項7記載の液晶表示装置。8. The liquid crystal display device according to claim 7, wherein the inorganic insulating layer is made of SiNx or SiO 2 .
塗布された物質を含むことを特徴とする請求項7記載の
液晶表示装置。9. The liquid crystal display device according to claim 7, wherein the flattening film includes a substance spin-coated on a glass substrate.
ことを特徴とする請求項7記載の液晶表示装置。10. The liquid crystal display of claim 7, wherein the flattening film includes an organic insulating material.
テンを含むことを特徴とする請求項10記載の液晶表示
装置。11. The liquid crystal display of claim 10, wherein the organic insulating material includes benzocyclobutene.
びソース電極を有するトランジスタを形成する段階と、 前記トランジスタ上に光遮断層を形成する段階と、 前記光遮断層を含む前記基板の全表面上に平坦化層を形
成する段階と、 そして、前記平坦化層上に配向層を形成する段階を含む
ことを特徴とする液晶表示装置の製造方法。12. Forming a transistor having a gate electrode, a drain electrode and a source electrode on a substrate; forming a light blocking layer on the transistor; and forming a light blocking layer on the entire surface of the substrate including the light blocking layer. Forming a flattening layer on the substrate, and forming an alignment layer on the flattening layer.
トランジスタ上に保護層を加えて形成することを特徴と
する請求項12記載の液晶表示装置の製造方法。13. The method according to claim 12, wherein a protective layer is formed on the transistor before the step of forming the light blocking layer.
ことを特徴とする請求項13記載の液晶表示装置の製造
方法。14. The method according to claim 13, wherein the protective layer is made of SiNx or SiO 2 .
ことを特徴とする請求項12記載の液晶表示装置の製造
方法。15. The method according to claim 12, wherein the flattening layer includes an organic insulating material.
テンを含むことを特徴とする請求項15記載の液晶表示
装置の製造方法。16. The method according to claim 15, wherein the organic insulating material includes benzocyclobutene.
ン塗布された物質を含むことを特徴とする請求項12記
載の液晶表示装置の製造方法。17. The method according to claim 12, wherein the flattening layer includes a substance spin-coated on a glass substrate.
ゲート電極に連結されるゲートバス配線を形成する段階
と、 前記基板上に前記ソース電極、又前記ドレイン電極に連
結されるデータバス配線を形成する段階を加えて含み、 前記光遮断層は、前記ゲートバス配線及び前記データバ
ス配線も覆うように形成することを特徴とする請求項1
2記載の液晶表示装置の製造方法。18. A step of forming a gate bus line connected to the gate electrode of the transistor on the substrate, and forming a data bus line connected to the source electrode and the drain electrode on the substrate. The method of claim 1, wherein the light blocking layer is formed to cover the gate bus line and the data bus line.
3. The method for manufacturing a liquid crystal display device according to item 2.
坦化層上に前記ソース電極、又はドレイン電極に連結さ
れる画素電極を加えて形成することを特徴とする請求項
18記載の液晶表示装置の製造方法。19. The liquid crystal according to claim 18, wherein a pixel electrode connected to the source electrode or the drain electrode is formed on the planarization layer before forming the alignment layer. A method for manufacturing a display device.
バス配線及び前記ゲートバス配線に選択的に重畳される
ように形成することを特徴とする請求項19記載の液晶
表示装置の製造方法。20. The method according to claim 19, wherein a part of the pixel electrode is formed so as to be selectively overlapped with the data bus line and the gate bus line.
極を有するトランジスタと、 前記ソース電極、又はドレイン電極に接触する画素電極
と、 前記トランジスタ及び前記画素電極上の保護層と、 前記トランジスタ上の前記保護層の一部分上の光遮断層
と、 前記光遮断層及び前記保護層上の平坦化層と、 前記平坦化層上の配向層と、から構成されることを特徴
とする液晶表示装置。21. A substrate; a transistor having a gate electrode, a source electrode, and a drain electrode on the substrate; a pixel electrode in contact with the source electrode or the drain electrode; and a protective layer on the transistor and the pixel electrode. A light blocking layer on a portion of the protection layer on the transistor; a planarization layer on the light blocking layer and the protection layer; and an alignment layer on the planarization layer. Liquid crystal display device.
タバス配線が加えて構成され、前記ゲートバス配線は前
記トランジスタの前記ゲート電極に連結され、前記デー
タバス配線は前記ソース電極、又は前記ドレイン電極に
連結され、前記光遮断層は前記ゲートバス配線及び前記
データバス配線を覆うことを特徴とする請求項21記載
の液晶表示装置。22. A gate bus line and a data bus line are additionally provided on the substrate, wherein the gate bus line is connected to the gate electrode of the transistor, and wherein the data bus line is the source electrode or the drain electrode. 22. The liquid crystal display of claim 21, wherein the light blocking layer covers the gate bus line and the data bus line.
バス配線及び前記ゲートバス配線中に選択的に重畳され
ることを特徴とする請求項22記載の液晶表示装置。23. The liquid crystal display device according to claim 22, wherein a part of the pixel electrode is selectively overlapped with the data bus line and the gate bus line.
ことを特徴とする請求項21記載の液晶表示装置。24. The liquid crystal display according to claim 21, wherein the flattening film is made of an organic insulating material.
テンを含むことを特徴とする請求項24記載の液晶表示
装置。25. The liquid crystal display of claim 24, wherein the organic insulating material includes benzocyclobutene.
ン塗布された物質を含むことを特徴とする請求項21記
載の液晶表示装置。26. The liquid crystal display device according to claim 21, wherein the flattening layer includes a substance spin-coated on a glass substrate.
を特徴とする、請求項21記載の液晶表示装置。27. The liquid crystal display device according to claim 21, wherein the protective layer includes an inorganic insulating layer.
あることを特徴とする請求項27記載の液晶表示装置。28. The liquid crystal display device according to claim 27, wherein the inorganic insulating layer is made of SiNx or SiO 2 .
ン塗布された物質を含むことを特徴とする請求項27記
載の液晶表示装置。29. The liquid crystal display device according to claim 27, wherein the flattening layer includes a substance spin-coated on a glass substrate.
ことを特徴とする請求項27記載の液晶表示装置。30. The liquid crystal display of claim 27, wherein the flattening layer includes an organic insulating material.
テンを含むことを特徴とする請求項30記載の液晶表示
装置。31. The liquid crystal display of claim 30, wherein the organic insulating material includes benzocyclobutene.
Applications Claiming Priority (2)
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KR1019960036947A KR100244450B1 (en) | 1996-08-30 | 1996-08-30 | Substrate manufacturing method of liquid crystal display device and substrate |
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JPH1096963A true JPH1096963A (en) | 1998-04-14 |
JP4374084B2 JP4374084B2 (en) | 2009-12-02 |
Family
ID=19471838
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JP (1) | JP4374084B2 (en) |
KR (1) | KR100244450B1 (en) |
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- 1997-08-26 JP JP24479697A patent/JP4374084B2/en not_active Expired - Lifetime
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Cited By (9)
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US7176993B2 (en) | 1997-02-06 | 2007-02-13 | Semiconductor Energy Laboratory Co., Ltd. | Reflection type display device using a light shading film with a light shading material evenly dispersed throughout |
US6284558B1 (en) | 1997-11-25 | 2001-09-04 | Nec Corporation | Active matrix liquid-crystal display device and method for making the same |
US6466279B1 (en) | 1998-04-23 | 2002-10-15 | Nec Corporation | Liquid crystal display device and process for producing same in which forming first and second organic insulating layers using curing and half curing process |
US7321413B2 (en) | 1998-04-23 | 2008-01-22 | Nec Lcd Technologies, Ltd. | Liquid crystal display device and process for producing same |
JP2007114729A (en) * | 2005-09-26 | 2007-05-10 | Epson Imaging Devices Corp | Liquid crystal display device |
US8553182B2 (en) | 2005-09-26 | 2013-10-08 | Japan Display West | Liquid crystal display device including a light-blocking member |
US8810757B2 (en) | 2005-09-26 | 2014-08-19 | Japan Display West Inc. | Liquid crystal display device including a light-blocking member |
WO2008105244A1 (en) * | 2007-02-28 | 2008-09-04 | Zeon Corporation | Active matrix substrate, method for producing the same, and flat display |
JP2015007806A (en) * | 2014-09-12 | 2015-01-15 | 株式会社半導体エネルギー研究所 | Liquid crystal display device |
Also Published As
Publication number | Publication date |
---|---|
DE19737372A1 (en) | 1998-03-05 |
FR2752988A1 (en) | 1998-03-06 |
FR2752988B1 (en) | 2002-09-27 |
KR19980017194A (en) | 1998-06-05 |
DE19737372C2 (en) | 2002-04-25 |
GB2316793A (en) | 1998-03-04 |
GB9716573D0 (en) | 1997-10-08 |
JP4374084B2 (en) | 2009-12-02 |
KR100244450B1 (en) | 2000-02-01 |
GB2316793B (en) | 1999-07-21 |
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