JPH1093606A - Data transfer system for switching hub - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer system for switching hub which shortens the delay time of frame data transfer. SOLUTION: Transfer of frame data to each port is started simultaneously with reception of a frame on a port, and a transfer destination port is retrieved in parallel with this operation, and transfer destination information as the retrieval result is reported to each port, and only the pertinent port validates frame data in a buffer memory 44. The other ports invalidates frame data. As the result, frame data is transferred to only the port to which the destination terminal of the frame is connected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of transferring frame data between ports in a switching hub, and more particularly to a data transfer method of a switching hub for reducing a delay time of frame data transfer.

[0002]

2. Description of the Related Art As shown in FIG. 3, a switching hub has a plurality of communication ports, and transfers frame data of a frame received from a communication port only to a port to which a destination terminal is connected. .

[0003] In FIG.
Are connected to terminals 31a to 31d. When receiving the frame 32a addressed to the terminal 31d (terminal D) from the terminal 31a (terminal A) connected to the port 1, the switching hub 30 transmits the frame data to the terminal 31a.
Transfer only to port 4 to which d is connected. At the same time, when the frame 32b addressed to the terminal 31c (terminal C) is received from the terminal 31b (terminal B) connected to the port 2, the frame data is transferred only to the port 3 to which the terminal 31c is connected. .

FIG. 4 shows the internal configuration of the switching hub. The switching hub includes a communication control LSI 40 for controlling transmission and reception of frames, a data transfer control circuit 41 for controlling transfer of frame data between ports, and an address search circuit 42 for searching for a transfer destination port from a destination address of the frame data. , A shared bus 43 used for transferring frame data, a buffer memory 44 for temporarily storing frame data transferred via the shared bus 43, and a transfer destination notification used for notification of transfer destination information. And a bus 45.

[0005] Here, port 1 of the switching hub is used.
Next, the operation inside the switching hub will be described by taking as an example a case where a frame addressed to a terminal connected to port 3 is received.

In FIG. 4, a communication control LSI 40a comprises:
When the frame is received, it outputs the frame data to the data transfer control circuit 41a. Data transfer control circuit 41a
Extracts the destination address (address of the terminal connected to the port 3) from the frame data output by the communication control LSI 40a, and outputs this to the address search circuit 42. The address search circuit 42 holds a database that records the terminal address and the port number of the port to which the terminal address is connected, and has the terminal address output from the data transfer control circuit 41a using this database. It searches which port the terminal is connected to and outputs the result information (port number = 3) to the data transfer control circuit 41a. Data transfer control circuit 41a
The transfer destination information (port 3) is transmitted to the other data transfer control circuit 41 via the transfer destination notification bus 45 based on this information.
Is output), and the transfer of the frame data is started.

The data transfer control circuit 41b detects from the transfer destination information notified via the transfer destination notification bus 45 that frame data not addressed to its own port is transferred, and is transferred via the shared bus 43. The stored frame data is not stored in the buffer memory 44b. On the other hand, the data transfer control circuit 41 c
From the transfer destination information notified through the communication bus 4 that the frame data addressed to the own port is transferred,
3 is stored in the buffer memory 44c. The frame data stored in the buffer memory 44c is read out and transmitted at the same time that the communication control LSI 40c can transmit.

[0008]

In the above-mentioned prior art, as shown in FIG. 5, a destination search 50 for extracting a destination address from received frame data and searching for a destination port by an address search circuit 42, and After the transfer destination notification 51 for notifying the transfer destination information obtained as a result of the transfer destination search is completed, the frame data transfer 52 is executed. For this reason, when the transfer destination search time becomes long, there is a problem that a transfer delay time from when a frame is received to when transfer of frame data is started increases.

An object of the present invention is to provide a data transfer system for a switching hub which solves the above-mentioned problems and reduces the delay time of frame data transfer.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a communication control LSI for controlling transmission and reception of frames at each of a plurality of ports, and transfer of frame data between the ports. And a buffer memory for temporarily storing the transferred frame data, and an address search circuit for searching for a transfer destination port from a destination address of the frame data. In a switching hub in which frame data is transferred only to the port to which the destination terminal is connected, the frame is transferred to each port at the same time as the frame is received by the port, and the transfer destination port is concurrently started. Search, and notifies each port of the transfer result information that is the search result. It is an effective frame data in the memory.

The data transfer control circuits are connected to each other by a shared bus, the data transfer control circuit of the port receiving the frame transfers frame data via the shared bus, and the data transfer control circuit of another port is transferred. The received frame data may be fetched into the buffer memory, and then, based on the notification of the transfer destination information, the data transfer control circuit of the port which does not correspond may stop the fetching and erase the buffer memory.

[0012]

An embodiment of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows the configuration of a data transfer control circuit according to the present invention. The data transfer control circuit includes a communication control LSI 4
Communication control LSI control unit 10 for controlling the input and output of data to and from destination address extraction unit 1 for extracting a destination address from frame data output from communication control LSI 40
1, an address search control unit 12 for controlling the output of the destination address to the address search circuit 42 and the detection of the transfer destination information from the address search circuit 42, and the input / output control of the transfer destination notification bus 45 and whether the transfer destination is the local port. A transfer destination notification control unit 13 for determining whether or not the shared memory 43 is connected to the shared bus 43;
And a buffer memory control unit 15 for controlling the control unit 4.

First, the operation when a port receives a frame will be described.

The communication control LSI control unit 10
When the frame data is output from the SI 40, the frame data is output to the destination address extraction unit 11 and the shared bus control unit 14. The destination address extraction unit 11 extracts a destination address from the frame data, and outputs the destination address to the address search control unit 12. The address search control unit 12 uses the address search circuit 42
, And waits for a response from the address search circuit 42. When detecting the response (transfer destination information) from the address search circuit 42, the address search control unit 12 outputs the transfer destination information to the transfer destination notification control unit 13. Transfer destination notification control unit 13
When the transfer destination information from the address search control unit 12 is detected, the transfer destination information is output to the transfer destination notification bus 45.

On the other hand, the shared bus control unit 14
When the frame data is output from the SI control unit 10, the right to output data to the shared bus 43 is acquired, and the frame data is output to the shared bus 43. FIG. 2 shows a time chart of the operation at the time of reception of the data transfer control circuit according to the present invention. The destination address extraction 20 for searching the destination port by the destination address extraction and address search circuit 42 from the frame data and the frame data transfer 22 are simultaneously executed.

Next, the operation for frame data transfer and transfer destination information notification from another data transfer control circuit will be described.

When detecting that frame data has been transferred from another data transfer control circuit via the shared bus 43, the shared bus control unit 14 outputs the frame data to the buffer memory control unit 15. The buffer memory control unit 15 stores the frame data in the buffer memory 44
To save.

When the transfer destination notification control unit 13 detects transfer destination information from another data transfer control circuit from the transfer destination notification bus 45, the transfer destination notification control unit 13 uses the transfer destination information to transmit the frame data transferred via the shared bus 43. Is determined to be directed to its own port, and when it is not directed to its own port, this is notified to the shared bus control unit 14 and the buffer memory control unit 15. The shared bus control unit 14 controls the transfer destination notification control unit 13
, The output of the frame data to the buffer memory control unit 15 is stopped, and the buffer memory control unit 15 clears the frame data stored in the buffer memory 44.

If the transferred frame data is addressed to its own port, the frame data in the buffer memory 44 is valid, so that it is read out at the same time that the communication control LSI 40 becomes available for transmission and transmitted from the port.

[0021]

The present invention exhibits the following excellent effects.

(1) Since the frame data transfer can be started before the transfer destination search is completed, the transfer delay time does not increase even if the transfer destination search time becomes long.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transfer control circuit according to an embodiment of the present invention.

FIG. 2 is a time chart of an operation at the time of reception of a data transfer control circuit according to the present invention.

FIG. 3 is a configuration diagram of a network using a switching hub.

FIG. 4 is an internal configuration diagram of a switching hub.

FIG. 5 is a time chart of an operation at the time of reception of a data transfer control circuit according to the related art.

[Explanation of symbols]

 Reference Signs List 10 communication control LSI control unit 11 destination address extraction unit 12 address search control unit 13 transfer destination notification control unit 14 shared bus control unit 15 buffer memory control unit 40 (41a to 40c) communication control LSI 42 address search circuit 43 shared bus 44 ( 44a-44c) Buffer memory

Claims (2)

[Claims] 1. A communication control LSI for controlling transmission and reception of frames at each of a plurality of ports, a data transfer control circuit for controlling transfer of frame data between the ports, and a frame data transferred A buffer memory for temporarily storing the frame data, and an address search circuit for searching for the transfer destination port from the destination address of the frame data, and transferring the frame data only to the port to which the destination terminal of the frame is connected. In the switching hub, the transfer of frame data to each port is started at the same time when a frame is received by a port, a search for a transfer destination port is performed in parallel, and transfer destination information as a search result is transmitted to each port. The port is notified and only the corresponding port validates the frame data in the buffer memory. Switching hub data transfer method. 2. The data transfer control circuit is connected to each other by a shared bus, and the data transfer control circuit of the port receiving the frame transfers frame data through the shared bus.
The data transfer control circuit of the other port captures the transferred frame data into the buffer memory, and then, based on the notification of the transfer destination information, determines that the data transfer control circuit of the port not applicable stops the capture and erases the buffer memory. The data transfer method for a switching hub according to claim 1, wherein: