JPH1092920A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the aspect ratio of the contact hole from rising due to a buried insulation film remaining on a substrate at forming a trench element isolation of a semiconductor device having bipolar transistors. SOLUTION: The emitter 23, bases 19a, 19b and collectors 12a, 12b of bipolar transistors are formed on active regions 10 of a semiconductor substrate 11 and Si film 21 is formed through a layer insulation film 17 on the surface of the substrate. The Si film 21, layer insulation film 17 and substrate 11 are etched to form trenches 23 into the substrate 11 and buried insulation film is formed on the Si film 21 so as to be buried in the trenches 24 and etched back to form element isolated regions with leaving the buried insulation film in the trenches, using the Si film 21 as a stopper, thus perfectly removing the buried insulation film from the film 21, without CMP(chemical mechanical polishing).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a plurality of elements and a trench element isolation region for isolating these elements on the same substrate.

[0002]

2. Description of the Related Art When manufacturing a semiconductor device having an element isolation region in which a trench is filled with an insulating film, first, a trench is formed on the front side of a semiconductor substrate, and the trench is filled with an insulator. After forming the element isolation region, an element such as a bipolar transistor is formed in an active region between the element isolation regions. But,
Since the coefficient of thermal expansion of the semiconductor substrate is different from the coefficient of thermal expansion of the insulator in the trench, a thermal stress is applied between the semiconductor substrate and the insulator during the heat treatment in the above-described element formation. Crystal defects may occur on the substrate. When such a crystal defect reaches the active region, current leakage occurs in an element formed in the active region.

[0003] Therefore, the trench is made to have a U-shaped cross section, a polysilicon film having a thermal expansion coefficient close to that of a silicon substrate is buried in the trench through an insulating film, so as to reduce thermal stress, or to form a trench with an element isolation region. By increasing the distance between the active region and the active region, the influence of thermal stress is prevented from being exerted on the active region.

[0004] However, by adopting the above countermeasures, crystal defects in the active region due to the thermal stress and leaks caused by the defects can be prevented to some extent, but there is a problem that the process of forming the element isolation region becomes complicated. And the degree of integration is reduced. For this reason, the application of element isolation consisting of trenches is limited to high value-added semiconductor devices.

[0005] Then, furthermore, European Sol
id State DeviceResearch Co
nreference (1995) has been devised. Hereinafter, this method will be described with reference to FIG. First, as shown in FIG. 6A, for example, a bipolar transistor (hereinafter, referred to as a bipolar Tr.) B is formed on the front surface side of the active region 60 of the semiconductor substrate 61. Next, as shown in FIG. 6B, a trench 62 is opened in the semiconductor substrate 61 so as to surround the active region 60, and a channel stop diffusion layer 63 is formed on the bottom of the trench 62. Thereafter, as shown in FIG. 6C, a buried insulating film 63 is formed on the semiconductor substrate 61 in a state where the trench 62 is buried, and an element isolation region A in which the insulating film is buried in the trench 62 is formed. . Then, FIG.
As shown in (4), CMP (Chemical Mechanical Po
After the surface of the buried insulating film 63 is planarized by lishing), contact holes 65 are formed in the buried insulating film 63 and the other insulating film 64 on the semiconductor substrate 61. Next, after a plug 66 is formed in the contact hole 65, a wiring 67 connected to the plug 66 is formed.

According to the above-mentioned method, the bipolar Tr. The step of forming B and the step of forming the channel stop diffusion layer 63 are performed before the element isolation region A is formed. Therefore, after the element isolation region A is formed, high temperature is not applied to the semiconductor substrate 61 and the buried insulating film 63 in the trench 62, and a thermal stress is generated between the semiconductor substrate 61 and the buried insulating film 62. There is no. Accordingly, a semiconductor device can be manufactured without lowering the degree of integration.

[0007]

However, in the above-described method of manufacturing a semiconductor device, the surface of the buried insulating film formed so as to bury the inside of the trench is planarized by CMP to form the film outside the trench. An extra portion of the buried insulating film is removed. Therefore, in order to terminate the CMP without affecting the bipolar transistor formed on the front surface side of the semiconductor substrate, it is necessary to leave an insulating film having a certain thickness on the semiconductor substrate.

Therefore, since the contact hole formed in the insulating film has a high aspect ratio, a plug must be formed in the contact hole. This is a factor that increases the number of manufacturing steps of the semiconductor device. Further, since CMP itself is a very laborious process, even if the above method is applied, it is not possible to reduce the TAT and the manufacturing cost.

[0009]

SUMMARY OF THE INVENTION The present invention is a method of manufacturing a semiconductor device which has been made to solve the above-mentioned problems.
Bipolar Tr. Is formed on the surface side of the semiconductor substrate separated by the element isolation region. This is a method for manufacturing a semiconductor device provided with:
That is, the bipolar T is applied to the active region of the semiconductor device.
r. To form the emitter, base, and collector of
A silicon film is formed on the surface of the semiconductor substrate via an interlayer insulating film. Next, at least the silicon film, the interlayer insulating film and the semiconductor substrate are etched to form a trench in the semiconductor substrate between active regions. Then, a buried insulating film is formed on the silicon film in a state where the trench is buried, thereby forming an element isolation region in which the trench is buried with the buried insulating film, and then leaving the buried insulating film in the trench. The buried insulating film is etched back using the silicon film as a stopper.

In the above manufacturing method, since the buried insulating film for burying the trench is formed on the silicon film, an excess portion of the buried insulating film is etched back using the silicon film as a stopper. For this reason,
The buried insulating film on the silicon film is completely removed, and the buried insulating film is left only in the trench. Therefore, when a contact hole reaching the semiconductor substrate is formed in a later step, the aspect ratio becomes small, and it is not necessary to form a plug in the contact hole.

In the method of manufacturing a semiconductor device, after the emitter opening reaching the semiconductor substrate is formed in the interlayer insulating film, the emitter is diffused from a silicon film formed so as to cover the interlayer insulating film. Shall be formed. In this case, a semiconductor device is formed without specially providing a manufacturing process of a silicon film serving as an etching stopper when etching back the buried insulating film.

In the step of etching back the buried insulating film, an SOG etch-back method or a resist etch-back method is performed. If you do this,
Even if there is a dent above the trench on the deposition surface of the buried insulating film, this dent is covered by SOG or resist. Therefore, when the etch back is performed, the dent does not remain as it is, and the buried insulating film is left flat in the opening in the trench.

Further, the bipolar Tr. When a semiconductor device having a resistor is manufactured, the silicon film is patterned to form the resistor.
Similarly, the bipolar Tr. In addition, when manufacturing a semiconductor device having a capacitor, the silicon film is patterned to form a lower electrode of the capacitor.

According to the above-described manufacturing method, the resistor or the capacitor is formed of a silicon film which serves as an etching stopper when the embedded insulating film is etched back. Therefore, a semiconductor device can be formed without specially providing a manufacturing process of the silicon film for the etching stopper.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. The embodiments described below are merely examples of the present invention.

(First Embodiment) FIGS. 1 and 2 show an NPN type bipolar Tr. Having a double polysilicon structure on the front side of a semiconductor substrate. FIG. 9 is a diagram showing an example of the present invention applied to a method of manufacturing a semiconductor device in which a plurality of are formed in an array. less than,
An embodiment of the method for manufacturing a semiconductor device will be described with reference to these drawings.

First, as shown in FIG. 1A, antimony oxide (Sb ₂ ) is formed on a surface layer of a P-type silicon substrate 11a.
After the buried collector 12a is formed by solid phase diffusion of N-type impurities from O ₃ ), an epitaxial layer 11b of N-type silicon is formed on the upper surface of the silicon substrate 11a.
This epitaxial layer 11b has a sheet resistance of 1 to 5Ω.
cm and a film thickness of 0.7 to 2.0 μm. Thus, the semiconductor substrate 11 including the silicon substrate 11a and the epitaxial layer 11b is formed.

Next, a normal LOCOS (Local Oxidatio)
A field oxide film 13 having a thickness of about 800 nm is formed on the surface layer of the semiconductor substrate 11 by an (n of Silicon) method. This field oxide film 13 is
2b and a shape exposing the base formation portion. Further, in this semiconductor device, since the field oxide film 13 is not used for the element isolation region, the field oxide film 1 on the semiconductor substrate 11 is not used when the LOCOS method is performed.
It is not necessary to etch the formation of No. 3.

Next, an N-type impurity for forming the take-out collector 12b is introduced into the surface side of the semiconductor substrate 11. As an example, phosphorus ions are used as N-type impurities, and 5 × 10 ¹⁵ /
Introduce about ² cm ² . Thereafter, by performing a heat treatment at 1000 ° C. for 30 minutes, the impurities are diffused and activated to form a take-out collector 12b.

Next, with the field oxide film 13 covered,
A first silicon oxide film having a thickness of about 100 nm is formed on the semiconductor substrate 11.
A silicon film 14 is formed on the first silicon oxide film 14.
A base opening 15 reaching the semiconductor substrate 11 is formed. Next
Therefore, the CVD (Chemical Vapor Deposition) method
To cover the first silicon oxide film 14 to a thickness of 150 n.
An about m polysilicon film 16 is formed. Next, this port
P-type impurities are introduced into the entire surface of the
The conductivity type of the polysilicon film 16 is set to P-type. P-type impurity
As an example of introduction, ion implantation
Iodine ion (BF _Two ⁺) With 30-70 keV injection energy
10 in rugi^Fifteen-10¹⁶Pieces / cm^TwoIntroduce a degree. That
Thereafter, the polysilicon film 16 is etched to form the base electrode 1.
6a is formed.

Next, as shown in FIG. 1B, an interlayer insulating film 17 made of silicon oxide having a thickness of about 300 nm is formed by a CVD method so as to cover the base electrode 16a. Thereafter, the interlayer insulating film 17 and the base electrode 16
Then, an emitter opening 18 reaching the semiconductor substrate 11 is formed. Next, a P for forming the intrinsic base 19a from the portion of the semiconductor substrate 11 exposed at the bottom of the emitter opening 18 is formed.
Introduce type impurities. As an example of P-type impurity introduction,
Boron difluoride ions are introduced at an implantation energy of 30 to 70 keV and about 10 ¹³ to 10 ¹⁴ ions / cm ² .

Next, the interlayer insulating film 17 is formed by CVD.
A second silicon oxide film 20 having a thickness of 600 nm is formed on the semiconductor substrate 11 so as to cover the semiconductor substrate 11. Thereafter, heat treatment is performed at 900 ° C. for 10 minutes. By this heat treatment, diffusion and activation of the P-type impurity introduced for forming the intrinsic base 10a are performed, and at the same time, the P-type impurity diffuses from the base electrode 16a to the surface layer of the semiconductor substrate 11 to be formed below the base electrode 16a. Thus, a graft base 19b is formed.

After the heat treatment, the entire surface of the second silicon oxide film 20 is etched back, and the side wall 2 of the second silicon oxide film 20 is formed on the side wall of the emitter opening 18.
0a is formed. This side wall 20a is for separating the emitter from the base electrode 16a.

After performing the above-described steps in the same procedure as usual, the following steps characteristic of the present invention are performed. That is, as shown in FIG. 1 (3), first, a silicon film 21 made of polysilicon having a thickness of 150 nm is formed on the semiconductor substrate 11 so as to cover the interlayer insulating film 17 by the CVD method.
Is formed. An N-type impurity is introduced into the entire surface of the silicon film 21. As an example of the introduction of N-type impurities, arsenic ions (As ⁺ ) are introduced by ion implantation at an implantation energy of 30 to 70 keV to about 10 ¹⁵ to 10 ¹⁶ / cm ² .

Next, a third silicon oxide film 22 having a thickness of about 800 nm is formed on the silicon film 21 by a CVD method. Thereafter, high-speed heat treatment (Rapid Thermal Anneal: RTA) is performed at 900 to 1100 ° C. for 5 to 30 seconds,
An emitter 23 is formed by diffusing an N-type impurity from the silicon film 21 to the surface layer of the intrinsic base 19a. At this time, the third silicon oxide film 22 prevents outdiffusion of impurities in the silicon film 22.

Next, a resist pattern (not shown) for forming a trench is formed on the third silicon oxide film 22, and the third silicon oxide film 22, the silicon film 21, and the interlayer are formed by etching using this resist pattern as a mask. The semiconductor film 11 is exposed by removing the insulating film 17 and the field oxide film 13.

Next, as shown in FIG. 1D, after removing the resist pattern, the semiconductor substrate 11 is etched by about 0.5 to 1.5 μm using the third silicon oxide film 22 as a mask. The trench 24 is formed by digging down to a depth of about 2.5 to 5.0 μm with a width of. As an example of this etching, the etching is performed by RIE (Reactive Ion Etching) using silane tetrachloride (SiCl ₄ ) / sulfur hexafluoride (SF ₆ ) as an etching gas. At this time, depending on the setting of the etching conditions and the depth of the trench 24, the third silicon oxide film 22 also has a thickness of 100 to 5 mm.
Etched to a thickness of 00 nm. For this reason, the thickness of the third silicon oxide film 22 is set to a thickness that does not remove the third silicon oxide film 22 on the silicon film 21 by this etching.

Then, the trench 24 is formed by ion implantation.
P-type impurities are introduced into the semiconductor substrate 11 from the bottom surface of FIG. As an example of the introduction of a P-type impurity, boron difluoride ions are implanted at a dose of 10 ^{13 to} 5
Introduce about × 10 ¹⁴ / cm ² . Next, 750-90
A heat treatment for activating the introduced ions is performed at a temperature of 0 ° C., thereby forming the channel stop diffusion layer 25.

Next, as shown in FIG. 2 (5), a buried insulating film 26 having a thickness of 0.5 to 1.5 μm is formed while the trench 24 is buried. Thus, an element isolation region A in which the trench 24 is buried with the buried insulating film 26 is formed. As the buried insulating film 26,
Silicon oxide containing no impurities (NSG) or silicon oxide containing phosphorus or boron (PSG, BSG, BP)
SG) or the like. In addition, the buried insulating film 2
The film 6 is formed by a method with good coverage such as a low pressure CVD method using TEOS (Tetraethoxysilane) gas.

Thereafter, as shown in FIG. 2 (6), the buried insulating film 26 deposited on the silicon film 21 is etched back to leave the buried insulating film 26 only in the trench 24. At this time, etching is performed using the silicon film 21 as a stopper and an end point of the etching. Silicon film 21
When the third silicon oxide film (22) remains on the third silicon oxide film (22), the third silicon oxide film (22) is also removed by etching.

The etch back of the buried insulating film 26 is performed by a SOG etch back method, a resist etch back method, or the like.

Next, as shown in FIG. 2 (7), the silicon film 21 is etched using a resist pattern (not shown) as a mask to form an emitter electrode 21a made of the silicon film 21. As an example of etching the silicon film 21, ethane trichloride ethane (C ₂ Cl
₃ F ₃₎ and sulfur hexafluoride (SF ₆₎ and is used for the etching gas.

Next, after removing the resist pattern, a contact hole 17a reaching the base electrode 16a and a contact hole 17b reaching the extraction collector 12b are formed in the interlayer insulating film 17. Next, the base electrode 16a, the extraction collector 12b, and the emitter electrode 21
a is formed on the front side of the semiconductor substrate 11 to form a bipolar polysilicon T
r. The semiconductor device 1 provided with B is completed.

According to the method of manufacturing a semiconductor device described above, after each step of forming an impurity diffusion layer on the surface side of the semiconductor substrate 11 is completed, a step of burying the buried insulating film 26 in the trench 24 (the step of forming the buried insulating film 26). A film forming step) is performed. Therefore, the trench 24 is filled with the buried insulating film 26.
After the burying, the heat treatment at a high temperature for diffusing and activating the impurities is not performed. Therefore, thermal stress due to a difference in thermal expansion coefficient between the buried insulating film 26 in the trench 24 and the semiconductor substrate 11 is not applied.

Furthermore, since the buried insulating film 26 is etched back using the silicon film 21 as a stopper, the buried insulating film 26 is completely removed on the silicon film 21 to leave the buried insulating film 26 only in the trench 24. Becomes possible. From this, the contact holes 17a, 17
The aspect ratio of b becomes small, and it becomes possible to form the wiring 27 connected to the bottom surfaces of the contact holes 17a and 17b without forming a plug. Moreover, as described above, the buried insulating film 2 in a portion other than in the trench 24 is formed.
Since 6 is removed by etch-back, it is not necessary to perform a complicated process such as CMP.

In addition, since the emitter electrode 21a is formed by patterning the silicon film 21 serving as a stopper when the buried insulating film 26 is etched back, it is not necessary to provide a special process for manufacturing the silicon film 21 for the stopper. Absent. Since the etch back is performed by the SOG etch back method or the resist etch back method, the etch back is performed in a state where the recess formed in the upper part of the trench on the film forming surface of the buried insulating film 26 is covered by the SOG or the resist. Done. Therefore, no dent remains on the surface of the buried insulating film 26 left in the trench 24, and the buried insulating film 26 having a flat surface can be left in the trench 24.

(Second Embodiment) FIGS. 3 and 4 show an NPN bipolar Tr. FIG. 7 is a diagram showing an example of the present invention applied to a method of manufacturing a semiconductor device in which a plurality of resistors and resistors are arranged on the same substrate. Hereinafter, an embodiment of the method of manufacturing the semiconductor device will be described with reference to FIG.

First, as shown in FIG.
As in the embodiment, an N-type buried collector 12a is formed in the active region 10 in the surface layer of the P-type silicon substrate 11a, and then an N-type buried collector 12 is formed on the silicon substrate 11a.
Type epitaxial layer 11b is formed and silicon substrate 1
Semiconductor substrate 1 comprising 1a and epitaxial layer 11b
Form one. Further, in the same manner as in the first embodiment,
An extraction collector 12b is formed.

Thereafter, a P-type impurity for forming the base 31 is introduced into the surface layer of the semiconductor substrate 11. Here, as an example, boron difluoride ions are introduced at a dose of about 10 ¹⁴ / cm ² at an implantation energy of about 35 keV.
Then, the base 31 is formed by diffusing and activating the P-type impurities by a heat treatment at 900 ° C. for 30 minutes. Next, a P-type impurity for forming the graft base 31a is introduced into the surface layer of the base 31. Here, as an example, boron difluoride ions are introduced at about 10 ¹⁵ / cm ² at an implantation energy of about 35 keV. Further, an N-type impurity for forming the emitter 32 is introduced into the surface layer of the base 31. Here, as an example, 5 × 10 ¹⁵ arsenic ions are implanted at an implantation energy of about 50 keV / cm 2.
Introduce about ^two .

Thereafter, the semiconductor substrate 1 is formed by CVD.
An interlayer insulating film 33 made of silicon oxide having a thickness of about 400 nm is formed on the substrate 1, and a silicon film 34 made of polysilicon having a thickness of about 150 nm is formed on the upper surface. Next, an impurity is introduced into the entire surface of the silicon film 34. As an example of impurity introduction, boron difluoride ion is introduced at about 2 × 10 ¹⁵ ions / cm ² at 70 keV.

Next, the silicon film 3 is formed by the CVD method.
A first silicon oxide film 35 having a thickness of about 800 nm
Is formed. Note that the first silicon oxide film 35 is not necessarily required as an etching mask for forming a trench in a later step, if sufficient resistance is obtained for the resist pattern.

Thereafter, as shown in FIG. 3B, a resist pattern (not shown) for forming a trench is formed on the first silicon oxide film 35, and the first pattern is formed by etching using this resist pattern as a mask. Silicon oxide film 3
5, the silicon film 34 and the interlayer insulating film 33 are removed to expose the semiconductor substrate 11.

Next, after removing the resist pattern, the semiconductor substrate 11 is etched with a width of about 0.5 to 1.5 μm to a thickness of 2.5 to 5.0 μm by etching using the first silicon oxide film 35 as a mask. The trench 36 is formed by digging down to a depth of the order. This etching is performed in the same manner as in the first embodiment.

Thereafter, a channel stop diffusion layer 37 is formed in the bottom layer of the trench 36 in the same manner as in the first embodiment. Each impurity introduced into the silicon film 34 by the heat treatment at this time is also activated.

Next, as shown in FIG. 3C, a buried insulating film 38 is formed on the silicon film 34 in a state where the trench 36 is buried, as in the first embodiment. Thus, an element isolation region A in which the buried insulating film 38 is buried in the trench 36 is formed.

Further, as shown in FIG.
Similarly to the embodiment, with the buried insulating film 38 left in the trench 36, the buried insulating film 38 is etched back using the silicon film 34 as a stopper.

Then, as shown in FIG. 4 (5), the silicon film 34 is etched in the same manner as in the first embodiment to form a resistor 34a made of the silicon film 34. Thereafter, a second silicon oxide film 39 having a thickness of about 300 nm is formed on the semiconductor substrate 11 so as to cover the resistor 34a. Next, the second silicon oxide film 39 and the interlayer insulating film 33
The contact hole 40a reaching the extraction collector 12b, the contact hole 40b reaching the graft base 31a, and the contact hole 40 reaching the emitter 32
Then, a contact hole 40d reaching the resistor c and the resistor 34a is formed.

Next, a wiring 41 connected to the extraction collector 12b, the graft base 31a, the emitter 32 and the resistor 34a is formed. Thereby, the semiconductor substrate 11
The above-mentioned bipolar Tr. The semiconductor device 2 including B and the resistor 34a is completed.

According to the method of manufacturing a semiconductor device, the following effects can be obtained in addition to the effects of the method of the first embodiment. That is, by patterning the silicon film 34 serving as a stopper when the buried insulating film 38 is etched back to form the resistor 34a, the manufacturing process of the silicon film 34 for the stopper is not particularly provided. A semiconductor device can be manufactured without increasing the number.

(Third Embodiment) FIG. 5 shows an NPN bipolar Tr. FIG. 9 is a diagram showing an example of the present invention applied to a method of manufacturing a semiconductor device in which a plurality of capacitors and capacitors are formed on the same substrate. Hereinafter, an embodiment of the method of manufacturing the semiconductor device will be described with reference to FIG.

First, in the same manner as in the second embodiment, the steps up to the steps described with reference to FIGS. 3A to 3C and FIG. Thereafter, as shown in FIG. 5, the silicon film 34 is etched and the lower electrode 34b of the capacitor made of the silicon film 34 is etched in the same manner as in the second embodiment.
To form

Next, as in the second embodiment, a second silicon oxide film 39 is formed on the semiconductor substrate 11 so as to cover the lower electrode 34b. This second silicon oxide film 3
Reference numeral 9 also serves as a dielectric film of the capacitor. Then, the second
In the same manner as in the embodiment, the contact holes 40a, 40b, and 40c reaching the extraction collector 12b, the graft base 31a, and the emitter 32 are formed in the second silicon oxide film 39 and the interlayer insulating film 33, and the contact reaching the lower electrode 34b. A hole 40e is formed.

Next, a wiring 41 connected to the extraction collector 12b, the graft base 31a, the emitter 32 and the lower electrode 34b and an upper electrode 42 of the capacitor are formed. Thereby, the bipolar T is formed on the semiconductor substrate 11.
r. A semiconductor device 3 including B and a capacitor C is completed.

According to the method of manufacturing a semiconductor device, the following effects can be obtained in addition to the effects of the method of the first embodiment. That is, since the lower electrode 34b of the capacitor C is formed by patterning the silicon film 34 serving as a stopper when the buried insulating film 38 is etched back, it is not necessary to provide a special manufacturing process of the silicon film 34 for the stopper. In other words, the semiconductor device can be manufactured without increasing the number of manufacturing steps.

In the first embodiment, the bipolar Tr. Although only the second embodiment is formed, a resistor and a capacitor may be formed as in the second and third embodiments. In this case, when forming the emitter electrode by patterning the silicon film, the lower electrode of the resistor or the capacitor is simultaneously formed by the silicon film.

[0056]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the bipolar Tr. In a method of forming a trench-type element isolation region after an impurity diffusion step in manufacturing, a buried insulating film that fills the trench is etched back by using a silicon film serving as a material for forming an element as a stopper, thereby forming a trench on the silicon film. Is completely removed, and the buried insulating film can be left only in the trench. Therefore, the aspect ratio of the contact hole reaching the semiconductor substrate can be reduced, and a wiring can be formed without forming a plug in the contact hole. Moreover, since the removal of the buried insulating film is performed by etch back, it is not necessary to perform a complicated process such as CMP. Therefore, the manufacturing process of the semiconductor device can be simplified.

[Brief description of the drawings]

FIG. 1 is a sectional process view (part 1) for explaining a first embodiment;
It is.

FIG. 2 is a sectional process view (part 2) illustrating the first embodiment.
It is.

FIG. 3 is a sectional process view (part 1) illustrating a second embodiment;
It is.

FIG. 4 is a sectional process view (part 2) for explaining the second embodiment;
It is.

FIG. 5 is a sectional process view illustrating a third embodiment.

FIG. 6 is a sectional process view for explaining a conventional technique.

[Explanation of symbols]

1,2,3 Semiconductor device 10 Active area
Reference Signs List 11 semiconductor substrate 12a buried collector 12b take-out collector 17, 33 interlayer insulating film 19a intrinsic base 19b, 31a graft base 21, 34 silicon film 23, 32 emitter 24, 36 trench 26, 38 buried insulating film 31 base 34a
Resistor 34b Lower electrode A Element isolation region B Bipolar Tr. C capacitor

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: providing a bipolar transistor on a front surface of a semiconductor substrate separated by an element isolation region; and providing an active region on the front surface of the semiconductor substrate with an emitter, a base, Forming a collector and forming a silicon film on a surface of the semiconductor substrate via an interlayer insulating film; and etching the active region by etching at least the silicon film, the interlayer insulating film, and the semiconductor substrate. Forming a trench in the semiconductor substrate in between, forming a buried insulating film on the silicon film in a state where the trench is buried, and forming an element isolation region in which the trench is buried with the buried insulating film. And leaving the embedded insulating film in the trench. The method of manufacturing a semiconductor device, which comprises carrying out a step of etching back the buried insulating film a silicon film with a stopper, a. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the emitter is formed so as to cover the interlayer insulating film after forming an emitter opening reaching the semiconductor substrate in the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: forming the emitter electrode by diffusion from a silicon layer; and patterning the silicon film after etching back the buried insulating film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of etching back the buried insulating film includes a step of etching back the buried insulating film.
Performing a G etch-back method or a resist etch-back method. 4. A method for manufacturing a semiconductor device, comprising: providing a bipolar transistor on a surface side of a semiconductor substrate separated by an element isolation region; and providing a resistor on the semiconductor substrate; Forming an emitter, a base, and a collector of a bipolar transistor in an active region of the above, and forming a silicon film on a surface of the semiconductor substrate via an interlayer insulating film; Forming a trench in the semiconductor substrate between the active regions by etching the semiconductor substrate; forming a buried insulating film on the silicon film while burying the trench; Forming an element isolation region buried with a buried insulating film; A step of etching back the buried insulating film using the silicon film as a stopper while leaving the buried insulating film, and a step of forming a resistor by patterning the silicon film. Production method. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the step of etching back the buried insulating film includes a step of etching back the SOI.
Performing a G etch-back method or a resist etch-back method. 6. A method for manufacturing a semiconductor device comprising: a bipolar transistor provided on a surface side of a semiconductor substrate separated by an element isolation region; and a capacitor provided on the semiconductor substrate. Forming an emitter, a base, and a collector of a bipolar transistor in an active region on a side of the semiconductor substrate; forming a silicon film on a surface of the semiconductor substrate via an interlayer insulating film; Forming a trench in the semiconductor substrate between the bipolar transistors by etching the semiconductor substrate; forming a buried insulating film on the silicon film in a state in which the trench is buried; Forming an element isolation region buried with the buried insulating film Performing a step of etching back the buried insulating film using the silicon film as a stopper while leaving the buried insulating film in the trench; and forming a lower electrode of the capacitor by patterning the silicon film. A method for manufacturing a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the step of etching back the buried insulating film includes the step of:
Performing a G etch-back method or a resist etch-back method.