JPH1074937A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device whose electrical characteristics can be easily controlled by forming an impurity area on the surface of a semiconductor substrate, without implanting ions directly and suppressing the generation of short channel effect or reverse short channel effect. SOLUTION: After the surface of an area for forming an S/D(source/drain) on a silicon substrate is exposed (step S6), an insulation film, containing second conductive impurities with specified concentration, is piled up on the entire surface thereof (step S7), and N-type impurities are thermally diffused thereon through heat treatment, so as to form a source area and a drain area (step P8). In comparison with the ion implantation, fower point detects are implanted to the surface of the silicon substrate, and the diffusion of the second conductive impurities is suppressed. Therefore, the effective gate length can be kept longer, so that the generation of short channel effect may be suppressed, and reverse short channel effect can be also suppressed because of fewer generation of point defect.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a surface channel type field effect transistor.

[0002]

2. Description of the Related Art A conventional surface channel type field effect transistor, for example, a conventional surface channel type MOSFET (Meta
l Oxide Semiconductor Field Effect Transistor) will be described with reference to FIGS. Here, FIG. 25 is a flowchart showing a manufacturing process of a conventional surface channel type MOSFET, and FIG. 26 is a simplified sectional view showing a part of the manufacturing process.

First, an insulating film used as a buffer in the next ion implantation step is formed on the silicon substrate 10 (Step S21 in FIG. 25). Subsequently, the first conductivity type impurity is added to the silicon substrate 10 by using an ion implantation method.
For example, a P-type impurity such as B (boron) or In (indium) is ion-implanted (step S22 in FIG. 25). This ion implantation process is a process for adjusting the threshold voltage of the MOSFET by controlling the impurity concentration of the channel region. Subsequently, the insulating film on the silicon substrate 10 is removed by etching (Step S23 in FIG. 25). Subsequently, for example, a thermal oxidation process is performed on the exposed surface of the silicon substrate 10 to form the gate insulating film 12 made of a silicon oxide film (Step S24 in FIG. 25). Subsequently, for example, a polysilicon layer is deposited on the gate insulating film 12 and then patterned into a predetermined shape to form the gate electrode 14 made of the polysilicon layer (FIG. 25, step S25, FIG. 2).
6 (a)).

Then, using a gate electrode 14 as a mask, a second conductivity type impurity, for example, an N-type impurity such as P (phosphorus) or As (arsenic) is selectively ion-implanted into the surface of the silicon substrate 10 by ion implantation. Then, the source region 18 and the drain region 20 are formed on the surface of the silicon substrate 10 so as to face each other. At this time, the surface of the silicon substrate 10 sandwiched between the source region 18 and the drain region 20 is
(Step S26 in FIG. 25 and FIG. 26B).
Subsequently, a heat treatment for impurity activation is performed at a predetermined temperature to activate the N-type impurity ions implanted into the source region 18 and the drain region 20 (Step S2 in FIG. 25).
7, see FIG. 26 (c)). Finally, after depositing an insulating film on the entire surface, the insulating film is removed or processed to form necessary wiring (step S28 in FIG. 25). Thus, a surface channel N-MOSFET (N-channel MOSFET) is manufactured.

Next, a conventional LDD (Lightly Doped Drai) is used.
n) A method of manufacturing a surface channel type MOSFET having a region will be described with reference to FIGS. Here, FIG.
7 is a flowchart showing a manufacturing process of a conventional surface channel type MOSFET having an LDD structure, and FIG. 28 is a simplified sectional view showing a part of the manufacturing process. The same steps as those in the manufacturing process of FIG. 25 are denoted by the same reference numerals, and the same elements as those of the surface channel type MOSFET in FIG. 26 are denoted by the same reference numerals and description thereof is omitted.

First, steps S21 to S24 in FIG.
In the same manner as described above, an insulating film is formed on the silicon substrate 10 (Step S21 in FIG. 27), and using this insulating film as a buffer, a P-type impurity is ion-implanted into the silicon substrate 10 as a first conductivity type impurity by ion implantation. (Figure 27)
(Step S22), the insulating film on the silicon substrate 10 is removed (Step S23 in FIG. 27), and subsequently, the gate insulating film 12 is formed on the exposed silicon substrate 10 surface (FIG. 27).
Step S24). Next, after a polysilicon layer and an insulating film are laminated and formed on the gate insulating film 12, these two layers are patterned into a predetermined shape to form the gate electrode 14 with the insulating film 72 placed thereon ( FIG. 27 step S
25a, see FIG. 28 (a)).

Next, a second conductivity type impurity, for example, an N-type impurity such as P or As is selectively ion-implanted into the surface of the silicon substrate 10 by ion implantation using the gate electrode 14 as a mask. Region 36,
38 are formed facing each other. At this time, the LDD region 36,
The surface of the silicon substrate 10 sandwiched between 38 becomes the channel region 22 (Step S29 in FIG. 27).

Next, an insulating film is deposited on the entire surface, and the insulating film is etched back to form a sidewall spacer 40 on the side surface of the gate electrode 14 and to form an S / D (source / drain) of the silicon substrate 10. The surface of the scheduled area is exposed (see step S30 in FIG. 27 and FIG. 28B). Next, a second conductivity type impurity, for example, an N-type impurity such as P or As is selectively ion-implanted into the surface of the silicon substrate 10 using the gate electrode 14 and the sidewall spacer 40 as a mask by ion implantation.
The source region 18 and the drain region 20 are formed on the surface 0 (see step S26a in FIG. 27 and FIG. 28C). At this time, the dose of ion implantation for forming the source region 18 and the drain region 20 is
8 is larger than the dose amount of the ion implantation for forming 8.

Next, a heat treatment for impurity activation is performed, and L
N-type impurity ions implanted into the DD regions 36 and 38 and the source region 16 and the drain region 18 are activated.
At this time, the impurity concentration of the source region 18 and the drain region 20 becomes higher than the impurity concentration of the LDD regions 36 and 38 (see step S27a in FIG. 27 and FIG. 28D). Finally, after an insulating film is deposited on the entire surface, the insulating film is removed or processed to form necessary wiring (FIG. 27, step S28a). Thus, a surface channel type N-MOSFET having an LDD structure is manufactured.

In the above, the manufacturing process of the normal surface channel N-MOSFET and the surface channel N-MOSFET having the LDD structure has been described by taking the surface channel N-MOSFET as an example. Here, the ion implantation method is generally used in the steps of forming the source region 18 and the drain region 20 and the LDD regions 36 and 38 because the control of the amount and distribution of impurities is easy, This is due to the advantage that various types of impurities can be prepared.

The surface channel type P-MOSFET
In the case of a (P-channel MOSFET), the P-type impurity is changed to an N-type impurity and the N-type impurity is changed to a P-type impurity in the above-described manufacturing process. Since a type P-MOSFET can be manufactured, only a method for manufacturing a surface channel type N-MOSFET has been described here to avoid duplication.

[0012]

With the recent increase in the degree of integration and miniaturization of semiconductor devices, the gate length of field-effect transistors, for example, MOSFETs, has been reduced.
The reduction of the channel region of the MOSFET has become noticeable. As described above, when the gate length of the MOSFET is reduced, the threshold voltage generally tends to suddenly decrease from a certain length. This phenomenon is called the short channel effect and has been known for a relatively long time. The short channel effect is a phenomenon that occurs when the gate length is shortened, the current path region is relatively large with respect to the gate length, and the current value suddenly increases from a certain gate length. Therefore, the short channel effect is an unavoidable phenomenon when the gate length is reduced.

However, with further miniaturization of the semiconductor integrated circuit device, as the gate length of the MOSFET further shortens, as the gate length shortens, the threshold once rises and then follows the short channel effect. The phenomenon of a sudden decrease is seen. There have been many reports on this. The phenomenon in which the threshold voltage rises immediately before being reduced by the short channel effect is called an inverse short channel effect.
FIG. 2 shows the short channel effect and the inverse short channel effect.
9 Here, FIG. 29 is a graph schematically showing the relationship between the gate length and the threshold voltage when the short channel effect and the inverse short channel effect appear. In this graph, the solid line shows the case where the inverse short channel effect appears, and the broken line shows the case where the inverse short channel effect does not appear.

In FIG. 29, as the gate length of the MOSFET is reduced, the threshold voltage of the MOSFET as a whole tends to decrease in both the case of the solid line and the case of the broken line. This phenomenon is due to the generally known short channel effect. However, in the case of the solid line, the threshold voltage increases immediately before the threshold voltage decreases as the gate length decreases. This phenomenon is due to the inverse short channel effect. The short channel effect is a phenomenon that always appears in a normal MOSFET, but the inverse short channel effect does not always appear in all cases, and differs depending on the case. It is not clear at this time which cases occur significantly. However, many results have been reported that are mainly observed in MOSFETs having a current path near the surface of a semiconductor substrate.

Accordingly, the cause of the reverse short channel effect in such a MOSFET having a current path near the surface of the semiconductor substrate, that is, a so-called surface channel type MOSFET will be described with reference to FIGS. Here, FIG.
0 is a sectional view showing a schematic configuration of a normal surface channel type N-MOSFET, and FIG. 31 is a surface channel type N-MOSFET having an LDD structure.
FIG. 32 is a sectional view showing a schematic configuration of a MOSFET, and FIG.
FIG. 33 is a graph schematically showing an impurity concentration distribution in a cross section taken along line AA of a normal surface channel N-MOSFET of FIG.
4 is a graph schematically showing an impurity concentration distribution in a cross section taken along the line BB of the FET.

In FIGS. 30 and 31, a surface channel type N-MOSFET 10 is a silicon substrate, 1
2 is an insulating film, 14 is a gate electrode, 18 is a source region, 2
0 is a drain region, 22 is a channel region where a channel through which carriers pass is formed, 36 and 38 are LDD regions, 40
Is a side wall spacer, S is a source electrode terminal connected to the source region 18, D is a drain electrode terminal connected to the drain region 20, and G is a gate electrode terminal connected to the gate electrode 14. Here, the entire silicon substrate 10 including the channel region 22 is doped with a P-type impurity, and the source region 18, the drain region 20 and the LD
The D regions 36 and 38 are doped with an N-type impurity.

In FIG. 32 and FIG. 33, the solid line shows the impurity concentration distribution by the process simulation in consideration of the point defect model. The broken line is provided for reference, and shows an impurity concentration distribution by a conventional classical process simulation without considering diffusion due to point defects, mutual diffusion between impurities, and the like.

As is clear from the graphs of FIGS. 32 and 33, a small peak occurs near the PN junction in the P-type impurity concentration distribution of the channel region 22. This small peak of the P-type impurity causes the P-type impurity having the same type as that of the channel region 22 below the gate electrode 14 to be diffused into the channel region 22 due to the diffusion of point defects injected into the source region 18 and the drain region 20 or the LDD regions 36 and 38. A deeper silicon substrate 10, a source region 18 and a drain region 20, or L
This causes a phenomenon that the P-type impurity diffuses from the DD regions 36 and 38 into the shallow channel region 22 below the gate electrode 14, and the P-type impurities in the channel region 22 are redistributed.

When such a phenomenon occurs, the P-type impurity concentration distribution of the channel region 22 below the gate electrode 14 changes according to the gate length, and the potential distribution of the channel region 22 changes accordingly. The state of the carrier flowing through the will also change. For this reason, the threshold voltage changes depending on the gate length, and an inverse short channel effect appears. From this, it is considered that the reverse short channel effect is a phenomenon that occurs because the potential distribution of the current path does not change uniformly with the gate length.
The potential distribution changes depending on the gate length because the impurities are redistributed due to point defects generated during ion implantation or the like, and the impurity in the channel region below the gate electrode is 2%.
The idea of creating a dimensional bias is the mainstream of the idea in recent years.

As described above, it is generally accepted that the bias of the impurities in the channel region 22 due to the impurity redistribution due to the diffusion of point defects generated during ion implantation or the like is a cause of the inverse short channel effect. It is being done. Therefore, in the conventional method of manufacturing the surface channel MOSFET described with reference to FIGS.
Since the ion implantation method is used in the steps of forming the source region 18 and the drain region 20 and the LDD regions 36 and 38, point defects occur on the surface of the silicon substrate 10 at the same time as the ion implantation, which promotes the diffusion of impurities. As a result, the effective gate length is reduced, and the impurity distribution in the channel region 22 below the gate electrode 14 is biased, thereby promoting the short channel effect and the reverse short channel effect. MOSF that requires a reduction in gate length
In the ET, when such a short channel effect or an inverse short channel effect occurs, there arises a problem that control of electrical characteristics such as a threshold voltage becomes more and more difficult.

In order to solve such a problem, the present invention forms an impurity region on the surface of a semiconductor substrate without directly implanting ions, thereby suppressing the occurrence of a short channel effect or an inverse short channel effect. It is an object to provide a method for manufacturing a semiconductor device in which electric characteristics such as a threshold voltage can be easily controlled.

[0022]

The above object is achieved by the following method of manufacturing a semiconductor device according to the present invention. That is, a method of manufacturing a semiconductor device according to claim 1 includes a step of forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film, and a step of forming a second conductivity type on the entire surface of a substrate on which the gate electrode is formed. A step of forming a film serving as a medium for impurity diffusion, and diffusing the second conductivity type impurity from the film serving as a medium for diffusion of the second conductivity type to the surface of the semiconductor substrate using the gate electrode as a mask; Selectively forming two impurity regions. Thus, in the method of manufacturing a semiconductor device according to the first aspect, two impurity regions, for example, S / D are formed on the surface of the semiconductor substrate.
When forming the region, the second conductivity type impurity is diffused from the film serving as a medium for diffusion of the second conductivity type impurity to the surface of the semiconductor substrate, thereby reducing the injection of point defects into the surface of the semiconductor substrate. Suppresses diffusion of two-conductivity-type impurities. Therefore, it is possible to keep the effective gate length long,
While the occurrence of the short channel effect can be suppressed,
Since the occurrence of point defects is small, the occurrence of the inverse short channel effect can also be suppressed.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film; Heat-treating in an atmosphere to thermally oxidize the surface of the semiconductor substrate, diffuse the second conductivity type impurity into the surface of the semiconductor substrate using the gate electrode as a mask, and selectively form two impurity regions on the surface of the semiconductor substrate; It is characterized by having. As described above, in the method of manufacturing a semiconductor device according to the second aspect, when forming two impurity regions, for example, S / D regions on the surface of the semiconductor substrate, the heat treatment is performed in an oxidizing atmosphere containing the second conductivity type impurity. Is performed to thermally diffuse the second conductivity type impurities while forming a thermal oxide film on the semiconductor substrate surface, thereby reducing the injection of point defects into the semiconductor substrate surface and reducing the diffusion of the second conductivity type impurities. Suppress. Therefore, as in the case of the first aspect, the effective gate length can be kept long, so that the short channel effect can be suppressed. The occurrence of the channel effect can also be suppressed.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film; Depositing a film and performing a heat treatment in an atmosphere containing a second conductivity type impurity to form a second
Diffusing conductive impurities and selectively forming two impurity regions on the surface of the semiconductor substrate. Thus, in the method of manufacturing a semiconductor device according to the third aspect, when forming two impurity regions, for example, S / D regions on the surface of the semiconductor substrate, after forming a semiconductor film containing no impurities, By performing heat treatment in an atmosphere containing two-conductivity-type impurities, the second-conductivity-type impurities are thermally diffused through the semiconductor film to the surface of the semiconductor substrate, thereby reducing the injection of point defects into the semiconductor substrate surface. The diffusion of the second conductivity type impurity is suppressed. Therefore, as in the case of the first or second aspect, the effective gate length can be kept long, so that the occurrence of the short channel effect can be suppressed, and the occurrence of point defects is small. The occurrence of the inverse short channel effect can also be suppressed.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device described above, after the step of forming the gate electrode on the semiconductor substrate via the gate insulating film, the periphery of the gate electrode is protected from oxidation. And a step of covering with a conductive film. After covering the periphery of the gate electrode with the oxidation-resistant film, two impurity regions, for example, S / D regions are formed on the surface of the semiconductor substrate by using the method of manufacturing a semiconductor device according to claim 2 or 3. Therefore, at this time, the side surface of the gate electrode is not thermally oxidized by the oxidation resistant film covering the periphery of the gate electrode. Therefore, the reduction of the gate length due to the thermal oxidation of the side surface of the gate electrode is prevented, so that the short channel effect can be more effectively suppressed than in the case of the second or third aspect. The occurrence of the channel effect can also be suppressed.

In the method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device described above, after selectively forming two impurity regions on the surface of the semiconductor substrate, a sidewall spacer is formed on a side surface of the gate electrode. A step of forming a film serving as a medium for diffusion of the second conductivity type impurity on the entire surface of the substrate on which the gate electrode and the sidewall spacer are formed; Diffusing a second conductivity type impurity on the surface of the semiconductor substrate using the sidewall spacer as a mask, and selectively forming two impurity regions having a higher concentration than the two impurity regions on the surface of the semiconductor substrate. Can be. After forming two impurity regions, that is, LDD regions by using the method of manufacturing a semiconductor device in this manner, by using the method of manufacturing a semiconductor device according to claim 1, the impurity concentration of the impurity region is higher than that of the two impurity regions. Since the two impurity regions, that is, the S / D regions are formed, the reduction of the gate length is prevented, and the injection of point defects into the surface of the semiconductor substrate is reduced, thereby suppressing the diffusion of the second conductivity type impurity. I do.
Therefore, in the field effect transistor having the LDD structure, the effective gate length can be kept long.
While the occurrence of the short channel effect can be suppressed,
Since the occurrence of point defects is small, the occurrence of the inverse short channel effect can also be suppressed.

According to the method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device described above, after selectively forming two impurity regions on the surface of the semiconductor substrate, a sidewall spacer is formed on a side surface of the gate electrode. A process and a heat treatment in an oxidizing atmosphere containing a second conductivity type impurity to thermally oxidize the semiconductor substrate surface and diffuse the second conductivity type impurity into the semiconductor substrate surface using the gate electrode and the sidewall spacer as a mask. And selectively forming two impurity regions having a higher concentration than the two impurity regions on the surface of the semiconductor substrate. After forming two impurity regions, that is, LDD regions by using the method of manufacturing a semiconductor device in this manner, by using the method of manufacturing a semiconductor device according to claim 2, the impurity concentration is higher than that of the two impurity regions. Since the two impurity regions, that is, the S / D regions are formed, the reduction of the gate length is prevented, and the injection of point defects into the surface of the semiconductor substrate is reduced, thereby suppressing the diffusion of the second conductivity type impurity. I do. Therefore, even in the field effect transistor having the LDD structure, the effective gate length can be maintained long, so that the short channel effect can be suppressed. Can also be suppressed.

In the method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device described above, after selectively forming two impurity regions on the surface of the semiconductor substrate, a sidewall spacer is formed on a side surface of the gate electrode. A step of depositing a semiconductor film on the entire surface of the substrate on which the gate electrode and the sidewall spacer are formed, and a heat treatment in an atmosphere containing impurities of the second conductivity type to pass through the semiconductor film using the gate electrode as a mask. Diffusing a second conductivity type impurity on the surface of the semiconductor substrate, and selectively forming two impurity regions having a higher concentration than the two impurity regions on the surface of the semiconductor substrate. After forming two impurity regions, that is, LDD regions by using the method of manufacturing a semiconductor device in this manner, by using the method of manufacturing a semiconductor device according to claim 2, the impurity concentration is higher than that of the two impurity regions. Since the two impurity regions, that is, the S / D regions are formed, the reduction of the gate length is prevented, and the injection of point defects into the surface of the semiconductor substrate is reduced, thereby suppressing the diffusion of the second conductivity type impurity. I do. Therefore, even in the field effect transistor having the LDD structure, the effective gate length can be maintained long, so that the short channel effect can be suppressed. Can also be suppressed.

In the method of manufacturing a semiconductor device, the step of forming a film serving as a medium for diffusion of the second conductivity type impurity may be a step of depositing an insulating film containing the second conductivity type impurity. It is suitable. In the method for manufacturing a semiconductor device, the step of forming a film serving as a medium for diffusion of the second conductivity type impurity is preferably a step of depositing a semiconductor film containing the second conductivity type impurity. . Further, in the method for manufacturing a semiconductor device, the second
It is preferable that the step of forming a film serving as a medium for diffusion of the conductive impurity is a step of adding a second conductive impurity to the semiconductor film after depositing the semiconductor film.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-described method for manufacturing a semiconductor device, after the step of forming a sidewall spacer on the side surface of the gate electrode, the periphery of the gate electrode and the sidewall spacer is resistant to oxidation. A step of covering with a film. After covering the periphery of the gate electrode and the sidewall spacer with the oxidation-resistant film in this manner, two impurity regions, ie, S / D, are formed on the surface of the semiconductor substrate by using the above-described method for manufacturing a semiconductor device.
Since the region is formed, the side surface of the gate electrode is not thermally oxidized by the oxidation-resistant film covering the periphery of the gate electrode and the sidewall spacers. Therefore, a decrease in the gate length due to thermal oxidation of the side surface of the gate electrode is prevented, so that the short channel effect can be more effectively suppressed and the reverse short channel effect can be suppressed. Can be.

[0031]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described. (First Embodiment) A method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.
Here, FIG. 1 is a flowchart showing a manufacturing process of a normal surface channel type MOSFET according to the present embodiment, and FIG. 2 is a simplified cross-sectional view showing a part of the manufacturing process. In the present embodiment, an S / D region forming step by thermal diffusion of impurities from an insulating film containing impurities of the second conductivity type is used instead of the S / D region forming step using a conventional ion implantation method. There is a feature in the point.

First, an insulating film is formed on the silicon substrate 10 (Step S1 in FIG. 1). This insulating film is, for example, a silicon oxide (SiO ₂ ) film or the like, and is used as a buffer in the next ion implantation step into the silicon substrate 10. Subsequently, a first conductivity type impurity is ion-implanted into the silicon substrate 10 by using an ion implantation method (Step S2 in FIG. 1). Here, the first conductivity type impurity is
For example, it is a P-type impurity such as B or In. This ion implantation step is a step for controlling the impurity concentration of the channel region, thereby suppressing punch-through and adjusting the threshold voltage of the MOSFET. Subsequently, the insulating film on the silicon substrate 10 is removed by etching (FIG. 1, step S3). Subsequently, for example, a thermal oxidation process is performed on the exposed surface of the silicon substrate 10 to form a gate insulating film 12 made of a silicon oxide film (Step S4 in FIG. 1). Subsequently, for example, a polysilicon layer is formed on the gate insulating film 12 and then patterned into a predetermined shape to form a gate electrode 14 made of the polysilicon layer (FIG. 1, step S5, FIG. 2A). reference).

Although not shown here, the conventional L
FIG. 2 for explaining a method of manufacturing a MOSFET having a DD structure.
As shown in FIG. 8, an insulating film for protecting the gate electrode 14 or the like may be formed on the gate electrode 14. The fact that an insulating film may be formed on the gate electrode 14 is also the same in the following second to twelfth embodiments. The steps S1 to S5 in FIG. 1 are the same as those of the conventional surface channel MOSFET.

Next, the gate insulating film 12 on the silicon substrate 10 is selectively etched using the gate electrode 14 as a mask, and the gate insulating film 12 on the region where the S / D is to be formed is removed (FIG. 1, step S6, FIG. 2). (B)). In this step, the surface of the silicon substrate 10 where the S / D is to be formed is exposed, an insulating film serving as an impurity diffusion source to be formed in the next step, and the silicon substrate 1 which is the S / D formation region are formed.
This is a process for bringing the surface 0 into direct contact. Next, for example, CVD (Chemical Vapor Deposi
1), an insulating film 16 containing a predetermined concentration of a second conductivity type impurity is deposited to a predetermined thickness (step S in FIG. 1).
7, see FIG. 2 (c)). Here, the second conductivity type impurity is
For example, it is an N-type impurity such as P or As.

Next, a heat treatment is performed at a predetermined temperature for a predetermined time, and the N-type impurity is thermally diffused into the surface of the silicon substrate 10 using the insulating film 16 containing the N-type impurity as an impurity diffusion source. Are formed opposite to each other. At this time, the source region 18 and the drain region 2
The surface of the silicon substrate 10 sandwiched between 0 and 0 becomes a channel region 22 (see step S8 in FIG. 1 and FIG. 2D). The thermal diffusion process of the N-type impurity from the insulating film 16 to the surface of the silicon substrate 10 proceeds statically as compared with the conventional ion implantation method.
6 and the drain region 18 rarely have a point defect. Further, unlike the case of the ion implantation method, it is not necessary to further perform a heat treatment for activating the impurity thereafter. Finally, necessary wiring is performed by removing and processing the insulating film 16 (Step S9 in FIG. 1). Thus, the N-MOSFE
Make T.

As described above, in the normal method of manufacturing the surface channel type N-MOSFET according to the first embodiment, when the source region 18 and the drain region 20 are formed on the surface of the silicon By thermally diffusing the N-type impurity from the insulating film 16 containing the type impurity to the surface of the silicon substrate 10, the injection of point defects into the surface of the silicon substrate 10 is reduced, and the diffusion of the N-type impurity is suppressed. Therefore, it is possible to keep the effective gate length long, so that the short channel effect can be suppressed from occurring. In addition, since the occurrence of point defects is small, the occurrence of the reverse short channel effect can be suppressed.

(Second Embodiment) A method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. Here, FIG. 3 is a flowchart showing a manufacturing process of the normal surface channel type MOSFET according to the present embodiment, and FIG. 4 is a simplified cross-sectional view showing a part of the manufacturing process. 1 are denoted by the same reference numerals, and the same components as those of the surface channel type MOSFET of FIG. 2 are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, steps S1 to S1 in FIG.
The step shown in S6 is the same as the steps S1 to S6 in FIG. 1 of the first embodiment, and is different from the step of depositing the insulating film containing the second conductivity type impurity in step S7 in FIG. Another feature is that a step of depositing a semiconductor film containing a second conductivity type impurity shown in step S10 of FIG. 3 is provided.

First, an insulating film is formed on the silicon substrate 10 in the same manner as the steps S1 to S6 in FIG. 1 of the first embodiment (step S1 in FIG. 3). After implanting P-type impurity ions as first conductivity type impurities into the substrate 10 (step S in FIG. 3)
2), the insulating film on the silicon substrate 10 is removed (Step S3 in FIG. 3). Subsequently, a gate insulating film 12 is formed on the silicon substrate 10 (Step S4 in FIG. 3), and a gate electrode 14 is formed on the gate insulating film 12 (Step S5 in FIG. 3). The gate insulating film 12 on the silicon substrate 10 is selectively etched away to expose the surface of the silicon substrate 10 where the S / D is to be formed (see step S6 in FIG. 3 and FIG. 4A).

Next, a semiconductor film 24 containing a predetermined concentration of an N-type impurity such as P or As as a second conductivity type impurity is deposited on the entire surface to a predetermined thickness (step S1 in FIG. 3).
0, see FIG. 4 (b)). The semiconductor film 24 is, for example, a polysilicon film or the like. Next, a heat treatment is performed at a predetermined temperature for a predetermined time to form a semiconductor film 2 containing an N-type impurity.
4 is used as an impurity diffusion source, N-type impurities are thermally diffused into the surface of the silicon substrate 10 to form a source region 18 and a drain region 2.
0 are formed opposite to each other, and the surface of the silicon substrate 10 sandwiched between the source region 18 and the drain region 20 is defined as a channel region 22 (see step S8a in FIG. 3 and FIG. 4C). Finally, after the semiconductor film 24 is removed by etching, an insulating film is deposited on the entire surface, and if necessary, the insulating film is removed or processed to perform necessary wiring (step S9a in FIG. 3). Thus, the N-MOS
Fabricate FET.

As described above, in the normal method of manufacturing the surface channel type N-MOSFET according to the second embodiment, when forming the source region 18 and the drain region 20 on the surface of the silicon substrate 10, Instead of the insulating film 16 containing an N-type impurity in the first embodiment, a semiconductor film 24 containing an N-type impurity is used as a diffusion source, and the semiconductor film 24 containing the N-type impurity is Because N-type impurities are diffused,
The same effects as in the case of the first embodiment can be obtained.

Third Embodiment A method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. Here, FIG. 5 is a flowchart showing a manufacturing process of the normal surface channel type MOSFET according to the present embodiment, and FIG. 6 is a simplified cross-sectional view showing a part of the manufacturing process. The same steps as those in the manufacturing process of FIG. 3 are denoted by the same reference numerals, and the same elements as those of the surface channel MOSFET of FIG. 4 are denoted by the same reference numerals, and description thereof is omitted. In the present embodiment, steps S1 to S1 in FIG.
The step shown in S6 is the same as the steps S1 to S6 in FIG. 3 of the second embodiment, and is different from the step of depositing the semiconductor film containing the second conductivity type impurity in Step S10 in FIG. 5 is characterized in that a step of depositing a semiconductor film and a step of adding a second conductivity type impurity to the semiconductor film shown in steps S11 to S12 of FIG. 5 are provided.

First, an insulating film is formed on the silicon substrate 10 in the same manner as the steps S1 to S6 in FIG. 3 of the second embodiment (step S1 in FIG. 5). After ion implantation of a P-type impurity as the first conductivity type impurity into the substrate 10 (step S in FIG. 5)
2), the insulating film on the silicon substrate 10 is removed (Step S3 in FIG. 5). Subsequently, a gate insulating film 12 is formed on the silicon substrate 10 (Step S4 in FIG. 5), and a gate electrode 14 is formed on the gate insulating film 12 (Step S5 in FIG. 5). The gate insulating film 12 on the silicon substrate 10 is selectively etched away to expose the surface of the silicon substrate 10 where the S / D is to be formed (see step S6 in FIG. 5 and FIG. 6A).

Next, a semiconductor film 26 containing no impurity is deposited to a predetermined thickness on the entire surface (step S in FIG. 5).
11). Subsequently, the semiconductor film 26 is doped with, for example, N such as P or As as the second conductivity type impurity by, for example, ion implantation.
Type impurity is implanted (step S12 in FIG. 5, FIG. 6B)
reference). Next, in the same manner as in the step S8a of FIG. 3 of the second embodiment, a heat treatment is performed at a predetermined temperature for a predetermined time, and the semiconductor film 26 into which the N-type impurity is implanted is used as an impurity diffusion source to form a surface of the silicon substrate 10 Then, an N-type impurity is thermally diffused to form a source region 18 and a drain region 20 facing each other, and the surface of the silicon substrate 10 sandwiched between the source region 18 and the drain region 20 is defined as a channel region 22 ( 5 step S8b, FIG.
(C)). Finally, after the semiconductor film 26 is removed by etching, an insulating film is deposited on the entire surface, and if necessary, the insulating film is removed or processed to perform necessary wiring (step S9b in FIG. 5). Thus, the N-MOSF
Make ET.

As described above, in the normal method of manufacturing a surface channel N-MOSFET according to the third embodiment, when forming the source region 18 and the drain region 20 on the surface of the silicon substrate 10, Instead of the semiconductor film 24 containing the N-type impurity in the second embodiment, for example, a semiconductor film 26 containing no impurity and ion-implanted with the second conductivity-type impurity is used as a diffusion source. Since the N-type impurity is diffused from the semiconductor film 26 into which the silicon film 10 has been implanted into the surface of the silicon substrate 10, the same effect as in the case of the second embodiment can be obtained. However, in the third embodiment, when the ion implantation method is used in the step S12 of FIG. 5, some point defects are implanted into the surface of the silicon substrate 10, so that the short channel effect or the reverse short The effect of suppressing the generation of the channel effect is expected to be slightly smaller than in the case of the first embodiment.

In the second and third embodiments, in the wiring forming steps of steps S9a and S9b in FIGS. 3 and 5, after the semiconductor films 24 and 26 are removed by etching, an insulating film is deposited. However, the semiconductor films 24 and 26 having an appropriate thickness may be left. The reason is described below.

In recent years, when a contact is made between an S / D region and a wiring, a method of interposing a metal layer made of, for example, Ti (titanium) has been widely used in order to make ohmic contact over the entire S / D region. It is being adopted. However, in this contact method, the S / D region on the surface of the semiconductor substrate reacts with the metal layer, and the influence of the metal layer extends deep into the semiconductor substrate. Therefore, it is necessary to form the S / D region thicker. In addition, a large amount of point defects are generated during this reaction by S / D.
It is also known that it occurs in an area. For this reason,
This contact method has an advantage that the ohmic contact between the S / D region and the wiring is excellent, but has a disadvantage that it promotes a short channel effect and a reverse short channel effect. Therefore, in the second and third embodiments, the semiconductor films 24, 2 having an appropriate thickness are formed on the source region 18 and the drain region 20 on the surface of the silicon substrate 10.
By leaving 6, it is possible to prevent the reaction with the metal layer such as Ti or the generation of point defects from remaining in the remaining semiconductor films 24 and 26 and not reaching the surface of the semiconductor substrate 10. Become. That is, it is possible to secure an ohmic contact between the source region 18 and the drain region 20 and the wiring without impairing the effect of suppressing the short channel effect and the reverse short channel effect.

(Fourth Embodiment) A method for manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. Here, FIG. 7 is a flowchart showing a manufacturing process of the normal surface channel type MOSFET according to the present embodiment, and FIG. 8 is a simplified cross-sectional view showing a part of the manufacturing process. 1 are denoted by the same reference numerals, and the same components as those of the surface channel type MOSFET of FIG. 2 are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, steps S1 to S1 in FIG.
The step shown in S6 is the same as the steps S1 to S6 in FIG. 1 of the first embodiment, and the step of depositing the insulating film containing the second conductivity type impurity in steps S7 to S8 in FIG. In place of the step of forming the S / D region by diffusing the second conductivity type impurity from the insulating film, heat treatment in an oxidizing atmosphere containing the second conductivity type impurity is performed in step S13 of FIG. It is characterized in that a step of forming a / D region is provided.

First, an insulating film is formed on a silicon substrate 10 in the same manner as the steps S1 to S6 in FIG. 1 of the first embodiment (step S1 in FIG. 7). After ion implantation of a P-type impurity as a first conductivity type impurity into the substrate 10 (step S in FIG. 7)
2), the insulating film on the silicon substrate 10 is removed (Step S3 in FIG. 7). Subsequently, a gate insulating film 12 is formed on the silicon substrate 10 (Step S4 in FIG. 7), and a gate electrode 14 is formed on the gate insulating film 12 (Step S5 in FIG. 7). The gate insulating film 12 on the silicon substrate 10 is selectively etched away to expose the surface of the silicon substrate 10 where the S / D is to be formed (see step S6 in FIG. 7 and FIG. 8A).

Next, the silicon substrate 1 is placed in an oxidizing atmosphere containing a predetermined concentration of an N-type impurity as a second conductivity type impurity.
The surface of the silicon substrate 10 is thermally oxidized to form a thermal oxide film 28 having a predetermined thickness on the surface of the silicon substrate 10 and on the upper surface and side surfaces of the gate electrode 14, and N-type impurities are thermally diffused on the surface of the silicon substrate 10 to form the source region 18. And the drain region 20 are formed opposite to each other, and the surface of the silicon substrate 10 sandwiched between the source region 18 and the drain region 20 is defined as a channel region 22 (see step S13 in FIG. 7, FIG. 8B). .

The reason why thermal oxidation is used in this S / D formation step is that the source region 18 and the drain region 20 cannot be formed as high-concentration impurity regions by simple vapor phase diffusion. In this thermal oxidation, N-type impurities diffused into the source region 18 and the drain region 20 are simultaneously activated, so that a heat treatment for impurity activation needs to be further performed as in the case of the conventional ion implantation method. There is no.

Finally, after an insulating film is formed on the entire surface if necessary, the insulating film and the thermal oxide film 28 are removed or processed to perform necessary wiring (step S9 in FIG. 7).
c). Thus, an N-MOSFET is manufactured.

As described above, in the normal method of manufacturing the surface channel type N-MOSFET according to the fourth embodiment, when forming the source region 18 and the drain region 20 on the surface of the silicon substrate 10, Silicon substrate 1 by performing thermal oxidation in an atmosphere containing mold impurities.
Silicon substrate 1 to diffuse N-type impurities
The diffusion of N-type impurities is suppressed by reducing the injection of point defects into the zero surface. Therefore, it is possible to keep the effective gate length long, so that the short channel effect can be suppressed from occurring. In addition, since the occurrence of point defects is small, the occurrence of the reverse short channel effect can be suppressed. However, in the fourth embodiment, although not as large as in the case of the ion implantation method, point defects are also implanted into the surface of the silicon substrate 10 by thermal oxidation in the step S13 of FIG. The effect or the effect of suppressing the occurrence of the inverse short channel effect is expected to be smaller than in the case of the third embodiment.

(Fifth Embodiment) A method of manufacturing a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. Here, FIG. 9 is a flowchart showing a manufacturing process of the normal surface channel type MOSFET according to the present embodiment, and FIG. 10 is a simplified cross-sectional view showing a part of the manufacturing process. The same steps as those in the manufacturing process of FIG. 7 are denoted by the same reference numerals, and the surface channel type MOSFET of FIG.
The same reference numerals are given to the same elements as the above-mentioned constituent elements, and the description is omitted. In the present embodiment, step S1 in FIG.
Steps S1 to S6 of the fourth embodiment are the same as steps S1 to S6 of FIG. 7 of the fourth embodiment, and the steps of FIG. It is characterized in that a step of forming a nitride film around the gate electrode shown in S14 is provided.

First, an insulating film is formed on a silicon substrate 10 in the same manner as the steps S1 to S6 in FIG. 7 of the fourth embodiment (step S1 in FIG. 9). After a P-type impurity is ion-implanted into the substrate 10 as the first conductivity type impurity (step S in FIG. 9).
2), the insulating film on the silicon substrate 10 is removed (Step S3 in FIG. 9). Subsequently, a gate insulating film 12 is formed on the silicon substrate 10 (Step S4 in FIG. 9), a gate electrode 14 is formed on the gate insulating film 12 (Step S5 in FIG. 9), and the gate electrode 14 is used as a mask. The gate insulating film 12 on the silicon substrate 10 is selectively etched away to expose the surface of the silicon substrate 10 where the S / D is to be formed (see step S6 in FIG. 9 and FIG. 10A).

Next, the periphery of the gate electrode 14, that is, the upper surface and side surfaces are covered with an oxidation-resistant film, for example, a thin nitride film 30 (see step S14 in FIG. 9 and FIG. 10B). This nitride film 30 is used as a gate electrode 14 in the next thermal oxidation step.
This is for preventing the side surface from being thermally oxidized to reduce the gate length. Then, the surface of the silicon substrate 10 is thermally oxidized in an atmosphere containing a predetermined concentration of an N-type impurity as a second conductivity type impurity in the same manner as in the step S13 of FIG. 10
An N-type impurity is thermally diffused on the surface of the silicon substrate 10 while the thermal oxide film 28 having a predetermined thickness is formed on the surface, thereby forming the source region 1.
8 and the drain region 20 are formed to face each other. At this time, the surface of the silicon substrate 10 sandwiched between the source region 18 and the drain region 20 is set as a channel region 22 (see step S13a in FIG. 9 and FIG. 10C). Finally, after an insulating film is formed on the entire surface as required, the insulating film, the thermal oxide film 28, and the nitride film 30 are removed or processed to perform necessary wiring (step S9d in FIG. 9). Thus, an N-MOSFET is manufactured.

As described above, in the normal method of manufacturing the surface channel type N-MOSFET according to the fifth embodiment of the present invention, when the source region 18 and the drain region 20 are formed on the surface of the silicon substrate 10, After the side surface of the gate electrode 14 is covered with the nitride film 30 so as not to be thermally oxidized, by thermal oxidation in an atmosphere containing N-type impurities,
In order to diffuse N-type impurities on the surface of the silicon substrate 10,
In addition to preventing the gate length from decreasing, the silicon substrate 10
Injection of point defects into the surface is reduced to suppress diffusion of N-type impurities. Therefore, the effective gate length can be kept longer than in the case of the fourth embodiment, so that the occurrence of the short channel effect can be more effectively suppressed and the occurrence of point defects is reduced. In addition, the occurrence of the reverse short channel effect can be suppressed. It is to be noted that some point defects are injected into the surface of the silicon substrate 10 by the thermal oxidation in the process of step S13a in FIG. 9 as in the case of the fourth embodiment.

(Sixth Embodiment) A method of manufacturing a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. Here, FIG. 11 is a flowchart showing a manufacturing process of the normal surface channel type MOSFET according to the present embodiment, and FIG. 12 is a simplified cross-sectional view showing a part of the manufacturing process. The same steps as those in the manufacturing steps in FIGS. 5 and 7 are denoted by the same reference numerals, and the same elements as those in the surface channel MOSFETs in FIGS. 6 and 8 are denoted by the same reference numerals. The description is omitted. In the present embodiment, the processes shown in steps S1 to S6 and S11a in FIG. 11 are the same as the steps S1 to S6 in FIG.
This is the same as the process of S11, and is performed in step S13b of FIG.
Is the step shown in FIG. 7 of the fourth embodiment.
The feature is that it is similar to the thirteenth step.

First, an insulating film is formed on the silicon substrate 10 in the same manner as the steps S1 to S6 and S11 in FIG. 5 of the third embodiment (step S1 in FIG. 11), and this insulating film is buffered. After ion implantation of a P-type impurity as a first conductivity type impurity into the silicon substrate 10 (FIG. 11)
Step S2), the insulating film on the silicon substrate 10 is removed (Step S3 in FIG. 11). Subsequently, the silicon substrate 10
A gate insulating film 12 is formed thereon (step S in FIG. 11).
4) After the gate electrode 14 is formed on the gate insulating film 12 (Step S5 in FIG. 11), the gate insulating film 12 on the silicon substrate 10 is selectively etched and removed using the gate electrode 14 as a mask. 10 S / D
Expose the surface of the region to be formed (Step S in FIG. 11)
6). Subsequently, a semiconductor film 26 containing no impurity is deposited to a predetermined thickness on the entire surface (step S11 in FIG. 11).
a, see FIG. 12 (a)).

Next, in the same manner as in the step S13 in FIG. 7 of the fourth embodiment, the surface of the semiconductor film 26 is heated in an oxidizing atmosphere containing a predetermined concentration of an N-type impurity as a second conductivity type impurity. Oxidized to form thermal oxide film 3 of predetermined thickness
While forming the silicon substrate 1 through the semiconductor film 26.
The source region 18 and the drain region 20 are formed facing each other by thermally diffusing an N-type impurity into the surface of the silicon substrate 10, and the surface of the silicon substrate 10 sandwiched between the source region 18 and the drain region 20 is (See step S13b in FIG. 11 and FIG. 12 (b)). At this time, depending on the thickness of the semiconductor film 26, the conditions of thermal oxidation, and the like, the entire semiconductor film 26 may be oxidized to become the thermal oxide film 32. Finally, after the thermal oxide film 32 and the semiconductor film 26 are removed by etching, an insulating film is deposited on the entire surface, and if necessary, the insulating film is removed or processed to perform necessary wiring (FIG. Eleven steps S9e). Thus, an N-MOSFET is manufactured.

As described above, in the normal method of manufacturing the surface channel type N-MOSFET according to the sixth embodiment, when forming the source region 18 and the drain region 20 on the surface of the silicon substrate 10, After forming the semiconductor film 26 containing no impurities as in the third embodiment, the semiconductor film 26 is subjected to thermal oxidation in an atmosphere containing N-type impurities as in the fourth embodiment.
Since the N-type impurity is thermally diffused to the surface of the silicon substrate 10 through the substrate, the same effect as in the third embodiment can be obtained. However, in the sixth embodiment, some point defects are injected into the surface of the silicon substrate 10 due to the thermal oxidation in the process of step S13b in FIG. 11, and therefore, similar to the case of the fourth embodiment, The effect of suppressing the generation of the short channel effect or the inverse short channel effect is expected to be smaller than in the case of the first embodiment, and the degree thereof is different between the first embodiment and the fourth embodiment. To position. Further, the superiority with the third embodiment differs depending on the ion implantation conditions and the oxidation conditions, and therefore, it cannot be said either.

In the sixth embodiment, the heat treatment is performed in an oxidizing atmosphere in the step S13b of FIG. 11, but the heat treatment may be performed in a non-oxidizing atmosphere. In this case, since the surface of the semiconductor film 26 is not thermally oxidized, the thermal oxide film 32 is not formed. Also,
In the wiring forming step of step S9e in FIG.
After the thermal oxide film 32 and the semiconductor film 26 are removed by etching, an insulating film is deposited. As in the case of the third embodiment, the semiconductor film 26 having an appropriate thickness is left. Is also good.

As described above, in the first to sixth embodiments, the ordinary surface channel type N-MOSFET has been described.
OSFET will be described.

(Seventh Embodiment) A method of manufacturing a semiconductor device according to a seventh embodiment of the present invention will be described with reference to FIGS. Here, FIG. 13 illustrates L according to the present embodiment.
14 is a flowchart showing a manufacturing process of a surface channel type MOSFET having a DD structure, and FIG. 14 is a simplified cross-sectional view showing a part of the manufacturing process. The same steps as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the same elements as those of the surface channel MOSFET of FIG. 2 are denoted by the same reference numerals. The description is omitted. In the present embodiment, the processes shown in steps S1 to S6a in FIG.
This is the same as the steps S1 to S6 in FIG. 1 of the first embodiment, and the steps S15 to S1 in FIG. 13 are interposed between the steps S6 and S7 in FIG.
6 is characterized in that a step of forming an LDD region and a step of forming a sidewall spacer are provided.

First, an insulating film is formed on the silicon substrate 10 in the same manner as the steps S1 to S6 in FIG. 1 of the first embodiment (step S1 in FIG. 13). After ion implantation of a first conductivity type impurity, for example, a P-type impurity into the substrate 10 (Step S2 in FIG. 13), the insulating film on the silicon substrate 10 is removed (Step S3 in FIG. 13). Subsequently, a gate insulating film 12 is formed on the silicon substrate 10 (Step S4 in FIG. 13),
After the gate electrode 14 is formed on the gate insulating film 12 (Step S5 in FIG. 13), the gate insulating film 12 on the silicon substrate 10 is selectively removed by etching using the gate electrode 14 as a mask. The surface to be formed and the surface to be S / D formed are exposed (FIG. 1)
Three steps S6a, see FIG. 14 (a)).

Next, an LDD region is formed on the surface of the silicon substrate 10.
This is performed by the same steps as the steps S7 to S8 in FIG. That is, an insulating film 34 containing a predetermined concentration of an N-type impurity as a second conductivity type impurity is deposited on the entire surface to a predetermined thickness by using, for example, a CVD method. Subsequently, the N-type impurity is thermally diffused from the insulating film 34 containing the N-type impurity to the surface of the silicon substrate 10 by heat treatment at a predetermined temperature for a predetermined time, thereby forming the LDD regions 36 and 38 facing each other. At this time, the surface of the silicon substrate 10 sandwiched between the LDD regions 36 and 38 is the channel region 22 (FIG. 13).
Step S15, see FIG. 14 (b)). The insulating film 3
The predetermined concentration of the N-type impurity contained in the LDD region 3 is
6 and 38, and the density is lower than in the case of the S / D region forming step of steps S7 to S8 in FIG. 1 of the first embodiment.

Next, the insulating film 34 is etched back to form the sidewall spacers 40 made of the insulating film 34 on the side surfaces of the gate electrode 14 and, at the same time, to expose the surface of the silicon substrate 10 where the S / D is to be formed (see FIG. 13 Step S16, see FIG. 14 (c)). In this case,
Instead of etching back the insulating film 34, after removing the insulating film 34 by etching, another insulating film is deposited on the entire surface,
The sidewall spacer 40 may be formed on the side surface of the gate electrode 14 by etching back the insulating film.

Next, like the steps S7 to S8 in FIG. 1 of the first embodiment, for example, C
After the insulating film 42 containing a predetermined concentration of the N-type impurity as the second conductivity type impurity is deposited to a predetermined thickness by using the VD method (see step S7a in FIG. 13 and FIG. 14 (d)), at a predetermined temperature, A heat treatment is performed for a predetermined time, and the silicon substrate 1 is used with the insulating film 42 containing an N-type impurity as an impurity diffusion source.
The source region 18 and the drain region 20 are formed by thermally diffusing an N-type impurity on the surface 0 (see step S8c in FIG. 13 and FIG. 14E). Finally, necessary wiring is performed by removing or processing the insulating film 42 (step S9 in FIG. 13).
f). Thus, an N-MOSFET is manufactured.

As described above, in the method of manufacturing the surface channel N-MOSFET having the LDD structure according to the seventh embodiment, the LDD regions 36 and 38 and the source region 18 and the drain region 20 are formed on the surface of the silicon substrate 10.
Are formed, insulating films 34 and 4 containing N-type impurities are formed.
By diffusing the N-type impurity from the surface of the LDD into the surface of the silicon substrate 10, the injection of point defects into the surface of the silicon substrate 10 can be reduced and the diffusion of the N-type impurity can be suppressed. The same effect as that of the first embodiment can be obtained also in the channel type MOSFET.

In the seventh embodiment, the same method as the S / D region formation in the first embodiment is adopted in the LDD region formation step of step S15 in FIG. Instead, any one of the S / D region forming methods in the second to sixth embodiments may be selected and adopted.

(Eighth Embodiment) A method of manufacturing a semiconductor device according to an eighth embodiment of the present invention will be described with reference to FIGS. Here, FIG. 15 shows L according to the present embodiment.
FIG. 16 is a flowchart showing a manufacturing process of the surface channel type MOSFET having the DD structure, and FIG. 16 is a simplified cross-sectional view showing a part of the manufacturing process. The same steps as those in the manufacturing process of FIG. 3 of the second embodiment are denoted by the same reference numerals, and the same elements as those of the surface channel MOSFET of FIG. 4 are denoted by the same reference numerals. The description is omitted. In the present embodiment, the processes shown in steps S1 to S6a in FIG.
The steps are the same as the steps S1 to S6 in FIG. 3 of the second embodiment, and the steps S15a to S15 in FIG. 15 are interposed between the steps S6 and S10 in FIG.
It is characterized in that a step of forming an LDD region and a step of forming a sidewall spacer shown in S16a are provided.

First, an insulating film is formed on the silicon substrate 10 in the same manner as the steps S1 to S6 in FIG. 3 of the second embodiment (step S1 in FIG. 15). After ion implantation of a P-type impurity as the first conductivity type impurity into the substrate 10 (Step S2 in FIG. 15), the insulating film on the silicon substrate 10 is removed (FIG. 1).
5 steps S3). Subsequently, a gate insulating film 12 is formed on the silicon substrate 10 (Step S4 in FIG. 15), and a gate electrode 14 is formed on the gate insulating film 12 (FIG. 1).
5 step S5), using the gate electrode 14 as a mask, the gate insulating film 12 on the silicon substrate 10 is selectively etched away to expose the surface of the silicon substrate 10 where the LDD is to be formed and the surface where the S / D is to be formed. 15 step S6a, see FIG. 16 (a)).

Next, an LDD region is formed on the surface of the silicon substrate 10.
The process is performed in the same manner as the processes of steps S10 to S8a in FIG. That is, a semiconductor film 44 containing a predetermined concentration of an N-type impurity as a second conductivity type impurity is deposited on the entire surface to a predetermined thickness, and subsequently, a heat treatment is performed at a predetermined temperature for a predetermined time to obtain an N-type impurity. Semiconductor film 44
N-type impurities are thermally diffused from the
The DD regions 36 and 38 are formed facing each other, and the surface of the silicon substrate 10 sandwiched between the LDD regions 36 and 38 is used as the channel region 22 (step S15 in FIG. 15).
a, see FIG. 16 (b)). At this time, the semiconductor film 4
The predetermined concentration of the N-type impurity contained in the LDD region 3 is
6 and 38, and the density is lower than in the case of the S / D region forming step of steps S10 to S8a in FIG. 3 of the second embodiment.

Next, after the semiconductor film 44 is removed by etching, an insulating film is deposited on the entire surface, and the insulating film is further etched back to form the sidewall spacers 40 made of the insulating film on the side surfaces of the gate electrode 14. Then, the surface of the silicon substrate 10 where the S / D is to be formed is exposed (see step S16a and FIG. 16 (c) in FIG. 15). Next, steps S10 to S8 in FIG. 3 of the second embodiment are performed.
Similarly to the step a, a semiconductor film 46 containing a predetermined concentration of an N-type impurity as a second conductivity type impurity is deposited on the entire surface to a predetermined thickness (step S10a in FIG. 15, FIG. 16D)
Subsequently, heat treatment is performed at a predetermined temperature for a predetermined time to thermally diffuse the N-type impurity from the semiconductor film 46 containing the N-type impurity to the surface of the silicon substrate 10, thereby forming the source region 18.
And the drain region 20 (FIG. 15, step S8)
d, see FIG. 16 (e)). Finally, after the semiconductor film 46 is removed by etching, an insulating film is deposited on the entire surface, and if necessary, the insulating film is removed or processed to perform necessary wiring (step S9g in FIG. 15). Thus, an N-MOSFET is manufactured.

As described above, in the method of manufacturing the surface channel type N-MOSFET having the LDD structure according to the eighth embodiment, the LDD regions 36 and 38 and the source region 18 and the drain region 20 are formed on the surface of the silicon substrate 10.
Is formed, a semiconductor film 44 containing an N-type impurity,
Since the N-type impurity is diffused from 46 to the surface of the silicon substrate 10, the surface channel type MOSFET having the LDD structure is formed.
In this case, the same effect as in the case of the second embodiment can be obtained.

In the eighth embodiment, the same method as the S / D region formation in the second embodiment is employed in the LDD region formation step of step S15a in FIG. Not limited to the above, the first, third to sixth
Any of the methods for forming the S / D region in the above embodiment may be selected and adopted.

(Ninth Embodiment) A method for manufacturing a semiconductor device according to a ninth embodiment of the present invention will be described with reference to FIGS. Here, FIG. 17 shows L according to the present embodiment.
FIG. 18 is a flowchart showing a manufacturing process of the surface channel type MOSFET having the DD structure, and FIG. 18 is a simplified cross-sectional view showing a part of the manufacturing process. The same steps as those of the third embodiment shown in FIG. 5 are denoted by the same reference numerals, and the same elements as those of the surface channel type MOSFET shown in FIG. 6 are denoted by the same reference numerals. The description is omitted. In the present embodiment, the processes shown in steps S1 to S6a in FIG.
The steps are the same as the steps S1 to S6 in FIG. 5 of the third embodiment, and the steps S15b to S15b in FIG. 17 are interposed between the steps S6 and S11 in FIG.
It is characterized in that the step of forming the LDD region and the step of forming the sidewall spacer shown in S16b are provided.

First, an insulating film is formed on the silicon substrate 10 in the same manner as the steps S1 to S6 in FIG. 5 of the third embodiment (step S1 in FIG. 17). After ion implantation of a P-type impurity as the first conductivity type impurity into the substrate 10 (Step S2 in FIG. 17), the insulating film on the silicon substrate 10 is removed (FIG. 1).
7 steps S3). Subsequently, a gate insulating film 12 is formed on the silicon substrate 10 (Step S4 in FIG. 17), and a gate electrode 14 is formed on the gate insulating film 12 (FIG. 1).
7 Step S5) Using the gate electrode 14 as a mask, the gate insulating film 12 on the silicon substrate 10 is selectively etched away to expose the surface of the silicon substrate 10 where the LDD is to be formed and the surface where the S / D is to be formed. 17 Step S6a, see FIG. 18 (a)).

Next, an LDD region is formed on the surface of the silicon substrate 10.
This is performed by the same steps as the steps S11 to S8b in FIG. That is, after depositing a semiconductor film 48 containing no impurity to a predetermined thickness on the entire surface, an N-type impurity as a second conductivity type impurity is ion-implanted into the semiconductor film 48 by an ion implantation method. A heat treatment is performed at a predetermined temperature for a predetermined time to thermally diffuse the N-type impurity from the semiconductor film 48 into which the N-type impurity has been ion-implanted to the surface of the silicon substrate 10, thereby forming the LDD regions 36 and 38 facing each other. The surface of the silicon substrate 10 sandwiched between the regions 36 and 38 is defined as a channel region 22 (see step S15b in FIG. 17 and FIG. 18B). At this time, the predetermined concentration of the N-type impurity to be ion-implanted into the semiconductor film 48 needs to be suitable for the LDD regions 36 and 38, and the ion-implantation step of step S12 in FIG. The concentration is lower than in the case of

Next, after the semiconductor film 48 is removed by etching, an insulating film is deposited on the entire surface, and the insulating film is etched back to form the sidewall spacers 40 made of the insulating film on the side surfaces of the gate electrode 14. Then, the surface of the region where the S / D is to be formed on the silicon substrate 10 is exposed (see step S16b in FIG. 17 and FIG. 18C).

Then, a semiconductor film 50 containing no impurity is deposited on the entire surface to a predetermined thickness in the same manner as in the steps S11 to S8b of FIG. 5 of the third embodiment (FIG. 17). Step S11b), an N-type impurity as a second conductivity type impurity is ion-implanted into the semiconductor film 50 by an ion implantation method (FIG. 17, Step S12a, FIG. 18).
(See (d)) Then, a heat treatment is performed at a predetermined temperature for a predetermined time to ion-implant the N-type impurity into the semiconductor film 50.
The N-type impurity is thermally diffused from the silicon substrate 10 to the surface to form a source region 18 and a drain region 20 (FIG. 17).
Step S8e, see FIG. 18 (e)). Finally, after the semiconductor film 50 is removed by etching, an insulating film is deposited on the entire surface, and if necessary, the insulating film is removed or processed to perform necessary wiring (step S9h in FIG. 17).
Thus, an N-MOSFET is manufactured.

As described above, in the method of manufacturing the surface channel type N-MOSFET having the LDD structure according to the ninth embodiment, the LDD regions 36 and 38 and the source region 18 and the drain region 20 are formed on the surface of the silicon substrate 10.
When forming the semiconductor film 4 containing no impurities
Since the N-type impurities are ion-implanted into the surface of the silicon substrate 10 from the semiconductor films 48 and 50 in which the N-type impurities are ion-implanted, the LDDs are used as LDDs. Surface channel type M of structure
The same effect as that of the third embodiment can be obtained also in the OSFET.

In the ninth embodiment, the same method as the S / D region formation in the third embodiment is employed in the LDD region formation step of step S15b in FIG. The first, second, fourth
Any of the S / D region forming methods in the sixth to sixth embodiments may be selected and adopted.

(Tenth Embodiment) A method of manufacturing a semiconductor device according to a tenth embodiment of the present invention will be described with reference to FIGS.
Explanation will be made using 0. Here, FIG. 19 is a flowchart showing a manufacturing process of the surface channel type MOSFET having the LDD structure according to the present embodiment, and FIG. 20 is a simplified cross-sectional view showing a part of the manufacturing process. FIG. 7 of the fourth embodiment.
8 are given the same reference numerals, and the same components as those of the surface channel type MOSFET shown in FIG. 8 are given the same reference numerals and description thereof is omitted. In the present embodiment, the processes shown in steps S1 to S6a in FIG. 19 are the same as the processes in steps S1 to S6 in FIG. 7 of the fourth embodiment, and the processes in step S6 and step S13 in FIG. Step S15 in FIG.
It is characterized in that a step of forming an LDD region and a step of forming a sidewall spacer are provided as shown in c to S16c.

First, an insulating film is formed on the silicon substrate 10 in the same manner as the steps S1 to S6 in FIG. 7 of the fourth embodiment (step S1 in FIG. 19). After ion implantation of a first conductivity type impurity, for example, a P-type impurity into the substrate 10 (Step S2 in FIG. 19), the insulating film on the silicon substrate 10 is removed (Step S3 in FIG. 19). Subsequently, a gate insulating film 12 is formed on the silicon substrate 10 (Step S4 in FIG. 19),
After the gate electrode 14 is formed on the gate insulating film 12 (Step S5 in FIG. 19), the gate insulating film 12 on the silicon substrate 10 is selectively removed by etching using the gate electrode 14 as a mask. The surface to be formed and the surface to be S / D formed are exposed (FIG. 1)
Nine steps S6a, see FIG. 20 (a)).

Next, an LDD region is formed on the surface of the silicon substrate 10.
The process is performed by a process similar to the process of step S13 in FIG. That is, the silicon substrate 10 is placed in an oxidizing atmosphere containing a predetermined concentration of an N-type impurity as a second conductivity type impurity.
The surface is thermally oxidized to form a thermal oxide film 52 having a predetermined thickness on the surface of the silicon substrate 10 and the upper surface and side surfaces of the gate electrode 14, while thermally diffusing an N-type impurity into the surface of the silicon substrate 10 to form the LDD region 36, 38 are formed facing each other, and the surface of the silicon substrate 10 sandwiched between the LDD regions 36 and 38 is defined as a channel region 22 (see step S15c in FIG. 19 and FIG. 20B).

Next, after an insulating film is formed on the entire surface as required, the insulating film and the thermal oxide film 52 are etched back, and the side wall spacers 40 made of the insulating film and the thermal oxide film 52 are formed on the side surfaces of the gate electrode 14. At the same time, the surface of the silicon substrate 10 where the S / D is to be formed is exposed (step S16c in FIG. 1, see FIG. 20 (c)).
In this case, after the thermal oxide film 52 is removed by etching, an insulating film may be deposited on the entire surface, and the insulating film may be etched back to form the sidewall spacers 40 on the side surfaces of the gate electrode 14.

Next, in the same manner as in the step S13 in FIG. 7 of the fourth embodiment, thermal oxidation of the surface of the silicon substrate 10 is performed in an oxidizing atmosphere containing a predetermined concentration of an N-type impurity as a second conductivity type impurity. Then, while forming a thermal oxide film 54 having a predetermined thickness on the surface of the silicon substrate 10 and on the upper surface and side surfaces of the gate electrode 14, N-type impurities are thermally diffused on the surface of the silicon substrate 10 to form the source region 18 and the drain region 2.
0 (FIG. 19, step S13c, FIG. 20 (d)).
reference).

Finally, after an insulating film is formed on the entire surface as necessary, the insulating film and the thermal oxide film 54 are removed or processed to perform necessary wiring (step S9 in FIG. 19).
i). Thus, an N-MOSFET is manufactured.

As described above, in the method of manufacturing the surface channel N-MOSFET having the LDD structure according to the tenth embodiment, the LDD regions 36 and 38 and the source region 18 and the drain region 2 are formed on the surface of the silicon substrate 10.
0 is formed, thermal oxidation is performed in an atmosphere containing an N-type impurity to diffuse the N-type impurity on the surface of the silicon substrate 10.
The same effect as that of the fourth embodiment can be obtained in the SFET.

In the tenth embodiment,
In the LDD region forming step of step S15c in FIG. 19, the same method as that of the S / D region forming in the fourth embodiment is employed, but the present invention is not limited to this, and the first to third, fifth, and Any of the methods for forming the S / D region in the sixth embodiment may be selected and adopted.

(Eleventh Embodiment) A method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention will be described with reference to FIGS.
2 will be described. Here, FIG. 21 is a flowchart showing a manufacturing process of the surface channel MOSFET having the LDD structure according to the present embodiment, and FIG. 22 is a simplified cross-sectional view showing a part of the manufacturing process. FIG. 9 of the fifth embodiment.
10 are given the same reference numerals, and the same components as those of the surface channel type MOSFET shown in FIG. 10 are given the same reference numerals and description thereof is omitted. In the present embodiment, the processes shown in steps S1 to S6a in FIG. 21 correspond to steps S1 to S6 in FIG.
21. Between the step S6 and the step S14 in FIG. 9, the step S1 in FIG.
It is characterized in that a step of forming an LDD region and a step of forming a sidewall spacer shown in 5d to S16d are provided.

First, an insulating film is formed on the silicon substrate 10 in the same manner as the steps S1 to S6 in FIG. 9 of the fifth embodiment (step S1 in FIG. 21). After the first conductivity type impurity, for example, a P-type impurity is ion-implanted into the substrate 10 (Step S2 in FIG. 21), the insulating film on the silicon substrate 10 is removed (Step S3 in FIG. 21). Subsequently, a gate insulating film 12 is formed on the silicon substrate 10 (Step S4 in FIG. 21),
After the gate electrode 14 is formed on the gate insulating film 12 (Step S5 in FIG. 21), the gate insulating film 12 on the silicon substrate 10 is selectively removed by etching using the gate electrode 14 as a mask. The surface to be formed and the surface to be formed S / D are exposed (FIG. 2).
One step S6a, see FIG. 22 (a)).

Next, an LDD region is formed on the surface of the silicon substrate 10.
This is performed by the same steps as steps S14 to S13a in FIG. That is, after the periphery of the gate electrode 14 is covered with a thin nitride film 56, the surface of the silicon substrate 10 is thermally oxidized in an atmosphere containing a predetermined concentration of an N-type impurity as a second conductivity type impurity. An N-type impurity is thermally diffused on the surface of the silicon substrate 10 while forming a thermal oxide film 58 of a predetermined thickness on the surface of the LDD region 36,
38 and the LDD regions 3
The surface of the silicon substrate 10 sandwiched between 6, 6 is used as the channel region 22 (FIG. 21, step S15d, FIG. 22).
(B)).

Next, after an insulating film is formed on the entire surface as necessary, the insulating film, the nitride film 56 and the thermal oxide film 56 are etched back, and the insulating film, the nitride film 56 and the thermal At the same time as the formation of the sidewall spacers 40 made of the oxide film 52, the S / S
Expose the surface of the region where the D is to be formed (step S1 in FIG. 21).
6d, see FIG. 22 (c)). In this case, the nitride film 5
After the etching oxide film 6 and the thermal oxide film 56 are removed by etching, an insulating film may be deposited on the entire surface, and the insulating film may be etched back to form the sidewall spacers 40 on the side surfaces of the gate electrode 14.

Next, in the same manner as in the steps S14 to S13a of FIG. 9 of the fifth embodiment, the periphery of the gate electrode 14 and the side wall spacers 40 is a thin nitride film 60 as an oxidation resistant film. (Step S14a in FIG. 21; see FIG. 22D). Then, the surface of the silicon substrate 10 is thermally oxidized in an atmosphere containing a predetermined concentration of an N-type impurity as a second conductivity type impurity, and the silicon substrate 1
The N-type impurity is thermally diffused on the surface of the silicon substrate 10 while the thermal oxide film 62 having a predetermined thickness is formed on the surface of the silicon substrate 10 to form the source region 18 and the drain region 20 (FIG. 21, step S13d, FIG. )reference).

Finally, after an insulating film is formed on the entire surface as required, the insulating film, the nitride film 60, and the thermal oxide film 62 are removed or processed to perform necessary wiring (FIG. 21 step). S9j). Thus, an N-MOSFET is manufactured.

As described above, in the method of manufacturing the surface channel N-MOSFET having the LDD structure according to the eleventh embodiment, the LDD regions 36 and 38, the source region 18 and the drain region 2 are formed on the surface of the silicon substrate 10.
In order to diffuse the N-type impurities into the surface of the silicon substrate 10 by thermal oxidation in an atmosphere containing the N-type impurities when forming the N-type MOSFET, a surface channel type MOSFE having an LDD structure is formed.
Also in T, the same effect as in the fifth embodiment can be obtained.

Note that steps S15d and S13 in FIG.
The fact that some point defects are injected into the surface of the silicon substrate 10 by the thermal oxidation in the step d is the same as in the case of the fifth embodiment. In addition, the eleventh
In the embodiment, L in step S15d in FIG.
In the DD region forming step, the S /
Although the same method as that for forming the D region is adopted, the present invention is not limited to this, and any one of the methods for forming the S / D region in the first to fourth and sixth embodiments may be selected and adopted. Good.

(Twelfth Embodiment) A method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention will be described with reference to FIGS.
4 will be described. Here, FIG. 23 is a flowchart showing a manufacturing process of the surface channel type MOSFET having the LDD structure according to the present embodiment, and FIG. 24 is a simplified cross-sectional view showing a part of the manufacturing process. FIG. 1 of the sixth embodiment.
The same processes as those in the first manufacturing process are denoted by the same reference numerals, and the same components as those of the surface channel type MOSFET shown in FIG. 12 are denoted by the same reference numerals, and description thereof is omitted. In the present embodiment, the processes shown in steps S1 to S6a in FIG. 23 are the same as those in steps S1 to S6 in FIG.
The step of forming the LDD region and the step of forming the sidewall spacer shown in steps S15e to S16e of FIG. The feature is that it is provided.

First, an insulating film is formed on the silicon substrate 10 in the same manner as the steps S1 to S6 in FIG. 1 of the sixth embodiment (step S1 in FIG. 23). After ion implantation of a first conductivity type impurity, for example, a P-type impurity into the substrate 10 (Step S2 in FIG. 23), the insulating film on the silicon substrate 10 is removed (Step S3 in FIG. 23). Subsequently, a gate insulating film 12 is formed on the silicon substrate 10 (Step S4 in FIG. 23),
After the gate electrode 14 is formed on the gate insulating film 12 (Step S5 in FIG. 23), the gate insulating film 12 on the silicon substrate 10 is selectively removed by etching using the gate electrode 14 as a mask. The surface to be formed and the surface to be formed S / D are exposed (FIG. 2).
Three steps S6a, see FIG. 24 (a)).

Next, an LDD region is formed on the surface of the silicon substrate 10.
This is performed by the same steps as the steps S11a to S13b in FIG. That is, a semiconductor film 64 containing no impurity is deposited on the entire surface to a predetermined thickness, and subsequently, the surface of the semiconductor film 64 is placed in an oxidizing atmosphere containing a predetermined concentration of an N-type impurity as a second conductivity type impurity. The semiconductor film 6 is thermally oxidized to form a thermal oxide film 66 having a predetermined thickness.
4, N-type impurities are thermally diffused into the surface of the silicon substrate 10 to form LDD regions 36 and 38 facing each other, and the surface of the silicon substrate 10 sandwiched between the LDD regions 36 and 38 is (See step S15e in FIG. 23 and FIG. 24 (b)).

Next, after the thermal oxide film 66 and the semiconductor film 64 are removed by etching, an insulating film is deposited on the entire surface, and the insulating film is etched back to form a side wall spacer 40 made of the insulating film on the side surface of the gate electrode 14. At the same time, the surface of the silicon substrate 10 where the S / D is to be formed is exposed (see step S16e in FIG. 23 and FIG. 24 (c)).

Next, a semiconductor film 68 containing no impurity is deposited on the entire surface to a predetermined thickness in the same manner as in the steps S11a to S13b of FIG. 11 of the sixth embodiment (FIG. 23). S11c) While thermally oxidizing the surface of the semiconductor film 68 in an oxidizing atmosphere containing a predetermined concentration of an N-type impurity as a second conductivity type impurity to form a predetermined thickness of the thermal oxide film 70, the semiconductor film 68 is N-type impurities are thermally diffused into the surface of the silicon substrate 10 through the
8 and the drain region 20 are formed (Step S in FIG. 23).
13e, see FIG. 24 (d)).

Finally, after the thermal oxide film 70 and the semiconductor film 68 are removed by etching, an insulating film is deposited on the entire surface, and if necessary, the insulating film is removed or processed to make necessary wiring. (Step S9k in FIG. 23). Thus, an N-MOSFET is manufactured.

As described above, in the method of manufacturing the surface channel N-MOSFET having the LDD structure according to the twelfth embodiment, the LDD regions 36 and 38, the source region 18 and the drain region 2 are formed on the surface of the silicon substrate 10.
0, the semiconductor film 6 containing no impurities
4 and 68, thermal oxidation is performed in an atmosphere containing an N-type impurity to thermally diffuse the N-type impurity to the surface of the silicon substrate 10 through the semiconductor films 64 and 68. The same effect as that of the sixth embodiment can be obtained in the channel MOSFET.

Note that steps S15e and S13 in FIG.
The fact that some point defects are injected into the surface of the silicon substrate 10 due to the thermal oxidation in the step e is the same as in the case of the sixth embodiment. In addition, the twelfth
In the embodiment, L in step S15e in FIG.
In the DD region forming step, the S /
Although the same method as that for forming the D region is employed, the present invention is not limited to this, and any one of the methods for forming the S / D region in the first to fifth embodiments may be selected and employed. Further, in the first to twelfth embodiments, the N-MOSFE
Although the case of T has been described, it is needless to say that the present invention can be applied to the case of a P-MOSFET. In this case, completely the same manufacturing method is realized by giving impurities of the conductivity type opposite to those of the first to twelfth embodiments, that is, by changing the P type and the N type.

[0107]

As described above in detail, according to the method of manufacturing a semiconductor device according to the present invention, when an impurity region is formed on a semiconductor substrate surface, for example, an S / D region or an LDD is formed.
When regions are formed, impurities can be diffused from the film that acts as a medium for diffusion of impurities to the surface of the semiconductor substrate, thereby reducing the injection of point defects into the surface of the semiconductor substrate and suppressing the diffusion of impurities. become. Therefore, the effective gate length can be kept long, and the occurrence of the short channel effect can be suppressed. In addition, the occurrence of point defects is reduced, and the occurrence of the inverse short channel effect can be suppressed. Electrical characteristics of the semiconductor device, such as a threshold voltage, can be easily controlled.

Further, when forming an impurity region on the surface of the semiconductor substrate, for example, when forming an S / D region or an LDD region, a heat treatment is performed in an oxidizing atmosphere containing impurities of the second conductivity type. By diffusing the second conductivity type impurity, it becomes possible to reduce the injection of point defects into the surface of the semiconductor substrate and suppress the diffusion of the impurity, so that the same effect as in the above case can be obtained. it can.

Further, when forming an impurity region on the surface of the semiconductor substrate, for example, when forming an S / D region or an LDD region, a semiconductor film containing no impurity is formed and then a second conductive type impurity is formed. Heat treatment in an atmosphere in which the second conductivity type impurities are thermally diffused through the semiconductor film to the surface of the semiconductor substrate, thereby reducing the injection of point defects into the surface of the semiconductor substrate and suppressing the diffusion of the impurities. Therefore, the same effect as in the above case can be obtained.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a manufacturing process of a normal surface channel type MOSFET according to a first embodiment of the present invention.

FIG. 2 is a simplified cross-sectional view showing a part of a manufacturing process of the normal surface channel MOSFET of FIG.

FIG. 3 is a flowchart showing a manufacturing process of a normal surface channel type MOSFET according to a second embodiment of the present invention.

FIG. 4 is a simplified cross-sectional view showing a part of the manufacturing process of the normal surface channel type MOSFET of FIG.

FIG. 5 is a flowchart showing a manufacturing process of a normal surface channel type MOSFET according to a third embodiment of the present invention.

FIG. 6 is a simplified cross-sectional view showing a part of the manufacturing process of the normal surface channel type MOSFET of FIG.

FIG. 7 is a flowchart showing a manufacturing process of a normal surface channel type MOSFET according to a fourth embodiment of the present invention.

FIG. 8 is a simplified cross-sectional view showing a part of the manufacturing process of the normal surface channel type MOSFET of FIG. 7;

FIG. 9 is a flowchart showing a process of manufacturing a normal surface channel type MOSFET according to a fifth embodiment of the present invention.

FIG. 10 is a simplified cross-sectional view showing a part of the manufacturing process of the normal surface channel MOSFET of FIG. 9;

FIG. 11 is a flowchart showing a process of manufacturing a normal surface channel type MOSFET according to a sixth embodiment of the present invention.

FIG. 12 shows a normal surface channel type MOSFET shown in FIG.
FIG. 7 is a simplified sectional view showing a part of the manufacturing process.

FIG. 13 is a flowchart showing a process of manufacturing a normal surface channel type MOSFET according to a seventh embodiment of the present invention.

FIG. 14 shows a normal surface channel type MOSFET shown in FIG.
FIG. 7 is a simplified sectional view showing a part of the manufacturing process.

FIG. 15 is a flowchart showing a manufacturing process of a normal surface channel type MOSFET according to an eighth embodiment of the present invention.

FIG. 16 shows a normal surface channel type MOSFET shown in FIG.
FIG. 7 is a simplified sectional view showing a part of the manufacturing process.

FIG. 17 is a flowchart showing a process of manufacturing a normal surface channel type MOSFET according to a ninth embodiment of the present invention.

FIG. 18 shows a normal surface channel type MOSFET shown in FIG.
FIG. 7 is a simplified sectional view showing a part of the manufacturing process.

FIG. 19 is a flowchart showing a process of manufacturing a normal surface channel type MOSFET according to the tenth embodiment of the present invention.

FIG. 20 shows a normal surface channel type MOSFET shown in FIG.
FIG. 7 is a simplified sectional view showing a part of the manufacturing process.

FIG. 21 is a flowchart showing a process of manufacturing a normal surface channel type MOSFET according to an eleventh embodiment of the present invention.

FIG. 22 shows a normal surface channel type MOSFET shown in FIG. 21;
FIG. 7 is a simplified sectional view showing a part of the manufacturing process.

FIG. 23 is a flowchart showing a process of manufacturing a normal surface channel MOSFET according to a twelfth embodiment of the present invention.

FIG. 24 shows a normal surface channel type MOSFET shown in FIG. 23;
FIG. 7 is a simplified sectional view showing a part of the manufacturing process.

FIG. 25 is a flowchart showing a manufacturing process of a conventional surface channel type MOSFET.

FIG. 26 shows the conventional surface channel type MOSFET shown in FIG.
FIG. 7 is a simplified sectional view showing a part of the manufacturing process.

FIG. 27 shows a conventional surface channel type MOSF having an LDD structure.
4 is a flowchart showing a manufacturing process of ET.

FIG. 28 is a simplified cross-sectional view showing a part of the manufacturing process of the conventional surface channel MOSFET having the LDD structure in FIG. 27;

FIG. 29 is a graph schematically showing a relationship between a gate length and a threshold voltage when a short channel effect and an inverse short channel effect appear.

FIG. 30 is a sectional view showing a schematic configuration of a normal surface channel type N-MOSFET.

FIG. 31 shows a surface channel type N-MOSFE having an LDD structure.
It is sectional drawing which shows the schematic structure of T.

FIG. 32 shows a normal surface channel type N-MOSF shown in FIG. 30;
4 is a graph schematically showing an impurity concentration distribution in a cross section taken along line AA of ET.

FIG. 33 shows a surface channel type NM having the LDD structure of FIG. 31;
4 is a graph schematically illustrating an impurity concentration distribution in a cross section taken along line BB of an OSFET.

[Explanation of symbols]

10 silicon substrate, 12 gate insulating film, 14
... gate electrode, 16 ... insulating film, 18 ... source region,
20 ... drain region, 22 ... channel region, 24,
26 semiconductor film, 28 thermal oxide film, 30 nitride film, 32 thermal oxide film, 34 insulating film, 36, 38
... LDD region, 40 ... sidewall spacer, 42
... insulating film, 44, 46, 48, 50 ... semiconductor film, 5
2, 54 ... thermal oxide film, 56 ... nitride film, 58 ... thermal oxide film, 60 ... nitride film, 62 ... thermal oxide film, 64 ... semiconductor film, 66 ... thermal oxide film, 68 ... ... semiconductor film, 70 ...
... thermal oxide film, 72 ... insulating film, S1 ... insulating film forming step, S2 ... first conductivity type impurity implantation step, S3 ... insulating film removing step, S4 ... gate insulating film forming step, S5 ...
Gate electrode forming step, S6... Insulating film removing step on S / D formation planned region, S6a... LDD formation planned region and S
/ D: an insulating film removing step on the region to be formed, S7 ... an insulating film forming step containing an impurity of the second conductivity type, S8, S8a,
S8b, S8c, S8d, S8e: heat treatment for impurity diffusion (formation of S / D region), S9, S9a, S9b, S
9c, S9d, S9e, S9f, S9g, S9h, S9
i, S9j, S9k ... wiring process, S10, S10a ...
... Semiconductor film forming step containing second conductivity type impurity, S1
1, S11a, S11b, S11c... Semiconductor film forming step, S12, S12a.
13c, S13d, S13e: thermal diffusion (S / D region formation) step in an atmosphere containing impurities of the second conductivity type;
14 Step of forming a nitride film around the gate electrode, S14a
... Step of forming nitride film around gate electrode and sidewall spacer, S15, S15a, S15b, S15
c, S15d, S15e... LDD region forming step, S1
6, S16a, S16b, S16c, S16d, S16
e: sidewall spacer forming step, S21: insulating film forming step, S22: first conductivity type impurity implanting step,
S23: an insulating film removing step; S24: a gate insulating film forming step; S25, S25a: a gate electrode forming step;
26, S26a ... second conductivity type impurity implantation (S / D region formation) step, S27, S27a ... impurity activation heat treatment step, S28, S28a ... wiring step, S29 ... second conductivity type impurity implantation ( S / D region formation) step, S30 ...
... Sidewall spacer forming step.

Claims (11)

[Claims] A step of forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film; and a medium for diffusion of a second conductivity type impurity over the entire surface of the substrate on which the gate electrode is formed. Forming a film; diffusing a second conductivity type impurity from the film serving as a medium for diffusion of the second conductivity type impurity into the surface of the semiconductor substrate using the gate electrode as a mask; Forming a semiconductor device selectively. 2. A step of forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film, and performing a heat treatment in an oxidizing atmosphere containing impurities of a second conductivity type to form a surface of the semiconductor substrate. Diffusing a second conductivity type impurity into the surface of the semiconductor substrate using the gate electrode as a mask while thermally oxidizing the semiconductor substrate, and selectively forming two impurity regions on the surface of the semiconductor substrate. A method for manufacturing a semiconductor device. A step of forming a gate electrode on a semiconductor substrate of the first conductivity type via a gate insulating film; a step of depositing a semiconductor film over the entire surface of the substrate on which the gate electrode is formed; Heat treatment in an atmosphere containing type impurities to diffuse second conductivity type impurities through the semiconductor film to the surface of the semiconductor substrate using the gate electrode as a mask, and select two impurity regions on the surface of the semiconductor substrate. Forming a semiconductor device. 4. The method for manufacturing a semiconductor device according to claim 2, wherein after the step of forming the gate electrode on the semiconductor substrate via the gate insulating film, the periphery of the gate electrode is resistant to oxidation. A method for manufacturing a semiconductor device, comprising a step of covering with a conductive film. 5. The method of manufacturing a semiconductor device according to claim 1, wherein after the step of selectively forming the two impurity regions on the surface of the semiconductor substrate, a sidewall is provided on a side surface of the gate electrode. A step of forming a spacer; a step of forming a film serving as a medium for diffusion of a second conductivity type impurity on the entire surface of the substrate on which the gate electrode and the sidewall spacer are formed; A second conductivity type impurity is diffused from the film to be formed into the surface of the semiconductor substrate using the gate electrode and the sidewall spacer as a mask, and two impurity regions having a higher concentration than the two impurity regions are selectively formed on the surface of the semiconductor substrate. A method of manufacturing a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 1, wherein after the step of selectively forming the two impurity regions on the surface of the semiconductor substrate, a sidewall is formed on a side surface of the gate electrode. Forming a spacer, and performing a heat treatment in an oxidizing atmosphere containing a second conductivity type impurity to thermally oxidize the surface of the semiconductor substrate and to form a mask on the surface of the semiconductor substrate using the gate electrode and the sidewall spacer as a mask. Diffusing a second conductivity type impurity to selectively form two impurity regions having a higher concentration than the two impurity regions on the surface of the semiconductor substrate. 7. The method for manufacturing a semiconductor device according to claim 1, wherein after the step of selectively forming the two impurity regions on the surface of the semiconductor substrate, a sidewall is provided on a side surface of the gate electrode. A step of forming a spacer; a step of depositing a semiconductor film on the entire surface of the substrate on which the gate electrode and the sidewall spacer are formed; and a heat treatment in an atmosphere containing a second conductivity type impurity to form the gate electrode and the gate electrode. Using the sidewall spacer as a mask, the second conductivity type impurity is diffused through the semiconductor film to the surface of the semiconductor substrate, and
Selectively forming two impurity regions having a higher concentration than one impurity region. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a film serving as a medium for diffusion of the second conductivity type impurity includes forming an insulating film containing the second conductivity type impurity. A method for manufacturing a semiconductor device, comprising a step of depositing. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a film serving as a medium for diffusion of the second conductivity type impurity includes: forming a semiconductor film containing the second conductivity type impurity. A method for manufacturing a semiconductor device, comprising a step of depositing. 10. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a film serving as a medium for diffusion of the second conductivity type impurity comprises: depositing a semiconductor film; A method for manufacturing a semiconductor device, comprising a step of adding a second conductivity type impurity. 11. The method for manufacturing a semiconductor device according to claim 6, wherein after the step of forming the sidewall spacer on the side surface of the gate electrode, the periphery of the gate electrode and the sidewall spacer is resistant to oxidation. A method for manufacturing a semiconductor device, comprising a step of covering with a film.