JPH1055677A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable performing write operation during a read-out period by comprising a semiconductor memory with a discriminating circuit, a switch circuit, and a two input AND gate in addition to a conventional circuit. SOLUTION: A discriminating circuit 15 receives two output SAO, SAOB taking a complementary level of a sense amplifier and discriminates whether read-out data is decided or not. When the read-out data is discriminated as decided, a decided signal S15 of a high level is generated, and outputted to an input terminal of one side of a switch circuit 16 and an AND gate 17. When the circuit 16 receives the signal S15 of a high level from a circuit 15, cuts off electrical connection of bit lines BL, BLB and an input of the sense amplifier 12. That is, data of the bit lines BL, BLB cuts off input to the sense amplifier 12. An AND gate 17 performs AND operation with the signal 15 and a writing signal Wr, when both signals are a high level, a writing control signal S17 of a high level is outputted to a writing buffer 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SRAM (Static
The present invention relates to a semiconductor memory device such as a random access memory (Random Access Memory).

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a configuration example of a conventional semiconductor memory device, and FIG. 5 is a timing chart of the circuit shown in FIG. The semiconductor memory device 10 includes an SRAM cell (hereinafter, referred to as a memory cell) 11, a sense amplifier 12 for reading data from the memory cell 11, and an output buffer 13 for amplifying and outputting output data SAO from the sense amplifier 12. , And write data S as an input signal
The write buffer 14 writes the value of IN to the memory cell 11. In FIG. 4, WL indicates a word line, BL indicates a bit line, and BLB indicates an inverted bit line.

In this circuit, the sense amplifier 12 and the output buffer 13 are controlled by a read control signal (hereinafter referred to as read signal) rd, and the write buffer is controlled by a write control signal (hereinafter referred to as write signal). wr. As shown in FIG. 5, the read and write operations are performed during a period when the level of the word line WL is at a high level, and the read signal rd and the write signal wr are applied to the word line W.
L is set to the active high level during the high level period. Then, the two outputs SA of the sense amplifier 12
The values of O and SAOB are determined only during the read operation by the read signal rd, and are precharged to the high level during the other periods.

In such a configuration, at the time of a read operation, the word line WL is set to a high level, whereby the access transistors 11a and 11a of the memory cell 11 are set.
1b becomes conductive and the two storage nodes N11a and N11
b is transmitted to the bit lines BL and BLB.
The read data value transmitted to the bit lines BL and BLB is input to the sense amplifier 12, the level difference is amplified, and output from the output SAO to the output buffer 13. Then, the signal is amplified by the output buffer 13 and the output signal S
Output as OUT.

In a write operation, when a write signal wr is input to the write buffer 14, the input write data S
IN is amplified by the write buffer 14 and bit lines BL,
Transmitted to BLB. Since the word line WL is set to the high level during the write operation, the values of the bit lines BL and BLB are changed to the access transistors 11a and 11b.
The signal is transmitted to the storage nodes N11a and N11b via the node b, and the storage value of the memory cell 11 changes.

[0006]

However, in the conventional circuit described above, since the read signal rd and the write signal wr are supplied independently, the write operation to the memory cell 11 during the read period is performed. , The sense amplifier 12 is affected, and the value of the read data may change.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device capable of executing a write operation during a read operation.

[0008]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises: a memory cell for outputting storage data to a bit line and storing data transmitted to the bit line; A sense amplifier for receiving and confirming the read data output to the bit line;
An output circuit for outputting the read data detected by the sense amplifier; receiving the read data detected by the sense amplifier; determining whether or not the read data has been determined; A determination circuit that outputs
A write circuit that receives the determination signal and transmits write data to the bit line; and a switch circuit that receives the determination signal and shuts off input of data of the bit line to the sense amplifier.

According to the semiconductor memory device of the present invention, during a read operation, data stored in a memory cell is output to a bit line and input to a sense amplifier. In the sense amplifier, read data of a bit line is detected and output to an output circuit and a determination circuit. Then, read data is output from the output circuit. The determination circuit determines whether or not the read data is determined from the output of the sense amplifier, and if determined to be determined, generates a determination signal,
Output to the write circuit and switch circuit. The write circuit that has received the determination signal transmits write data to the bit line. At this time, the input of the data on the bit line to the sense amplifier is cut off by the switch circuit that has received the determination signal.
Then, in this state, the value of the bit line is transmitted to the storage node of the memory cell, and data is written.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device according to the present invention. The same components as those in FIG. Represents. FIG. 2 is a timing chart of FIG.

As shown in FIG. 1, the semiconductor memory device 10a includes a memory cell 11, a sense amplifier 12, an output buffer 13, a write buffer 14, a determination circuit 15, a switch circuit 16, and a two-input AND gate 17. Have been. WL is a word line, BL is a bit line, B
LB is an inverted bit line, SOUT is an output signal (data), S
IN indicates write data (input signal), rd indicates a read signal, and wr indicates a write signal.

A determination circuit 15 receives two outputs SAO and SAOB of complementary levels of the sense amplifier 12, determines whether or not the read data is determined, and determines that the read data is determined. Is a high-level decision signal S
15 to generate the switch circuit 16 and the AND gate 1
7 to one input terminal.

When the switch circuit 16 receives the determination signal S15 from the determination circuit 15 at a high level, the bit line B
The electrical connection between L and BLB and the input of the sense amplifier 12 is cut off. That is. The input of the data of the bit lines BL and BLB to the sense amplifier 12 is cut off.

The AND gate 17 takes the logical product of the decision signal S15 and the write signal wr, and outputs a high-level write control signal S17 to the write buffer 1 when both signals are at a high level.
4 is output.

In this circuit, sense amplifier 12 and output buffer 13 are controlled by read signal rd, and write buffer 14 is controlled by write control signal S17.
As shown in FIG. 2, the read and write operations are performed during the period when the level of the word line WL is high, and the read signal rd and the write signal wr are active during the period when the word line WL is high. Set to high level.
In the present embodiment, as shown in FIG. 2, the read signal rd and the write signal wr are simultaneously set to the active high level. The values of the two outputs SAO and SAOB of the sense amplifier 12 are determined only during the read operation by the read signal rd, and are precharged to the high level during the other periods.

Next, the operation of the above configuration will be described with reference to FIG. During a read operation, the access transistors 11a and 11b of the memory cell 11 are turned on by setting the word line WL to a high level,
Data stored in two storage nodes N11a and N11b are transmitted to bit lines BL and BLB. The read data value transmitted to the bit lines BL and BLB is input to the sense amplifier 12, the level difference is amplified, one output SAO is output to the output buffer 13, and two outputs having complementary levels are taken. SAO and SAOB are output to the determination circuit 15. The read data is amplified by the output buffer 13 and output as an output signal SOUT.

In the determination circuit 15, the sense amplifier 12
It is determined from the outputs SAO and SAOB whether or not the read data has been determined. When it is determined that the read data has been determined, a high-level determination signal S15 is generated and output to the AND gate 17 and the switch circuit 16.

In the AND gate 17, the logical product of the decision signal S15 and the write signal wr is obtained, and when both signals are at the high level, the write control signal S17 at the high level is output to the write buffer 14. Further, when the switch circuit 16 receives the determination signal S15 from the determination circuit 15 at a high level, the electrical connection between the bit lines BL and BLB and the input of the sense amplifier 12 is cut off.

Write data SIN is transmitted to bit lines BL and BLB by write buffer 14 receiving write control signal S17. At this time, since the input of the data of the bit lines BL and BLB to the sense amplifier 12 is cut off by the switch circuit 16 which has received the determination signal S15 as described above, the writing to the memory cell 11 is performed during the reading period. However, without affecting the sense amplifier 12,
There is no possibility that the value of the read data changes.
Since the word line WL is set to the high level in this state, the values of the bit lines BL and BLB are set to the storage nodes N11a and N11a via the access transistors 11a and 11b.
N11b, and the stored value of the memory cell 11 changes. That is, data is written to the memory cell 11.

As described above, according to the first embodiment, two outputs SAO and SAOB having complementary levels of the sense amplifier 12 are received, and it is determined whether or not the read data is determined. If it is determined that the read data has been determined, a determination circuit 15 that generates a high-level determination signal S15 and outputs it to one of the input terminals of the switch circuit 16 and the AND gate 17; At the high level, the bit lines BL, BLB
A switch circuit 16 for interrupting the electrical connection between the signal and the input of the sense amplifier 12, and a logical product of the decision signal S15 and the write signal wr. Is provided to the write buffer 14 so that the write operation can be performed during the period of reading. As a result, a longer writing period can be obtained in combination with the writing signal.

Second Embodiment FIG. 3 is a block diagram showing a semiconductor memory device according to a second embodiment of the present invention. The difference between the second embodiment and the first embodiment is that the decision circuit 15 calculates the logical product of the decision signal S15 and the write signal wr, and the result is written by the write control signal S17. Instead of operating the write buffer 14, the determination signal S15 is directly sent to the write buffer 1
4 is input. Other configurations are the same as those of the first embodiment.

According to the second embodiment, the first
In addition to the effects of the embodiment, there is an advantage that the data content of the memory cell 11 can be updated without inputting a write signal.

[0023]

As described above, according to the present invention,
A writing operation can be performed during a period in which reading is performed. As a result, a longer writing period can be obtained in combination with the writing signal. Further, there is an advantage that the data content of the memory cell can be updated without inputting a write signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG.

FIG. 3 is a block diagram showing a second embodiment of the semiconductor memory device according to the present invention.

FIG. 4 is a block diagram illustrating a configuration example of a conventional semiconductor memory device.

FIG. 5 is a timing chart for explaining the operation of FIG. 4;

[Explanation of symbols]

10a, 10b ... semiconductor memory device, 11 ... memory cell,
12: sense amplifier, 13: output buffer, 14: writing circuit, 15: discriminating circuit, 16: switch circuit, 17: AND gate.

Claims (3)

[Claims] 1. A memory cell for outputting storage data to a bit line and storing data transmitted to the bit line, and a sense amplifier receiving a read signal and detecting and fixing the read data output to the bit line. An output circuit for outputting read data detected by the sense amplifier; receiving the read data detected by the sense amplifier; determining whether the read data is determined; and determining that the read data is determined. A determination circuit that outputs a determination signal; a write circuit that receives the determination signal and transmits write data to the bit line; and receives the determination signal and inputs data of the bit line to the sense amplifier. And a switch circuit for shutting off the current. 2. The memory cell has two storage nodes having complementary levels, and these storage nodes are paired via an access transistor whose conduction state is controlled by a word line voltage. The sense amplifier obtains two outputs obtained by amplifying a level difference between two bit lines, and the determination circuit determines whether or not read data is determined from the two outputs of the sense amplifier. 2. The semiconductor memory device according to 1. 3. The semiconductor memory device according to claim 1, wherein said write circuit transmits write data to said bit line when a write signal is input in addition to a decision signal.