JPH10326006A - Method for forming pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend the depth of focus of an isolated pattern, to form a fine pattern well and to easily form a mask by providing second exposing process by which only the latent image of an auxiliary pattern among the latent images of a design pattern and the auxiliary patten transferred on a resist by exposure is exposed. SOLUTION: A main pattern (design pattern) 52 and the auxiliary patterns 53 on the right and left of the pattern 52 are respectively formed on the mask 51 as an exposing film. In first exposing process, light from an exposing device passes through the patterns 52 and 53 on the mask 51 and exposes the resist, then the latent images of the patterns 52 and 53 are respectively transferred and formed in the resist. In the second exposing process, second exposure is performed on the resist 62 through the reversal auxiliary pattern of the mask 51 by using the exposing device. Only the latent image of the pattern 52 remains in the resist by the second exposure, so that the latent image of the pattern 53 is perfectly erased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pattern forming method, and more particularly, to a pattern forming method capable of improving the depth of focus.

[0002]

2. Description of the Related Art In a semiconductor lithography process, when a pattern on a mask is transferred to a resist on a wafer by using an exposure apparatus, as shown in FIG. Of the exposure apparatus, or oblique incidence illumination such as annular illumination or quadrupole illumination in which only one of the 0th-order light and ± 1st-order light is incident on the projection optical system. The law is known. Is defined by the ratio of the numerical aperture of the illumination optical system to the numerical aperture of the projection optical system, and is an important parameter that affects the imaging performance. In the annular illumination and the quadrupole illumination, the secondary light source has a special shape different from a conventional circular shape. However, even if the σ (coherence factor) of the exposure apparatus is increased or the oblique incidence illumination method is used, the depth of focus does not increase for a sparse pattern (isolated line pattern) that is not a dense repetitive pattern.

[0003] Here, Table 1 shows that a KrF excimer laser stepper (wavelength: 248 nm) is used to form a resist pattern for a 0.20 μm L / S (line width and line width) pattern and an isolated line pattern. This shows the depth of focus when the camera is turned on. The pattern is formed by setting the secondary light source of the exposure apparatus to a flat light intensity distribution, and setting the σ of the exposure apparatus to
The experiment was performed for the case where the values were changed to 0.55 and 0.88 and for the case where the quadrupole illumination method was used.

[Table 1] As shown in Table 1, the depth of focus of the L / S pattern is enlarged by increasing the σ of the exposure apparatus or by using a quadrupole illumination method. However, the depth of focus of the isolated line pattern at the time of exposure is not enlarged by the above method, and is smaller than the focal depth of the L / S pattern.

On the other hand, as a method of expanding the depth of focus of a sparse pattern, as shown in FIG. 21, a plurality of auxiliary patterns 33 are arranged near a main pattern 32 which is an isolated design pattern on a mask 31. A method of forming a pseudo repetitive pattern is known. By forming the pseudo repeating pattern, the depth of focus of the isolated main pattern can be expanded by applying the above-described method of expanding the depth of focus of the repeating pattern. Here, FIG. 22 shows that the line width w1 of the main pattern 32 is
The result of the light intensity calculation showing the relationship between the depth of focus of the main pattern 32 and the line width w2 of the auxiliary pattern 33 when the distance between the main pattern 32 and the auxiliary pattern 33 is 0.20 μm is 0.20 μm. . The line width is a value converted on the wafer. FIG. 22 shows that the depth of focus of the main pattern when the auxiliary pattern is arranged increases as the auxiliary pattern line width w2 approaches the main pattern line width w1.

[0005]

However, if the line width w2 of the auxiliary pattern 33 is large, the auxiliary pattern 33 is resolved after development to become a resist residue, which is a defect of the semiconductor device. For this reason, conventionally, the auxiliary pattern 3
In this case, the line width w2 of No. 3 is considerably reduced to ensure that the auxiliary pattern 33 is not resolved after development. In this case, as can be seen from FIG. 22, there is a disadvantage that the effect of expanding the depth of focus of the main pattern 32 is insufficient. Further, if the line width w2 of the auxiliary pattern 33 is too small, defect inspection and defect correction may not be performed or line width accuracy may not be guaranteed during mask pattern creation. Further, the line width w2 of the auxiliary pattern 33 is made equal to the line width w1 of the main pattern 32, and the auxiliary pattern 33 is made translucent so that the auxiliary pattern 33 is not resolved so that a mask can be created. Methods are known. However, according to the above method,
The transmittance and phase of the auxiliary pattern 33 must be controlled, which has the disadvantage that the mask forming process is complicated.

The present invention has been made in view of such a situation, and provides a pattern forming method that can greatly increase the depth of focus of an isolated pattern, can form a fine pattern satisfactorily, and can easily form a mask. The purpose is to provide.

[0007]

According to the present invention, there is provided a pattern forming method comprising: a mask forming step of forming a mask having an auxiliary pattern formed in the vicinity of a design pattern; and a mask forming step for forming the mask on a resist-coated substrate. A first exposure step for exposing the designed pattern and the auxiliary pattern, and a second exposure for exposing only the latent image of the auxiliary pattern among the latent images of the design pattern and the auxiliary pattern transferred onto the resist by the exposure. Having a process.

Further, the pattern forming method of the present invention includes a first mask forming step of forming a first mask in which an auxiliary pattern adjusted to a predetermined line width is formed in the vicinity of a design pattern; A second mask forming step of forming a second mask in which a reverse auxiliary pattern in which light and darkness is inverted with respect to the auxiliary pattern formed in the mask is formed at a position corresponding to the auxiliary pattern, and resist coating for coating a resist on the substrate A first exposing step of exposing a design pattern and an auxiliary pattern formed on the first mask on the substrate coated with the resist, and a second exposing step exposing the second mask on the exposed resist. And a second exposure step of exposing the inversion assisting pattern.

In the pattern forming method of the present invention, a latent image of a design pattern and an auxiliary pattern is formed on a resist in the first exposure step. Next, in the second exposure step, only the latent image of the auxiliary pattern is reliably erased. Therefore, if the line width of the auxiliary pattern is adjusted and formed on the first mask within a range where the focal depth of the design pattern at the time of exposure can be appropriately enlarged, the focal depth of the design pattern at the time of exposure can be increased. Thus, a fine pattern can be favorably formed.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. First Embodiment First, a mask used for a first exposure step of the pattern forming method according to the present embodiment is created. 1A and 1B are explanatory views showing an example of a mask used in a first exposure step of a pattern forming method according to the present embodiment, wherein FIG. 1A is a plan view, and FIG. 1B is a plan view of FIG. FIG. 3 is a sectional view taken along line A. As shown in FIG. 1, on a mask 51, a main pattern 52 (design pattern) as a light shielding film and auxiliary patterns 53 on the left and right sides thereof are formed. For example, a glass substrate is used for the mask 51, and Cr is used for the material of the main pattern 52 and the auxiliary pattern 53, for example. The line width w1 of the main pattern 52 is, for example, 1.
The line width w2 of the auxiliary pattern 53 is 0.625 μm.
And the distance s between the main pattern 52 and the auxiliary pattern 53 is
1.0 μm.

Next, a mask used in the second exposure step of the pattern forming method according to the present embodiment is formed. FIG.
FIGS. 3A and 3B are explanatory views showing an example of a mask used in a second exposure step of the pattern forming method according to the embodiment; FIG.
Is a plan view, and (b) is a cross-sectional view taken along line AA of (a). As shown in FIG. 2, on a mask 82 having the same shape as the above-described mask 51, an inversion auxiliary pattern 81 that transmits light whose brightness has been inverted is formed corresponding to the formation position of the auxiliary pattern 53. The line width of the inversion auxiliary pattern 81 is
The same as the above auxiliary pattern 53 is used.

Next, a resist is applied on the base substrate 62. As shown in FIG. 3, a positive-type chemically amplified resist 63 having, for example, PHS + photoacid generator as a main component is formed on a base substrate 62 on a silicon wafer 61 so as to have a thickness of, for example, 0.6 μm. Apply. The application of the resist 63 can be performed using, for example, a spin coater.
The positive-type chemically amplified resist 63 is a photosensitive material having a property of being decomposed by light irradiation, becoming soluble in a developer, and being removed from the substrate surface during development.

Next, a first exposure step is performed to expose the resist 63 described above. Exposure wavelength is 248nm
Reduction ratio of 1/5 using KrF excimer laser as light source
Is used. The numerical aperture NA of the exposure apparatus is set to 0.55, and σ is set to 0.8. When light from the exposure apparatus is passed through the main pattern 52 and the auxiliary pattern 53 of the mask 51 shown in FIG. 1 and is exposed on the resist 62, as shown in FIG.
Inside, the latent image 72 of the main pattern 52 and the latent image 73 of the auxiliary pattern 53 are transferred and formed.

Next, a second exposure process is performed to perform a second exposure on the resist 63. Using the exposure apparatus described above, the inversion assisting pattern 8 of the mask 82 shown in FIG.
1 to expose the resist 62. The first mentioned above
Exposure is performed under the same conditions as the exposure in the exposure step. In the second exposure, the exposure amount is increased until the auxiliary pattern 53 exposed in the first exposure is not resolved after development. As a result, as shown in FIG.
2 remains, and the latent image 7 of the auxiliary pattern 53 remains.
2 is completely erased.

Thereafter, when the resist 63 is baked using a baking device and developed using a developing device, a main pattern 101 made of a resist having a line width of 0.20 μm is formed as shown in FIG.

As described above, when the line width w2 of the auxiliary pattern 53 is set to 0.625 μm (0.125 μm on a wafer) and the main pattern 101 is formed by the pattern forming method according to the present embodiment, The depth of focus at the time of exposure was about 1.2 μm. On the other hand, the conventional depth of focus at the time of exposure when no auxiliary pattern is used is about 0.6.
If the line width of the auxiliary pattern is set to 0.5 μm (0.10 μm on a wafer) to ensure that the auxiliary pattern is not resolved, the depth of focus is only about 1.1 μm. I can't get it. Therefore, according to the pattern forming method of the present embodiment, for example, when the line width w2 of the auxiliary pattern 53 is 0.625 μm (0.125 μm in terms of on a wafer) as described above, the depth of focus at the time of exposure is 1.2. The depth of focus can be greatly increased to about μm.

As described above, according to the pattern forming method according to the present embodiment, the line width w2 of the auxiliary pattern 53 is formed in the vicinity of the main pattern 52 of the mask 51 so as to be larger than that of the related art. The depth of focus of the main pattern 52 at the time of exposure can be greatly increased. Further, since the auxiliary pattern 53 can be surely erased by the second exposure step, generation of a resist residue due to enlargement of the line width w2 of the auxiliary pattern 53 can be prevented. As a result, a fine pattern can be favorably formed.

According to the pattern forming method of this embodiment, the line width w2 of the auxiliary pattern 53 is
Since it can be increased to 0.625 μm, the creation of the auxiliary pattern 53 on the mask 51 becomes easier than in the case of the conventional fine auxiliary pattern. Furthermore, in the pattern forming method according to the present embodiment, since the second exposure is performed and the exposure amount is increased so that the auxiliary pattern 53 is not resolved after development, the pattern transfer defect after etching due to the resist residue is increased. Can be more reliably prevented. In the present embodiment, in the second exposure, the exposure amount is increased until the auxiliary pattern 53 exposed in the first exposure is not resolved after development. However, in the second exposure, the auxiliary pattern 53 is exposed in the etching step. Even if the process is performed until the size is not transferred to the base substrate 62, an undesirable pattern can be prevented from being formed after the etching.

Second Embodiment FIG. 7 shows the depth of focus of the main pattern 52 and the resolution line width of the auxiliary pattern 53 when the main pattern 52 is formed by the pattern forming method according to the above-described embodiment . It is a graph obtained from light intensity calculation by changing the line width w2 of the pattern 53. Note that the line width w1 of the main pattern 52 was the target line width 0.20 μm, and the exposure was performed by changing the line width w2 of the auxiliary pattern 53 of the mask 51 and setting other conditions as described above. Also, the auxiliary pattern 5
The line width w2 of 3 indicates a value projected on the wafer.
As can be seen from FIG. 7, as the line width w2 of the auxiliary pattern 53 increases, both the resolution line width of the auxiliary pattern 53 and the focal depth of the main pattern 52 increase.

Here, in the first embodiment described above,
Line width w of auxiliary pattern 53 and inverted auxiliary pattern 81
2, the same pattern as that of the pattern forming method according to the first embodiment is formed by setting 1.0 to 1.0 μm (0.20 μm on a wafer), which is the same as the main pattern 52. As can be seen from FIG. 7, when the line width w2 of the auxiliary pattern 53 and the inverted auxiliary pattern 81 is 1.0 μm (0.20 μm in terms of on-wafer), the depth of focus is about 1.7 μm. As described above, the depth of focus without using the conventional auxiliary pattern is approximately
If only 0.6 μm is obtained and the line width of the auxiliary pattern is 0.5 μm (0.10 μm on a wafer) to ensure that the auxiliary pattern is not resolved, the depth of focus is about 1.
Only 1 μm can be obtained. However, in the present embodiment, when the line width w2 of the auxiliary pattern 53 and the inversion auxiliary pattern 81 is increased to the same width as the line width w1 of the main pattern 52, the focal depth of the main pattern can be greatly increased. The main pattern (design pattern) 52 and the auxiliary pattern 5
By setting 3 to the same line width, the lithography margin can be significantly increased. Therefore, the auxiliary pattern 53 is designed based on the line width at which the mask inspection can be performed.
If the auxiliary pattern 53 is formed by adjusting the line width up to the same line width as 1, an appropriate depth of focus can be obtained, and the mask 51 can be easily formed. Defect correction becomes easy.

Third Embodiment FIG. 8 is an explanatory view showing another example of the mask used in the first exposure step of the pattern forming method according to the present embodiment.
(A) is a plan view, and (b) is a cross-sectional view taken along line AA of (a). As shown in FIG. 8, two auxiliary patterns 123 are formed on the left and right sides of the main pattern 122 on the mask 121. The main pattern 122 and the auxiliary pattern 12
The method of forming No. 3 is the same as that of the first embodiment. FIG. 9 is an explanatory view showing another example of the mask used in the second exposure step of the pattern forming method according to the present embodiment,
(A) is a plan view, and (b) is a cross-sectional view taken along line AA of (a). As shown in FIG. 9, on a mask 125 having the same shape as the above-mentioned mask 121, the brightness is inverted in accordance with the formation position of the above-mentioned auxiliary pattern 123, and an inversion auxiliary pattern 124 that transmits light is formed.

Using the masks 121 and 125 shown in FIGS. 8 and 9, pattern formation is performed in the same manner as in the pattern formation method according to the first embodiment described above. By increasing the number of the auxiliary patterns 123 used in the first exposure step, the repeatability of the pattern constituted by the main pattern 122 and the auxiliary pattern 123 is increased, and the depth of focus of the main pattern can be increased.

Further, the mask 12 used in the second exposure step
The inversion auxiliary pattern 124 of No. 5, as shown in FIG.
Instead of a pattern in which the brightness of the auxiliary pattern 123 is simply inverted, a large pattern including the above two inverted auxiliary patterns 126 may be used as shown in FIG. By making the shape of the inversion auxiliary pattern 126 as shown in FIG. 10, the amount of exposure applied to the resist increases, so that the latent image of the auxiliary pattern 123 transferred onto the resist can be efficiently erased. In addition, it is possible to prevent the occurrence of pattern transfer defects after etching due to resist residues.

Fourth Embodiment In the above-described first to third embodiments, an overlay shift actually occurs between the mask used in the first exposure step and the mask used in the second exposure step. If a resist is generated between the mask used in the first exposure step and the mask used in the second exposure step, a resist residue is generated, which causes a failure of the semiconductor device.

For this reason, the line width of the above-described reversal assist pattern is determined by taking into account the misalignment occurring between the mask used in the first exposure process and the mask used in the second exposure process. It is made wider than the line width of the auxiliary pattern by the amount of the shift. This makes it possible to surely prevent the occurrence of resist residues even when a misalignment occurs between the mask used in the first exposure step and the mask used in the second exposure step.

Fifth Embodiment Of the so-called repetitive patterns in which the main patterns are densely formed on the mask, the pattern located at the end portion has a pattern formed on one side of the pattern and a pattern formed on the other side. Since no pattern is formed, the depth of focus decreases when exposed through the pattern on the wafer,
The pattern transferred on the wafer may be deteriorated.
This is because the pattern existing at the end of the repeated pattern is a kind of isolated pattern. In order to prevent this, for example, as shown in FIG. 11, among the repetitive patterns in which the main patterns 150 are densely formed, the auxiliary patterns 15 are provided beside the edge patterns 152 located at the ends.
Then, a mask 151 in which No. 3 is arranged is created. Further, a mask in which the inversion auxiliary pattern is formed at a position corresponding to the formation position of the auxiliary pattern 153 is also created at the same time. Using these masks, the first and second exposures are performed in the same manner as the above-described pattern forming method according to the present embodiment. As a result, it is possible to prevent the depth of focus of exposure through the edge pattern 152 existing at the end position of the resist repeating pattern on the wafer from being deteriorated through the mask 151 shown in FIG. Can be formed.

Sixth Embodiment Next, a case where the pattern forming method according to the present embodiment is applied to the formation of a logic gate pattern having a gate length of 0.20 μm of an ASIC device will be described with reference to FIGS. I do. First, as shown in FIG. 12, after a device isolation (not shown) is formed on a silicon substrate 161, a gate oxide film 162 is formed, a polysilicon layer 163 is formed by a CVD method, and a tungsten silicide layer 164 is formed by a CVD method. Then, an antireflection film (SiOxNy: H) 165 is formed by the CVD method, and an oxide film 166 is formed by the CVD method. After forming the oxide film 166, a positive chemically amplified resist 167 is applied on the oxide film 166 by a spin coater so as to have a thickness of 0.6 μm. Note that the antireflection film 165 has a feature of absorbing or attenuating UV light, and is formed below the resist 167 to reduce standing waves and halation generated during exposure. The steps up to here are the normal manufacturing steps of the ASIC device.

Next, as shown in FIG. 13, a mask 171 on which a logic gate pattern 172 and an auxiliary pattern 173 are formed is prepared. On the mask 171, the minimum line width of the logic gate pattern 172 which is the main pattern is
For example, the line width of the auxiliary pattern 173 is 1.0 μm.
The distance between the logic gate pattern 172 and the auxiliary pattern 173 is 1.0 μm or more. Next, a first exposure step is performed using the exposure apparatus under the same conditions as those described in the first embodiment. Exposure is shown in Fig. 1.
The mask 1 shown in FIG. 13 is formed on the resist 167 shown in FIG.
Exposure is performed at a reduction magnification of 1/5 through the 71 logic gate pattern 172 and the auxiliary pattern 173. FIG.
13 shows a cross-sectional view of the substrate taken along line AA of FIG. 13 after the completion of the first exposure step. As shown in FIG.
7, a latent image of the logic gate pattern 172 and the auxiliary pattern 182 is formed.

Next, as shown in FIG.
A mask 192 composed of an inverted auxiliary pattern 191 obtained by inverting the brightness of the first auxiliary pattern 173 is exposed under the same conditions as the exposure in the first exposure step. In the second exposure step, the exposure amount is increased within a range in which the latent image 182 of the auxiliary pattern exposed in the first exposure step is not resolved by the developing step performed after the second exposure step.

As a result, as shown in FIG. 16, only the gate pattern latent image 201 remains in the resist 167, and the auxiliary pattern latent image 182 is erased. Thereafter, when the resist is baked and developed, a resist gate pattern 211 having a line width of 0.20 μm is formed as shown in FIG. Next, using a resist gate pattern 211 made of an oxide film as a mask, for example, using a magnetron etching apparatus,
When the pattern 211 and the oxide film are anisotropically etched, the resist gate pattern 211 is completely removed, and an oxide film gate pattern made of an oxide film is formed on the antireflection film 165 as shown in FIG. .

Next, the antireflection film 165, the tungsten silicide layer 164, and the polysilicon layer 163 are anisotropically etched using, for example, an ECR (Electron Cyclotron) etching apparatus with the oxide film gate pattern 221 as a mask. As shown in FIG.
Logic gate pattern 231 made of 20 μm oxide film
Is formed satisfactorily. As described above, according to the pattern forming method of the present embodiment, the depth of focus at the time of exposure can be greatly increased, and the fine logic gate pattern 231 having a line width of 0.20 μm can be favorably formed. .

In the above embodiment, the case where the logic gate pattern 231 is formed has been described. However, the pattern forming method according to the present embodiment can be applied to the formation of a logic wiring. Further, the pattern forming method according to the present embodiment includes the above-described logic gate pattern 23.
It is also possible to form gates, wirings, and the like of a semiconductor device on which logic and memory are mounted in a similar process to the formation of 1.

Further, in the pattern forming method according to the present embodiment, the case where a normal exposure method is used has been described, but an oblique incidence illumination method such as an annular illumination and a quadrupole illumination may be used. Since the oblique illumination method is a technique for increasing the depth of focus of a repetitive pattern, the effect of the pattern forming method according to the present embodiment can be further improved.

Further, in the pattern forming method according to the present embodiment, the case where the KrF excimer laser light is used as the exposure light source has been described, but instead of the KrF excimer laser light, depending on the line width of the pattern to be formed. And g
Exposure can also be performed using a line, i-line, ArF excimer laser light, or X-ray. Further, as the exposure device, a scanner can be used instead of the stepper.

[0035]

According to the present invention, the latent image of the design pattern and the auxiliary pattern is formed in the resist in the first exposure step, and only the latent image of the auxiliary pattern is erased in the second exposure step. Therefore, the depth of focus of the design pattern at the time of exposure can be expanded by the action of the auxiliary pattern, and the auxiliary pattern having a larger line width than the conventional one can be arranged near the design pattern. As a result, when the design pattern is a sparse pattern, the depth of focus can be greatly increased, and a fine pattern can be satisfactorily formed. Further, the production yield of the semiconductor device can be improved. According to the present invention,
Since an auxiliary pattern having a larger line width than that of the related art can be arranged near the design pattern, a mask can be easily created. Further, according to the present invention, a gate pattern of a high-performance logic semiconductor device can be favorably formed. Further, according to the present invention, it is possible to manufacture a high-performance semiconductor device in which a logic and a memory are mixed.

[Brief description of the drawings]

FIGS. 1A and 1B are explanatory views showing an example of a mask used in a first exposure step of a pattern forming method according to an embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG. FIG. 3 is a sectional view taken along line AA.

FIGS. 2A and 2B are explanatory views showing an example of a mask used in a second exposure step of the pattern forming method according to the embodiment of the present invention, wherein FIG. 2A is a plan view, and FIG. FIG. 3 is a sectional view taken along line AA.

FIG. 3 is a view for explaining a pattern forming step by a pattern forming method according to the embodiment of the present invention, and is a cross-sectional view showing a step until a positive chemically amplified resist is applied on a substrate.

FIG. 4 is a view for explaining a pattern forming step by a pattern forming method according to the embodiment of the present invention,
FIG. 9 is a cross-sectional view showing a state where latent images of a main pattern and an auxiliary pattern are formed in the resist by the exposure step of FIG.

FIG. 5 is a view for explaining a pattern forming step by the pattern forming method according to the embodiment of the present invention,
FIG. 13 is a cross-sectional view showing a state where the latent image of the auxiliary pattern has been erased by the exposure step.

FIG. 6 is a view for explaining a pattern forming step by a pattern forming method according to the embodiment of the present invention, and is an explanatory view showing a state where a main pattern is formed after baking and developing a resist.

FIG. 7 shows the depth of focus of the main pattern and the resolution line width of the auxiliary pattern when the main pattern is formed by the pattern forming method according to the embodiment of the present invention, from the light intensity calculation by changing the line width of the auxiliary pattern. It is a graph obtained.

FIG. 8 is an explanatory view showing another example of the mask used in the first exposure step of the pattern forming method according to the embodiment of the present invention, wherein (a) is a plan view and (b) is (a). A) AA
It is a line sectional view.

FIG. 9 is an explanatory view showing another example of a mask used in the second exposure step of the pattern forming method according to the embodiment of the present invention, wherein (a) is a plan view and (b) is (a). A) AA
It is a line sectional view.

FIG. 10 is an explanatory view showing still another example of the mask used in the second exposure step of the pattern forming method according to the embodiment of the present invention.

FIG. 11 is a plan view showing an example of a mask having a repetitive pattern to which a pattern forming method according to an embodiment of the present invention is applied.

FIG. 12 is a cross-sectional view for explaining a forming step of forming a gate pattern of an ASIC device by a pattern forming method according to an embodiment of the present invention, and showing a process up to a resist coating step;

FIG. 13 is a plan view illustrating an example of a mask on which a gate pattern and an auxiliary pattern are formed.

FIG. 14 is a cross-sectional view showing a state where a latent image of a gate pattern and an auxiliary pattern is formed in a resist.

FIG. 15 is a plan view showing an example of a mask on which a reversal assist pattern is formed.

FIG. 16 is a cross-sectional view showing a state where a latent image of an auxiliary pattern formed in a resist is erased.

FIG. 17 is an explanatory diagram showing a state where a resist gate pattern is formed.

FIG. 18 is a sectional view showing a state where an oxide film gate pattern is formed.

FIG. 19 is a cross-sectional view showing a state where a logic gate pattern is formed.

FIG. 20 is a plan view illustrating an example of a mask on which a repetitive pattern is formed.

FIG. 21 is a plan view showing an example of a mask in which an auxiliary pattern is formed near a main pattern.

FIG. 22 is a graph showing a relationship between a line width of an auxiliary pattern and a depth of focus.

[Explanation of symbols]

51: mask, 52: main pattern, 53: auxiliary pattern, 81: inversion auxiliary pattern, 82: mask.

Claims (7)

[Claims] A mask forming step of forming a mask in which an auxiliary pattern is formed in the vicinity of the design pattern; and a first step of exposing the design pattern and the auxiliary pattern formed in the mask on a substrate coated with a resist. A pattern forming method comprising: an exposing step; and a second exposing step of exposing only the latent image of the auxiliary pattern among the latent images of the design pattern and the auxiliary pattern transferred onto the resist by the exposure. 2. The pattern forming method according to claim 1, wherein a plurality of auxiliary patterns are formed in the vicinity of the design pattern formed on the mask. 3. A first mask forming step of forming a first mask in which an auxiliary pattern adjusted to a predetermined line width is formed in the vicinity of a design pattern, and a step of forming a first mask on the auxiliary pattern formed on the first mask. A second mask forming step of forming a second mask in which the auxiliary pattern and the inversion auxiliary pattern whose brightness is inverted at a corresponding position are formed; a resist coating step of coating a resist on a substrate; A first exposing step of exposing a designed pattern and an auxiliary pattern formed on the first mask on the exposed substrate, and a second exposing step of exposing an inverted auxiliary pattern formed on the second mask on the exposed resist Pattern forming method having an exposing step. 4. The second exposing step includes exposing the inversion auxiliary pattern so that the auxiliary pattern exposed in the first exposing step is not resolved in a developing step performed after the second exposing step. The pattern forming method according to claim 3. 5. The pattern according to claim 3, wherein in the first mask forming step, the auxiliary pattern is formed by adjusting the auxiliary pattern in a range from a line width capable of mask inspection to the same line width as a design pattern. Formation 6. The inversion assist pattern is formed such that the line width of the inversion assist pattern is larger than the line width of the assist pattern by the amount of misalignment between the first mask and the second mask.
3. The method for forming a pattern according to item 1. 7. The pattern forming method according to claim 4, wherein in the second exposing step, the auxiliary pattern exposed in the first exposing step is exposed by adjusting an exposure amount so as not to be resolved after the developing step. Method.