JPH10321717A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method for manufacturing a semiconductor device which is satisfactory in flatness degree and step coverage. SOLUTION: An electrode 12 is formed on a semiconductor substrate 11, and an interlayer insulating film 13 is deposited on the semiconductor substrate 11. After the pyrogenic atmosphere is heat-treated, the nitrogen atmosphere is further heated and a contact hole 14 is formed by a wet etching and a succeeding dry etching and an electrode wiring 16 is formed in the contact hole 14. Note, a composite film having BPSG(boric acid-phosphorous silicic acid) or PSG(phosphorous silicic acid) as an upper layer is used in the interlayer insulating film 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices become more highly integrated and higher in density, (1) surface irregularities become severer. (2) The aspect ratio increases. Two major problems have arisen.

Therefore, as shown in FIGS. 6 to 10,
As an effective means of the flattening method between the gate electrode 22 and the first aluminum wiring 26, for example, a composite film having BPSG (boron-phosphosilicate glass) or PSG (phosphorus-silicate glass) as an upper layer is used. After depositing an interlayer insulating film 23 on the silicon substrate 21 by a CVD apparatus, an interlayer insulating film (glass) is formed.
There is a method of performing a heat treatment in a pyrogenic atmosphere or a nitrogen atmosphere in order to melt and flow 23 to obtain a flattened shape. FIG. 7 shows the shape before heat treatment, and FIG. 8 shows the shape after heat treatment. Reference numeral 22 denotes a gate electrode made of polycrystalline silicon or the like.

On the other hand, as an effective means of forming a contact hole 24 for obtaining good step coverage, the contact hole 24 with a taper 25 is formed by performing wet etching and subsequent dry etching of the interlayer insulating film 23. Is formed. In order to increase the amount of aluminum deposited on the bottom and side walls of the contact hole 24, the opening above the contact hole 24 is widened. In other words, the provision of the taper 25 allows the aluminum particles to be deposited in the contact hole 2 during the deposition of aluminum.
4, so that step coverage is improved.

FIG. 9 shows the shape after the formation of the contact hole 24, and FIG. 10 shows the shape after the aluminum is deposited.

[0006]

FIG. 11 shows the shape after heat treatment in a nitrogen atmosphere, and FIG. 12 shows the shape after heat treatment in a pyrogenic atmosphere. In general, heat treatment in a pyrogenic atmosphere provides better planarization. this is,
In a nitrogen atmosphere, the interlayer insulating film 23 is merely melted and flown at a high temperature. However, in a pyrogenic atmosphere, not only the interlayer insulating film 23 is melted, but an OH group as an oxidant enters the inside of the interlayer insulating film 23. Si in the interlayer insulating film 23
This is because the interlayer insulating film 23 flows due to the re-vitrification (SiO ₂ ) by reacting with, and the flatness is better in the pyrogenic atmosphere than in the nitrogen atmosphere.

FIG. 13 shows the shape of the contact hole 24 formed by wet etching after the heat treatment in the pyrogenic atmosphere and the subsequent dry etching after the aluminum deposition, and FIG. 14 shows the wet etching and the heat treatment after the heat treatment in the nitrogen atmosphere. The shape after the aluminum deposition of the contact hole 24 formed by the subsequent dry etching is shown. Conversely, when the heat treatment is performed in a nitrogen atmosphere, the width of the taper 25 in the lateral direction is increased. This is because boron (B) and phosphorus (P) diffuse into the nitrogen atmosphere from the surface of the interlayer insulation film 23 when the interlayer insulation film 23 formed of a composite film having BPSG or PSG as an upper layer is heat-treated in a nitrogen atmosphere. Therefore, the concentration of boron (B) and phosphorus (P) in the interlayer insulating film 23 is low on the surface side,
This is because the inside becomes higher. That is, in wet etching, the etching rate becomes higher toward the surface side where the impurity concentration is lower, and the taper 2 has a wider width in the lateral direction.
5 are formed.

On the other hand, in a pyrogenic atmosphere, O
Since the H group always reacts with Si in the interlayer insulating film 23 to form glass (SiO ₂ ), this hinders diffusion of boron (B) and phosphorus (P) into the pyrogenic atmosphere, and Since the impurity concentration on the surface side of the insulating film 23 is unlikely to decrease, the taper 25 does not spread in the lateral direction during wet etching.

When the lateral spread of the taper 25 increases, aluminum particles are deposited during the deposition of aluminum.
Since step 4 is easier to flow, step coverage is improved. From the above, the results shown in Table 1 were obtained in the conventional method for manufacturing a semiconductor device, and both the flatness and the contact shape could not be satisfactorily compatible.

[0010]

[Table 1] SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a method of manufacturing a semiconductor device having good flatness and good step coverage.

[0011]

According to a method of manufacturing a semiconductor device of the present invention, an electrode is formed on a semiconductor substrate, an interlayer insulating film is deposited on the semiconductor substrate, heat-treated in a pyrogenic atmosphere, and further heated in a nitrogen atmosphere. Heat treatment is performed, and a contact hole is formed by wet etching followed by dry etching, and an electrode wiring is formed in the contact hole.

Note that BPSG or P
A composite film having SG as an upper layer is used. According to the method of manufacturing a semiconductor device of the present invention, heat treatment is first performed in a pyrogenic atmosphere, whereby not only the interlayer insulating film is melted, but also the interlayer insulating film is burned and revitrified by the action of hydrogen and oxygen. To perform good flattening. Subsequently, by performing a heat treatment in a nitrogen atmosphere, boron (B) and phosphorus (P) are drawn from the surface of the interlayer insulating film, which is a characteristic in the nitrogen atmosphere. Phosphorus (P) has a concentration gradient from the surface toward the inside. After that, a contact hole having a taper extending in the lateral direction is formed by wet etching followed by dry etching, and an electrode wiring is formed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5 show a manufacturing process of a semiconductor device. In FIG. 1, reference numeral 11 denotes a silicon substrate. Polycrystalline silicon is deposited on the silicon substrate 11 to a thickness of 400 nm by a CVD apparatus and then patterned to form a gate electrode 12.

Next, as shown in FIG. 2, B
The interlayer insulating film 13 composed of a composite film having PSG is
It is deposited by the D apparatus. Then, as shown in FIG. 3, after depositing the interlayer insulating film 13, a heat treatment is performed in a pyrogenic atmosphere at, for example, 900 ° C. for 45 minutes, and then a heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes.

Next, as shown in FIG.
Is etched by wet etching with an HF solution or the like, followed by dry etching to form a contact hole 14. Further, as shown in FIG. 5, for example, aluminum is vapor-deposited on the entire surface with a thickness of 1 μm by PVD, and is patterned to form the first electrode wiring 16.

According to the method of manufacturing a semiconductor device of the present invention, the interlayer insulating film 13 is not only melted by heat treatment in a pyrogenic atmosphere, but also burned by the action of hydrogen and oxygen. By performing re-vitrification, flow is performed and good flattening is performed. Subsequently, by performing a heat treatment in a nitrogen atmosphere, boron (B) and phosphorus (P) in the interlayer insulating film 13 are absorbed by the surface of the interlayer insulating film 13 in the nitrogen atmosphere. ) And phosphorus (P) have a concentration gradient from the surface toward the inside. Thereafter, a contact hole 14 having a taper 15 extending in the lateral direction is formed by wet etching and subsequent dry etching, and aluminum is deposited. As a result, a semiconductor device having both good flatness and good step coverage can be manufactured.

The interlayer insulating film 13 is not limited to a composite film having BPSG in the upper layer, but may be a composite film having PSG in the upper layer.

[0018]

According to the method of manufacturing a semiconductor device of the present invention, heat treatment is first performed in a pyrogenic atmosphere to not only melt the interlayer insulating film but also to burn the interlayer insulating film by the action of hydrogen and oxygen. By performing re-vitrification, flow is performed and good flattening is performed. Subsequently, by performing a heat treatment in a nitrogen atmosphere, boron (B) and phosphorus (P) are drawn from the surface of the interlayer insulating film, which is a characteristic in the nitrogen atmosphere. Phosphorus (P) has a concentration gradient from the surface toward the inside. After that, a contact hole having a taper extending in the lateral direction is formed by wet etching followed by dry etching, and an electrode wiring is formed. As a result, a semiconductor device having both good flatness and good step coverage can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a step of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device according to one embodiment of the present invention;

FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device in one embodiment of the present invention;

FIG. 6 is a sectional view showing a manufacturing process of a semiconductor device in a conventional example.

FIG. 7 is a sectional view showing a manufacturing process of a semiconductor device in a conventional example.

FIG. 8 is a sectional view showing a manufacturing process of a semiconductor device in a conventional example.

FIG. 9 is a sectional view showing a manufacturing process of a semiconductor device in a conventional example.

FIG. 10 is a sectional view showing a manufacturing process of a semiconductor device in a conventional example.

FIG. 11 is a cross-sectional view showing a planarized shape of a conventional semiconductor device.

FIG. 12 is a cross-sectional view showing a planarized shape of a conventional semiconductor device.

FIG. 13 is a cross-sectional view showing a shape of a contact hole of a conventional semiconductor device.

FIG. 14 is a cross-sectional view illustrating a shape of a contact hole of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 11 silicon substrate (semiconductor substrate) 12 gate electrode 13 interlayer insulating film 14 contact hole 15 taper 16 electrode wiring 21 silicon substrate (semiconductor substrate) 22 gate electrode 23 interlayer insulating film 24 contact hole 25 taper 26 electrode wiring

Claims (2)

[Claims] Forming an electrode on a semiconductor substrate;
A step of depositing an interlayer insulating film on the semiconductor substrate, a step of heat-treating in a pyrogenic atmosphere and then a heat treatment in a nitrogen atmosphere, a step of forming a contact hole by wet etching and subsequent dry etching, Forming an electrode wiring. 2. The method according to claim 1, wherein the interlayer insulating film comprises a composite film having BPSG or PSG as an upper layer.