JPH10313152A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPH10313152A
JPH10313152A JP11991797A JP11991797A JPH10313152A JP H10313152 A JPH10313152 A JP H10313152A JP 11991797 A JP11991797 A JP 11991797A JP 11991797 A JP11991797 A JP 11991797A JP H10313152 A JPH10313152 A JP H10313152A
Authority
JP
Japan
Prior art keywords
thick
thickness
thin
circuit pattern
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11991797A
Other languages
Japanese (ja)
Inventor
Takashi Kobayashi
隆志 小林
Takao Kobayashi
隆雄 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP11991797A priority Critical patent/JPH10313152A/en
Publication of JPH10313152A publication Critical patent/JPH10313152A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0263High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/428Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern

Abstract

PROBLEM TO BE SOLVED: To accurately set the pattern width according to the current capacity and ensure an insulation distance in the thickness direction by making a thin- walled conductor continuous in the widthwise direction, and dividing an increasingly thick plated layer in sections in the widthwise direction. SOLUTION: A circuit board has thin-walled circuit patterns 23A, 23B for low currents and thick-walled circuit patterns 25A, 25B for high currents on both sides of an insulation board 13. The patterns 23A, 23B are composed of Cu foils 3A, 3B of specified circuit patterns with a Cu-plated layer 19. The patterns 25A, 25B have increasingly thick Cu plated layers 7A, 7B on the Cu foils 3A, 3B of thin wall conductor (3A, 19; 3B, 19) of specified circuit patterns. The broader thick-walled circuit pattern 25A has thin-wall conductors 3A, 19 continuous in the widthwise direction, while the thick walled plated layer 7A is divided in sections in the widthwise direction. This ensures required insulation distance in the thickness direction, without increasing the thickness of the board 13.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、大電流通電用の厚
肉回路パターンを有する回路基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board having a thick circuit pattern for supplying a large current.

【0002】[0002]

【従来の技術】電子回路の利用が産業機械分野および自
動車部品分野などへ急速に拡大するなかで、インバータ
ー回路や電源装置などでは、省スペースおよび省力化を
図る必要から、同一絶縁基板上に小電流用(信号用)の
薄肉回路パターンと大電流用の厚肉回路パターンを混載
した複合回路基板が広く利用されるようになってきてい
る。
2. Description of the Related Art As the use of electronic circuits is rapidly expanding to the fields of industrial machinery and automobile parts, inverter circuits and power supply devices need to be reduced in space and power, so that they can be mounted on the same insulating substrate. A composite circuit board on which a thin circuit pattern for a current (for a signal) and a thick circuit pattern for a large current are mixed has been widely used.

【0003】この種の回路基板に用いられる厚肉回路パ
ターンには種々の形態があるが、その一つとして、所定
の回路パターンに形成された薄肉導体(銅箔)の片面
に、電気メッキにより増厚用の厚メッキ層を設けたもの
が知られている。
[0003] There are various types of thick circuit patterns used for this type of circuit board. One of them is electroplating on one surface of a thin conductor (copper foil) formed in a predetermined circuit pattern. The thing provided with the thick plating layer for thickening is known.

【0004】[0004]

【発明が解決しようとする課題】しかしこの形態の厚肉
回路パターンの場合、薄肉導体上に電気メッキにより比
較的厚いメッキ層を形成しようとすると、回路パターン
の幅の両側部より中央部でメッキ厚が薄くなる傾向があ
る。この傾向は回路パターンの幅が広くなるほど顕著に
なる。このため厚肉回路パターンの幅が広い場合には、
相対的に両側部のメッキ厚が厚くなりすぎて、増厚メッ
キ層を絶縁基板に埋め込むときに、絶縁基板の厚さ方向
で必要な絶縁距離を確保することが困難になるという問
題が生じる。この問題は絶縁基板の厚さを厚くすれば回
避できるが、絶縁基板を厚くすることは、寸法および重
量の増大やコストアップをまねくので好ましくない。ま
た上述の傾向に起因して、同一基板内に幅の異なる厚肉
回路パターンが混在する場合は、各パターンの平均メッ
キ厚に差が生じてしまう。すなわち幅の狭い厚肉回路パ
ターンのメッキ厚が厚くなりすぎて、やはり上述のよう
な絶縁距離の問題が生じる。また同一基板内でメッキ厚
のバラツキが大きいと、設計の際に電流容量に応じたパ
ターン幅の設定が難しい。
However, in the case of a thick circuit pattern of this form, if a relatively thick plating layer is to be formed on a thin conductor by electroplating, the plating is performed at the center of the width of the circuit pattern rather than at both sides. The thickness tends to be thin. This tendency becomes remarkable as the width of the circuit pattern increases. Therefore, when the width of the thick circuit pattern is wide,
There is a problem that the plating thickness on both sides becomes relatively thick, and it becomes difficult to secure a required insulation distance in the thickness direction of the insulating substrate when the thickened plating layer is embedded in the insulating substrate. This problem can be avoided by increasing the thickness of the insulating substrate, but increasing the thickness of the insulating substrate is not preferable because it increases the size and weight and increases the cost. In addition, when thick circuit patterns having different widths coexist on the same substrate due to the above tendency, a difference occurs in the average plating thickness of each pattern. That is, the plating thickness of the thick circuit pattern having a small width becomes too thick, and the above-described problem of the insulation distance also occurs. If the plating thickness varies greatly within the same substrate, it is difficult to set a pattern width according to the current capacity at the time of designing.

【0005】本発明の目的は、以上のような問題点に鑑
み、薄肉導体と増厚メッキ層とで構成される厚肉回路パ
ターンを有する回路基板において、比較的幅の広い厚肉
回路パターンの増厚メッキ層の厚さのバラツキを小さく
して電流容量に応じたパターン幅の設定を正確に行える
ようにすると共に、絶縁基板の厚さを厚くすることなく
厚さ方向の絶縁距離を確保できるようにすることにあ
る。
SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a circuit board having a thick circuit pattern composed of a thin conductor and an increased plating layer. In addition to reducing the variation in the thickness of the thickened plating layer, it is possible to accurately set the pattern width according to the current capacity, and to secure the insulation distance in the thickness direction without increasing the thickness of the insulating substrate. Is to do so.

【0006】[0006]

【課題を解決するための手段】この目的を達成するため
本発明は、絶縁基板と大電流用の厚肉回路パターンとを
有し、前記厚肉回路パターンは、所定の回路パターンに
形成された薄肉導体の片面に増厚メッキ層を設けたもの
からなり、前記薄肉導体が幅方向に連続していて、増厚
メッキ層が幅方向に複数に分割されていることを特徴と
するものである。
In order to achieve this object, the present invention comprises an insulating substrate and a thick circuit pattern for a large current, wherein the thick circuit pattern is formed in a predetermined circuit pattern. The thin conductor is provided with a thick plating layer on one surface, and the thin conductor is continuous in the width direction, and the thick plating layer is divided into a plurality of pieces in the width direction. .

【0007】このように厚肉回路パターンの幅が広い場
合に、増厚メッキ層を幅方向に複数に分割すると、増厚
メッキ層を形成するときに厚さのバラツキを小さくする
ことが可能となり、前記課題を解決できる。
In the case where the thickness of the thick circuit pattern is wide, dividing the thick plating layer into a plurality of parts in the width direction makes it possible to reduce variations in thickness when forming the thick plating layer. The above-mentioned problem can be solved.

【0008】[0008]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

〔実施形態1〕図1は本発明の一実施形態を示す。この
回路基板は、絶縁基板13の両面に小電流用の薄肉回路
パターン23A、23Bと、大電流用の厚肉回路パター
ン25A、25Bを設けたものである。薄肉回路パター
ン23A、23Bは所定の回路パターンに形成された銅
箔3A、3Bと銅メッキ層19とで構成されている。
[Embodiment 1] FIG. 1 shows an embodiment of the present invention. This circuit board is provided with thin circuit patterns 23A and 23B for small current and thick circuit patterns 25A and 25B for large current on both surfaces of the insulating substrate 13. The thin circuit patterns 23A and 23B are composed of copper foils 3A and 3B formed in a predetermined circuit pattern and a copper plating layer 19.

【0009】厚肉回路パターン25A、25Bは所定の
回路パターンに形成された薄肉導体(3Aと19、3B
と19)の銅箔3A、3B側の面に銅の増厚メッキ層7
A、7Bを設けたものである。厚肉回路パターン25
A、25Bの薄肉導体3Aと19、3Bと19は薄肉回
路パターン23A、23Bと同様に絶縁基板13の表面
から突出しており、増厚メッキ層7A、7Bは絶縁基板
13に埋め込まれている。
The thick circuit patterns 25A, 25B are thin conductors (3A, 19, 3B) formed in a predetermined circuit pattern.
And 19) the copper thick plating layer 7 on the copper foil 3A, 3B side.
A and 7B are provided. Thick circuit pattern 25
The thin conductors 3A and 19 of A and 25B protrude from the surface of the insulating substrate 13 like the thin circuit patterns 23A and 23B, and the thickened plating layers 7A and 7B are embedded in the insulating substrate 13.

【0010】また厚肉回路パターン25A、25Bのう
ち比較的幅の広い(図1で右上の)厚肉回路パターン2
5Aは、薄肉導体3A、19が幅方向に連続しているの
に対し、増厚メッキ層7Aが幅方向に複数に(三つに)
分割された形態となっている。この点がこの回路基板の
特徴である。この例では、幅の広い厚肉回路パターン2
5Aに分割して設けられた増厚メッキ層7Aと、幅の狭
い厚肉回路パターン25Aに設けられた増厚メッキ層7
Aとが、ほぼ同じ幅になっている。
The relatively thick (upper right in FIG. 1) thick circuit pattern 2 of the thick circuit patterns 25A and 25B
5A shows that the thinned conductors 3A and 19 are continuous in the width direction, while the thickened plating layer 7A has a plurality (three) in the width direction.
It has a divided form. This is a feature of this circuit board. In this example, a wide thick circuit pattern 2
5A and a thick plating layer 7A provided on a narrow thick circuit pattern 25A.
A has almost the same width.

【0011】以下、この回路基板の具体的構造を明らか
にするため、図2〜図7を参照してこの回路基板の製造
方法を説明する。まず図2に示すように、2枚の支持板
1A、1Bを用意し、各々の片面に接着剤等により1オ
ンス(公称厚さ35μm)の汎用銅箔3A、3Bを張り
付ける。支持板1A、1Bの材質はステンレス板、アル
ミニウム板又はベーク板等である。
Hereinafter, a method for manufacturing the circuit board will be described with reference to FIGS. 2 to 7 in order to clarify the specific structure of the circuit board. First, as shown in FIG. 2, two support plates 1A and 1B are prepared, and 1 ounce (nominal thickness 35 μm) general-purpose copper foils 3A and 3B are attached to one surface of each of them by an adhesive or the like. The material of the support plates 1A and 1B is a stainless plate, an aluminum plate, a bake plate, or the like.

【0012】次に銅箔3A、3B上に、増厚メッキ層を
形成するため、得ようとする増厚メッキ層と逆のパター
ン(ミラーパターン)が残るようにメッキレジスト5
A、5Bを形成する。メッキレジスト5A、5Bは、銅
箔3A、3B上にドライフィルムを張り付け、厚肉回路
パターンのミラーパターンを露光、現像することにより
形成する。メッキレジスト5A、5Bの厚さは、ドライ
フィルムの積層枚数により設定することができ、後に形
成する増厚メッキ層の厚さと同じかそれより厚くなるよ
うに設定する。
Next, in order to form a thick plating layer on the copper foils 3A and 3B, a plating resist 5 is formed so that a pattern (mirror pattern) opposite to the thick plating layer to be obtained remains.
A and 5B are formed. The plating resists 5A and 5B are formed by attaching a dry film on the copper foils 3A and 3B, exposing and developing a mirror pattern of a thick circuit pattern. The thickness of the plating resists 5A and 5B can be set by the number of laminated dry films, and is set to be equal to or larger than the thickness of a thick plating layer to be formed later.

【0013】ところで、増厚メッキ層を形成するための
メッキレジストパターンは、次のような考え方で形成す
るとよい。まず厚肉回路パターンの中から最も幅の狭い
厚肉回路パターンを選び出し、そのパターンの幅を基準
幅とする。これに対して厚肉回路パターンの中でこの基
準幅より幅の広いものについては次の〜の事項を考
慮する。
Incidentally, a plating resist pattern for forming the thickened plating layer may be formed according to the following concept. First, the narrowest thick circuit pattern is selected from the thick circuit patterns, and the width of the pattern is set as a reference width. On the other hand, the following items (1) to (5) are considered for the thick circuit patterns having a width wider than the reference width.

【0014】 厚肉回路パターンの幅が基準幅の2倍
以上であるときは、形成する増厚メッキ層を幅方向に複
数に分割するため、厚肉回路パターンの内部に長手方向
に連続するメッキレジストの細い島(図2の5A1がこ
れに相当)を配置する。このメッキレジストの島の幅
は、それ自身を正確に現像でき、かつ銅箔からの十分な
剥離強度が得られる最小の幅以上とする。例えばメッキ
レジストの厚さが約150μmの場合は、0.5mm以
上の幅にすることが好ましい。メッキレジストの細い島
を配置したときは、それによって増厚メッキ層の断面積
が減少するのを補うため厚肉回路パターンの幅を広く補
正する必要がある。メッキレジストの島の幅が広いと、
その分厚肉回路パターンの幅を広くしなければならない
ので、島の幅は0.5〜1.0mm程度にするのが現実
的である。
When the width of the thick circuit pattern is not less than twice the reference width, the thick plating layer to be formed is divided into a plurality of parts in the width direction. A thin island of resist (5A1 in FIG. 2 corresponds to this) is arranged. The width of the island of the plating resist should be equal to or larger than the minimum width at which the plating resist itself can be developed accurately and sufficient peel strength from the copper foil can be obtained. For example, when the thickness of the plating resist is about 150 μm, the width is preferably 0.5 mm or more. When thin islands of the plating resist are arranged, it is necessary to widen the width of the thick circuit pattern in order to compensate for the decrease in the cross-sectional area of the thick plating layer due to this. If the width of the plating resist island is wide,
Since the width of the thick circuit pattern must be increased by that amount, it is practical to set the width of the island to about 0.5 to 1.0 mm.

【0015】 スルーホール加工が施されず、かつシ
ールドなどの目的を持っていないベタパターンに関して
は、円形や角形またはその他の形状のメッキレジストの
島を配置してよい。ただし、島の数が多く、それぞれの
大きさが小さいときは、増厚メッキ層を絶縁基板に埋め
込むときに、樹脂の流れやプリプレグの追従性に悪影響
を及ぼし、剥離強度が低下するおそれがあるため、注意
が必要である。
For a solid pattern that is not subjected to through-hole processing and has no purpose such as shielding, a circular, square or other shape of a plating resist island may be arranged. However, when the number of islands is large and the size of each is small, when the thickened plating layer is embedded in the insulating substrate, the flow of the resin and the followability of the prepreg are adversely affected, and the peel strength may be reduced. Therefore, care must be taken.

【0016】 回路基板を製造する過程で、スルーホ
ール加工が施される円形やその他形状のランドについて
は、〔スルーホール径−1mm〕程度のメッキレジスト
の島(図2の5A2、5B2がこれに相当)を設ける
と、メッキ厚を均一化できるだけでなく、メッキ面積を
少なくでき、かつ加工ドリルの負担も少なくできる。
In the process of manufacturing a circuit board, for a land having a circular shape or other shape to be subjected to through-hole processing, an island of plating resist having a diameter of [through-hole diameter of -1 mm] (5A2 and 5B2 in FIG. The provision of (equivalent) makes it possible not only to make the plating thickness uniform, but also to reduce the plating area and the load on the working drill.

【0017】以上のようにしてメッキレジスト5A、5
Bを形成した後、薄肉銅箔3A、3Bを電極として電気
メッキを行う。これによってメッキレジスト5A、5B
で覆われていない領域に、図3に示すように銅の増厚メ
ッキ層7A、7Bを形成する。この実施形態では、各増
厚メッキ層7A、7Bの幅を、最も狭い増厚メッキ層の
幅に合わせてほぼ同じにしてあるので、各増厚メッキ層
7A、7Bは両側縁で若干メッキ厚が厚くなる傾向はあ
るものの、厚さのバラツキは小さくて済む。
As described above, the plating resists 5A, 5A
After forming B, electroplating is performed using the thin copper foils 3A and 3B as electrodes. Thereby, the plating resists 5A, 5B
Copper thick plating layers 7A and 7B are formed in the areas not covered with the metal as shown in FIG. In this embodiment, the width of each of the thickened plating layers 7A and 7B is made substantially the same in accordance with the width of the narrowest thickened plating layer. Although the thickness tends to be thick, the variation in thickness can be small.

【0018】これに対し図8に示すように、増厚メッキ
層7A、7Bに幅の狭いものと広いものとがある場合に
は、例えば幅の広い増厚メッキ層7A(図8の左上)で
は両側縁のメッキ層の盛り上がりが大きくなるが、その
隣の幅の狭い増厚メッキ層7Aでは両側縁のメッキ厚の
盛り上がりが小さくなる。その結果、これを用いて最終
的に回路基板を構成すると、図9のように、幅の広い増
厚メッキ層7Aの両側縁が絶縁基板13に深く食い込む
ため、厚さ方向の絶縁距離を確保できなくなるという問
題が生じる。
On the other hand, as shown in FIG. 8, when the thickened plating layers 7A and 7B include a narrow one and a wide one, for example, the wide thickened plating layer 7A (upper left of FIG. 8) In this case, the swelling of the plating layers on both side edges becomes large, but the swelling of the plating thickness on both side edges becomes small in the adjacent thickened plating layer 7A having a small width. As a result, when a circuit board is finally formed using this, as shown in FIG. 9, both side edges of the wide thick plating layer 7 </ b> A penetrate deeply into the insulating substrate 13, so that the insulation distance in the thickness direction is secured. There is a problem that it becomes impossible.

【0019】この実施形態では図3に示すように、幅の
広い増厚メッキ層7Aに相当する部分が、幅方向に三分
割されているため、増厚メッキ層7A、7Bの厚さのバ
ラツキが小さくなる。
In this embodiment, as shown in FIG. 3, since the portion corresponding to the wide thick plating layer 7A is divided into three in the width direction, the thickness of the thick plating layers 7A and 7B varies. Becomes smaller.

【0020】次に、メッキレジスト5A、5Bを除去す
ると、図4に示すように、銅箔3A、3B上に得ようと
する厚肉回路パターンに対応するパターンの増厚メッキ
層7A、7Bが得られる。その後、積層時の位置決めの
ため、合わせフィルムを使用してガイド穴(図示せず)
を形成する。ガイド穴は前工程で予め形成しておいても
よい。
Next, when the plating resists 5A and 5B are removed, as shown in FIG. 4, the thickened plating layers 7A and 7B having a pattern corresponding to the thick circuit pattern to be obtained on the copper foils 3A and 3B are formed. can get. Then, a guide hole (not shown) using a laminated film for positioning during lamination
To form The guide holes may be formed in advance in the previous step.

【0021】次に図5に示すように、増厚メッキ層7
A、7Bを形成した側の面を内側にして対向させ、その
間にプリプレグ9を適当枚数挟んで積層する。積層する
プリプレグのうち最上層と最下層のプリプレグには、増
厚メッキ層7A、7Bが入る穴11を形成しておくこと
が好ましい。またプリプレグは繊維が増厚メッキ層の突
起形状に追従できるように、重ね合わせるときに各層厚
さの異なるものを使用してもよい。
Next, as shown in FIG.
The prepregs 9 are stacked with an appropriate number of prepregs 9 interposed therebetween with the surfaces on which the A and 7B are formed facing inside. It is preferable that holes 11 for receiving the thick plating layers 7A and 7B are formed in the prepregs of the uppermost layer and the lowermost layer among the prepregs to be laminated. Also, prepregs having different layer thicknesses may be used at the time of superposition so that the fibers can follow the projections of the thickened plating layer.

【0022】なお、銅箔3A、3Bおよび厚メッキ層7
A、7Bの表面には、プリプレグ9との接着性を向上さ
せるため、積層前に黒化処理などの粗面化処理を施して
おくことが好ましい。
The copper foils 3A and 3B and the thick plating layer 7
The surfaces of A and 7B are preferably subjected to a surface roughening treatment such as a blackening treatment before lamination in order to improve the adhesion to the prepreg 9.

【0023】次に、図5のように積層したものをホット
プレスで加熱加圧した後、支持板1A、1Bを除去する
と図6のような銅張り積層板が得られる。この銅張り積
層板は、増厚メッキ層7A、7Bが絶縁基板13の肉厚
の中に埋め込まれ、銅箔3A、3Bが絶縁基板13の表
面に積層されたものとなる。
Next, the laminate as shown in FIG. 5 is heated and pressed by a hot press, and then the support plates 1A and 1B are removed to obtain a copper-clad laminate as shown in FIG. In this copper-clad laminate, the thickened plating layers 7A and 7B are embedded in the thickness of the insulating substrate 13, and the copper foils 3A and 3B are laminated on the surface of the insulating substrate 13.

【0024】なお、ホットプレス後の支持板1A、1B
の除去を容易にするには、支持板1A、1Bに銅箔3
A、3Bを張り付けるときに、加熱すると接着力が低下
するタイプの接着剤(例えば熱硬化性樹脂が配合された
接着剤)を用いるとよい。そうすると、図5の積層体を
加熱加圧するときの熱で、支持板1A、1Bと銅箔3
A、3Bとの接着力が低下するので、支持板1A、1B
を容易に剥がすことができる。また支持板1A、1Bを
除去するためには、接着力の弱い接着剤を使用すること
も考えられる。
The support plates 1A, 1B after hot pressing
In order to facilitate the removal, copper foil 3
When attaching A and 3B, it is preferable to use a type of adhesive (for example, an adhesive in which a thermosetting resin is blended) whose adhesive strength is reduced when heated. Then, the heat when the laminate of FIG. 5 is heated and pressurized causes the support plates 1A and 1B and the copper foil 3
A, since the adhesive strength with 3B decreases, the support plates 1A, 1B
Can be easily peeled off. In order to remove the support plates 1A and 1B, it is also conceivable to use an adhesive having a low adhesive strength.

【0025】これ以降の工程は通常の回路基板の製造工
程と同様である。すなわち、所定の位置にスルーホール
用の貫通孔を形成した後、貫通孔の内面に図7のように
銅メッキ層19を設けて、スルーホールを形成する。こ
の銅メッキ層19は銅箔3A、3Bの表面にも形成され
る。次に両面にドライフィルムを張り付けてパターン露
光、現像を行い、薄肉回路パターン(小電流用)と厚肉
回路パターン(大電流用)に対応するパターンのエッチ
ングレジストを形成する。このあとエッチングを行って
薄肉導体3Aと19、3Bと19の不要領域を溶去した
後、エッチングレジストを除去すると、図1のような複
合回路基板が得られる。
The subsequent steps are the same as the ordinary circuit board manufacturing steps. That is, after a through hole for a through hole is formed at a predetermined position, a copper plating layer 19 is provided on the inner surface of the through hole as shown in FIG. 7 to form a through hole. This copper plating layer 19 is also formed on the surfaces of the copper foils 3A and 3B. Next, a dry film is adhered to both sides, and pattern exposure and development are performed to form an etching resist having a pattern corresponding to a thin circuit pattern (for small current) and a thick circuit pattern (for large current). Thereafter, etching is performed to remove unnecessary regions of the thin conductors 3A and 19, 3B and 19, and then the etching resist is removed to obtain a composite circuit board as shown in FIG.

【0026】この複合回路基板は、絶縁基板13の両面
に小電流用の薄肉回路パターン23A、23Bと大電流
用の厚肉回路パターン25A、25Bを有している。薄
肉回路パターン23A、23Bの厚さは図1からも明ら
かなように銅箔3A、3Bにそれぞれ銅メッキ層19が
プラスされた厚さである。また厚肉回路パターン25
A、25Bの厚さは銅箔3A、3Bにそれぞれ増厚メッ
キ層7A、7Bと銅メッキ層19がプラスされた厚さで
ある。厚肉回路パターンの中には幅の広い厚肉回路パタ
ーン25A(図1の右上)もあるが、この厚肉回路パタ
ーン25Aは増厚メッキ層7A、7Bが幅方向に三分割
されていて厚さのバラツキが小さいので、絶縁基板13
で厚さ方向の必要な絶縁距離を確保することは容易であ
る。
This composite circuit board has thin circuit patterns 23A and 23B for small current and thick circuit patterns 25A and 25B for large current on both sides of the insulating substrate 13. As is clear from FIG. 1, the thickness of the thin circuit patterns 23A and 23B is a thickness in which the copper plating layers 19 are added to the copper foils 3A and 3B, respectively. Also, the thick circuit pattern 25
The thicknesses of A and 25B are the thicknesses obtained by adding the thicker plating layers 7A and 7B and the copper plating layer 19 to the copper foils 3A and 3B, respectively. Among the thick circuit patterns, there is also a thick circuit pattern 25A having a large width (upper right in FIG. 1). However, this thick circuit pattern 25A is formed by dividing the thickened plating layers 7A and 7B into three in the width direction and increasing the thickness. Since the variation in the height is small, the insulating substrate 13
It is easy to secure the required insulation distance in the thickness direction.

【0027】またこの回路基板では、薄肉回路パターン
23A、23Bはその厚さ分が絶縁基板13の表面から
突出している。厚肉回路パターン25A、25Bは全厚
さのうち薄肉回路パターン23A、23Bと同じ厚さ分
が絶縁基板13の表面から突出し、残る厚さ分が絶縁基
板13に埋め込まれた状態となっている。したがって薄
肉回路パターン23A、23Bの表面と厚肉回路パター
ン25A、25Bの表面は同レベルに位置することにな
る。
In this circuit board, the thin circuit patterns 23A and 23B project from the surface of the insulating substrate 13 by the thickness. The thick circuit patterns 25A and 25B have the same thickness as the thin circuit patterns 23A and 23B of the entire thickness protruding from the surface of the insulating substrate 13, and the remaining thickness is embedded in the insulating substrate 13. . Therefore, the surfaces of the thin circuit patterns 23A and 23B and the surfaces of the thick circuit patterns 25A and 25B are located at the same level.

【0028】この複合回路基板には、このあと、ソルダ
ーレジストの形成、シルク文字の印刷、ノンスルーホー
ル穴加工、はんだレベラー等の表面処理、外形加工等が
施されるが、これらの工程では、絶縁基板の表面から突
出する回路パターンの厚さが通常の回路基板と同様に薄
く、かつ回路パターンの表面に段差がないため、通常の
設備を使用して容易に加工を行うことができる。
This composite circuit board is then subjected to solder resist formation, silk character printing, non-through hole drilling, surface treatment such as a solder leveler, outer shape processing, and the like. Since the thickness of the circuit pattern protruding from the surface of the insulating substrate is as thin as that of a normal circuit board, and there is no step on the surface of the circuit pattern, the processing can be easily performed using ordinary equipment.

【0029】〔その他の実施形態〕前記実施形態では、
絶縁基板13の両面に厚肉回路パターン25A、25B
を設けたが、厚肉回路パターンは絶縁基板の片面のみに
設ける場合もある。また前記実施形態では、回路パター
ンが2層の場合を示したが、一部の層の回路パターンを
絶縁基板内に埋め込むようにすれば、3層以上の回路パ
ターンを有する回路基板とすることも可能である。
[Other Embodiments] In the above embodiment,
Thick circuit patterns 25A, 25B on both sides of insulating substrate 13
However, the thick circuit pattern may be provided only on one side of the insulating substrate. Further, in the above-described embodiment, the case where the circuit pattern has two layers is shown. However, if the circuit patterns of some layers are embedded in the insulating substrate, a circuit board having three or more circuit patterns may be used. It is possible.

【0030】[0030]

【発明の効果】以上説明したように本発明によれば、薄
肉導体と増厚メッキ層とで構成される厚肉回路パターン
を有する回路基板において、厚肉回路パターンの増厚メ
ッキ層の厚さのバラツキを小さくすることができるの
で、絶縁基板の厚さを厚くすることなく厚さ方向の必要
な絶縁距離を確保することができる。
As described above, according to the present invention, in a circuit board having a thick circuit pattern composed of a thin conductor and a thick plating layer, the thickness of the thick plating layer of the thick circuit pattern is increased. Therefore, the required insulation distance in the thickness direction can be ensured without increasing the thickness of the insulating substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明に係る回路基板の一実施形態を示す断
面図。
FIG. 1 is a sectional view showing an embodiment of a circuit board according to the present invention.

【図2】 図1の回路基板を製造する最初の段階を示す
断面図。
FIG. 2 is a sectional view showing an initial stage of manufacturing the circuit board of FIG. 1;

【図3】 図2の次の段階を示す断面図。FIG. 3 is a sectional view showing the next stage of FIG. 2;

【図4】 図3の次の段階を示す断面図。FIG. 4 is a sectional view showing the next stage of FIG. 3;

【図5】 図4の次の段階を示す断面図。FIG. 5 is a sectional view showing the next stage of FIG. 4;

【図6】 図5の次の段階を示す断面図。FIG. 6 is a sectional view showing the next stage of FIG. 5;

【図7】 図6の次の段階を示す断面図。FIG. 7 is a sectional view showing the next stage of FIG. 6;

【図8】 厚肉回路パターンを有する回路基板を製造す
る場合の問題点を示す断面図。
FIG. 8 is a cross-sectional view showing a problem when a circuit board having a thick circuit pattern is manufactured.

【図9】 厚肉回路パターンを有する回路基板の問題点
を示す断面図。
FIG. 9 is a sectional view showing a problem of a circuit board having a thick circuit pattern.

【符号の説明】[Explanation of symbols]

1A、1B:支持板 3A、3B:銅箔 5A、5B:メッキレジスト 7A、7B:増厚メッキ層 9:プリプレグ 13:絶縁基板 19:スルーホール用銅メッキ層 23A、23B:小電流用の薄肉回路パターン 25A、25B:大電流用の厚肉回路パターン 1A, 1B: support plate 3A, 3B: copper foil 5A, 5B: plating resist 7A, 7B: thicker plating layer 9: prepreg 13: insulating substrate 19: copper plating layer for through hole 23A, 23B: thinner for small current Circuit pattern 25A, 25B: Thick circuit pattern for large current

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板(13)と大電流用の厚肉回路パ
ターン(25A)とを有し、前記厚肉回路パターン(2
5A)は、所定の回路パターンに形成された薄肉導体
(3A、19)の片面に増厚メッキ層(7A)を設けた
ものからなり、前記薄肉導体(3A、19)が幅方向に
連続していて、増厚メッキ層(7A)が幅方向に複数に
分割されていることを特徴とする回路基板。
An insulating substrate (13) and a thick circuit pattern (25A) for a large current, wherein said thick circuit pattern (2) is provided.
5A) is formed by providing a thickened plating layer (7A) on one surface of a thin conductor (3A, 19) formed in a predetermined circuit pattern, and the thin conductor (3A, 19) is continuous in the width direction. Wherein the thickened plating layer (7A) is divided into a plurality in the width direction.
JP11991797A 1997-05-09 1997-05-09 Circuit board Pending JPH10313152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11991797A JPH10313152A (en) 1997-05-09 1997-05-09 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11991797A JPH10313152A (en) 1997-05-09 1997-05-09 Circuit board

Publications (1)

Publication Number Publication Date
JPH10313152A true JPH10313152A (en) 1998-11-24

Family

ID=14773388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11991797A Pending JPH10313152A (en) 1997-05-09 1997-05-09 Circuit board

Country Status (1)

Country Link
JP (1) JPH10313152A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006147881A (en) * 2004-11-19 2006-06-08 Multi:Kk Printed wiring board and manufacturing method therefor
JP2007134410A (en) * 2005-11-08 2007-05-31 Multi:Kk Printed wiring board with resistor circuit and method of manufacturing same
JP2009117598A (en) * 2007-11-06 2009-05-28 Denki Kagaku Kogyo Kk Circuit substrate and semiconductor device using the same
US7868464B2 (en) 2004-09-16 2011-01-11 Tdk Corporation Multilayer substrate and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7868464B2 (en) 2004-09-16 2011-01-11 Tdk Corporation Multilayer substrate and manufacturing method thereof
JP2006147881A (en) * 2004-11-19 2006-06-08 Multi:Kk Printed wiring board and manufacturing method therefor
JP4713131B2 (en) * 2004-11-19 2011-06-29 株式会社マルチ Printed wiring board and method for manufacturing the printed wiring board
JP2007134410A (en) * 2005-11-08 2007-05-31 Multi:Kk Printed wiring board with resistor circuit and method of manufacturing same
JP4713305B2 (en) * 2005-11-08 2011-06-29 株式会社マルチ Printed wiring board with resistance circuit and manufacturing method thereof
JP2009117598A (en) * 2007-11-06 2009-05-28 Denki Kagaku Kogyo Kk Circuit substrate and semiconductor device using the same

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