JPH10304251A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device in which deterioration of an output of a read circuit due to circuit noise of a fixed pattern noise(FPN) correction circuit is prevented with a small circuit scale. SOLUTION: An FPN correction circuit of a bolometer infrared ray sensor 101 of the image pickup device is provided with a bias current cancellation circuit 1000 that cancels a bias current except a signal current of all currents supplied to a bolometer. Dispersion in current caused by the dispersion in the resistance of the bolometer is stored in an FPN correction memory 109, a load resistance of a resistor group 106 that decides a bias current 1102 of the bias current cancellation circuit 1000 is changed for each pixel based on output digital data of the FPN correction signal generated in response to the resistance dispersion of each bolometer to be stored to control the bias current 1102 thereby correcting the FPN.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an F
The present invention relates to an imaging device having a PN (fixed pattern noise) correction circuit, and more particularly to a bolometer-type infrared imaging device having an FPN correction circuit for canceling a current variation caused by a resistance variation of a bolometer or the like.

[0002]

2. Description of the Related Art Generally, a solid-state image sensor has a variation in output called FPN (fixed pattern noise) due to variation in the characteristics of detectors of each pixel. Therefore, it is necessary to remove the FPN included in the image signal. In particular, in an infrared imaging device, the FPN included in the image signal hinders the circuit D range, so that the gain in the readout circuit cannot be sufficiently obtained.

Conventionally, in this type of infrared imaging apparatus, as shown in Japanese Patent Application No. 08-122163, for example, the main cause of FPN of a bolometer type infrared sensor which is a solid-state imaging device is a resistance of a detector of each pixel. FPN is generated in the output voltage by applying a constant voltage to the detector of each pixel in which the resistance value varies and applying a current to the detector, and the FPN is included in the image signal in order to improve the image quality. This F
PN needs to be removed.

FIG. 8 is a circuit diagram showing an example of a conventional infrared imaging device. In the figure, reference numeral 801 denotes a bolometer-type infrared sensor which is a solid-state imaging device; 802, a transistor;
03 is a bias voltage, 804 is an integration capacitor, 805
Is a transistor, 806 is a bias voltage, 807 is a resistor, 808 is a reset switch, 809 is a reset voltage, 810 is a transistor, 811 and 812 are resistors, 8
13 is an amplifier, 814 is a clamp circuit, 815 is A / D
Converter, 816 is an integrating circuit, 817 is a memory, 818 is an averaging circuit, 819 is a D / A converter, 820 is an amplifier, 821 is a capacitor, I801 is a discharge current,
802 is a bias current, and I803 is a sensor current.

[0005] The bolometer type infrared sensor 801 is connected to the emitter of the transistor 802, and the sensor current I803 flows. This sensor current I803 is synthesized from a discharge current I801 from the integration capacitor 804 and a bias current I802 provided by a constant current circuit including a transistor 805, a bias voltage 806, and a resistor 807. The potential of the integration capacitor 804 is reset by the reset switch 808 to the potential of the reset voltage 809 during a reset period for each pixel cycle. Resistance 8
11, a resistor 812 and a transistor 810 are a source follower circuit composed of FETs,
4 is output.

[0006] Individual detector resistance R _B of the bolometer type infrared sensor 801 is varied, different, the potential change of the integration capacitor 804 varies the discharge current I801 from the integration capacitor 804 by each pixel, F
PN occurs. The output of the source follower circuit including this FPN passes through an amplifier 813 and a clamp circuit 814, and is then subjected to A / D conversion.
The digital signal is converted by the converter 815, and the integration circuit 816
, A signal of several tens of frames is integrated, and is taken into the memory 817. The data taken in the memory 817 is averaged by an averaging circuit 818. The output of the averaging circuit 818 is converted to an analog signal by the D / A converter 819, the gain of the feedback loop is adjusted by the amplifier 820, and the gain is added to the bias voltage 803 via the capacitor 821 to perform feedback control. As described above, conventionally, the bias voltage 803 is changed in accordance with the variation in the resistance value RB of the bolometer-type infrared sensor 801 to keep the current value flowing through the bolometer constant, thereby removing FPN.

[0007]

SUMMARY OF THE INVENTION As described above, the conventional F
In the PN correction circuit, the FPN correction signal is fed back to a voltage for controlling the current flowing through the bolometer. FP
It is difficult to sufficiently reduce circuit noise such as output noise of the D / A converter included in the N correction signal with respect to minute sensor noise such as Johnson noise of the bolometer,
Therefore, the output of the read circuit may be deteriorated by noise.

SUMMARY OF THE INVENTION An object of the present invention is to provide an FP with a small circuit scale.
It is an object of the present invention to provide an image pickup apparatus capable of preventing the noise of the output of the readout circuit from deteriorating due to the circuit noise of the N correction circuit.

[0009]

According to the present invention, there is provided an imaging apparatus comprising: a solid-state imaging device in which detectors are arranged in a predetermined arrangement; a unit for reading an output of the solid-state imaging device; and a solid-state image sensor corresponding to each of the detectors Means for recording the variation amount of the output of the image sensor, outputting the recorded variation amount corresponding to each detector, and outputting the output as a correction value to means for inputting the output and reading out the output of the solid-state image sensor Output correction means.

The output correcting means may be a bias current canceling circuit for simultaneously canceling a bias current component of the signal of the solid-state image sensor and a bias current component of the signal of the solid-state image sensor. It may be a combination of a constant current circuit for canceling a current component and a bias current canceling circuit for canceling a variation in a bias current component of a signal of the solid-state imaging device.

[0011] The bias current canceling circuit may be composed of a resistor group and a switch group having binary weights.
It may be composed of an R-2R ladder resistor network and a switch group.

[0012] The imaging device may be an infrared imaging device.

The FPN correction circuit of the bolometer type infrared sensor according to the present invention includes a bias current canceling circuit for canceling a bias current excluding a signal current in a total current flowing through the bolometer, and a current generated by a resistance variation of the bolometer. The FP is controlled by changing the load resistance that determines the amount of bias current of the bias current canceling circuit for each pixel by using an FPN correction signal generated according to the amount of resistance variation of the bolometer, and controlling the amount of bias current.
N correction is performed.

In this correction method, the load resistance of the bias current canceling circuit can be switched by a switch using the FPN correction signal, which is digital data, so that FPN correction can be performed. In addition, since the bias current canceling circuit has a D / A conversion function, a circuit configuration such as a D / A converter provided separately from the readout circuit as in the conventional example becomes unnecessary, and the circuit scale is reduced. Is done.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a readout circuit including an FPN correction circuit of an infrared sensor of a bolometer type infrared imaging device according to a first embodiment of the present invention.
In the figure, reference numeral 101 is a bolometer type infrared sensor, 102 is a transistor, 103 is a bias voltage, 104 is a transistor, 105 is a bias voltage, 106 is a resistor group, 10
7 is a switch group, 108 is output digital data, 109
Is an FPN correction memory, 110 is a reset pulse, 111
Is a reset switch, 112 is a reset voltage, 113 is an integration capacitor, 114 is an FET, 115 is a resistor, 11
6 is a read circuit output, 1000 is a bias current canceling circuit, 10,000 is a read circuit, I101 is a discharge current,
I102 is a bias current, and I103 is a sensor current.

Referring to FIG. 1, in the readout circuit 10000 of the image pickup apparatus of the present invention, an integrating capacitor 113 is provided.
Are reset pulse 110 and reset switch 11
1 resets to the potential of the reset voltage 112.
The bolometer type infrared sensor 101 includes a transistor 1
02, the bias voltage 103 [(bias voltage 1
03—base-emitter voltage of transistor 102)
/ Sensor resistance R _B ]. This sensor current is composed of a bias current I102 given by a bias current canceling circuit 1000 composed of a transistor 104, a bias voltage 105, a resistor group 106, and a switch group 107, and a discharge current I101 from an integrating capacitor 113. It can be expressed as an equation.

I103 = I101 + I102 (1) I101: Discharge current from the integrating capacitor 113 I102: Bias current from the bias current canceling circuit 1000 I103: Sensor current flowing through the bolometer type infrared sensor 101 FET114, Source follower composed of resistor 115 The circuit outputs a change in potential of the integrating capacitor 113.

Next, the circuit operation of FIG. 1 will be described with reference to the drawings. 2A and 2B are waveform diagrams showing the operation of the first embodiment, in which FIG. 2A shows a read circuit output, FIG. 2B shows a clock of a bolometer type infrared sensor, FIG. 2C shows a reset pulse, and FIG. This is the output digital data of the correction memory. FIG. 3 is a configuration diagram showing an example of a bolometer type infrared sensor. In the figure, reference numeral 301 denotes a horizontal shift register, 302 denotes a vertical shift register, and 303 denotes a horizontal AN.
D, 304 is a vertical AND, 305 is a horizontal switch, 30
6 is a vertical switch, 307 is a horizontal signal line, 308 is a vertical signal line, 309 is a common source line, 310 is a bolometer, and 311 is a sensor output.

The reset pulse 110 shown in FIG. 2C is turned on.
During the period, the bolometer type infrared sensor 101 shown in FIG.
The pixel is switched by the clock of. Here, the bolometer-type infrared sensor 101 is configured as shown in FIG. 3, and includes a horizontal shift register 301, a vertical shift register 302,
Each pixel is sequentially selected by the horizontal switch 305 and the vertical switch 306. Readout circuit output 11 of FIG.
6 shows a change in the potential of the integration capacitor 113. The potential of the integration capacitor 113 is reset to the potential of the reset voltage 112 during the ON period of the reset pulse 110, and from the integration capacitor 113 during the OFF period of the reset pulse 110. And the bias current I102 given by the bias current canceling circuit 1000.
Flows into the bolometer-type infrared sensor 101.

[0020] Here, the output voltage V1 of the readout circuit output _{116, V1 = V R - (I101} · t / C1) (2) V R: reset voltage 112 I101: the integrating capacitor 113 discharges current t: integration time ( OFF period of reset switch 111) C1: expressed by the capacitance of integration capacitor 113, bias voltage 103 is constant, bias voltage 1
05, the resistor group 106, (is or bias current I102 fixed) certain conditions and situations that can switch group 107 Under are variations in the resistance value R _B of each detector of the sensor, the discharge of the integration capacitor 113 Since the current I101 is different between the detectors, the output voltage V1 of the read circuit output 116 also fluctuates, generating FPN and hindering the circuit D range.

[0021] Accordingly, the present invention may have variations in resistance R _B of each detector of the sensor, as the discharge current I101 of the integrating capacitor 113 is constant, the resistance variation of the sensor corresponding to the individual detectors FP for storing data
The output digital data 108 corresponding to each selected pixel from the N correction memory 109 is used to generate the bias current canceling circuit 1
Operating the switch group 107 of 000, switches the resistor group 106, by selecting the corresponding to each pixel selected resistance, the resistance value of the sensor of the R _B, according to the variation, changing the bias current I102.

In the first embodiment, the case where the output digital data 108 of the FPN correction memory 109 is 4 bits is shown as an example. Therefore, the resistor group 106 and the switch group 107 are also shown for 4 bits.

The actual output digital data 108 of the FPN correction memory 109 and the bias current canceling circuit 1000
Is determined by the following equation, where n is the number of bits and X is the resolution of the FPN.

N = logX / log2 (3.1) X = (△ R · Vet ·) / (DR · C1 · R _B ) (3.2) ΔR: Ratio of variation to resistance value R _B of sensor Ve: Emitter voltage of transistor 102 t: Integration time (OFF period of reset switch 111) DR: D range of readout circuit C1: Capacity of integration capacitor 113 R _B : Sensor resistance value For example, ΔR = 10%, Ve = 3 V, t = 60 μs, D
When R = 2V, C1 = 20pF, R _B = 3kΩ, bit
The number n is 7.288..., And 8 bits or more are required.

The FPN correction operation using the bias current canceling circuit 1000 will be described with reference to the drawings.
FIG. 4 is a detailed circuit diagram of the bias current canceling circuit and the peripheral circuit according to the first embodiment of the present invention. Reference numeral 401 in the figure
Is a bolometer type infrared sensor, 402 is a transistor,
403 is a bias voltage, 404 is a transistor, 405
Are bias voltages, 406a, 406b, 406c, 40
6d is a resistor, 407a, 407b, 407c, 407d
Is a switch, 408 is output digital data, 409 is F
PN correction memory 4000 is a bias current canceling circuit,
060 is a resistor group, 4070 is a switch group, I401 is a discharge current, I402 is a bias current, and I403 is a sensor current.

The resistor group 4060 includes a resistor 406a, a resistor 4
06b, a resistor 406c, and a resistor 406d. Assuming that the resistance value of the resistor 406a is R, the resistor 406b has 2R, the resistor 406c has 4R, and the resistor 406d.
Are weighted by binarization like 8R. Also,
The switch group 4070 includes a switch 407a, a switch 4
07b, a switch 407c, and a switch 407d. The resistors 406a, 406b, 406c,
It is connected to the resistor 406d. ON / O of each switch
The pulse for switching the FF is the output digital data 408 of the FPN correction memory 409, and the MSB data line of the output digital data 408 is connected to the switch 407a.
The data line B-1 is connected to the switch 407b, the data line MSB-2 is connected to the switch 407c, and the data line LSB is connected to the switch 407c. With such a configuration, the load resistance value connected to the transistor 404 has the data of the resistance variation of the sensor by each detector.
The bias current I402 changes according to the output digital data 408 of the PN correction memory 409, and is generated from the voltage given by V _DD and the voltage between the emitters of the transistor 404.
Changes.

Here, a specific operation of the bias current canceling circuit 4000 will be considered. V _DD and transistor 404
The voltage between the emitters is V2. Resistances 406a, 406b, 406c, 406d constituting resistance group 4060
Is weighted by binarization, so for example, F
M of the output digital data 408 of the PN correction memory 409
When only data equivalent to SB is valid (only the switch 407a is conducting), the bias current I402 becomes (V
2 / R). Also, the FPN correction memory 40
When only the data corresponding to the LSB of the output digital data 408 of No. 9 is valid (only the switch 407d is conductive), a current of (V2 / 8R) flows as the bias current I402. Further, all the bits of the output digital data 408 of the FPN correction memory 409 are valid (the switch group 40
70 are all conducting), the bias current I4
In 02, a current of (15V2 / 8R) flows. Thus, the output digital data 40 of the FPN correction memory 409 is
The eight states of, can control the bias current 1402, for example, by setting the bias current value flowing MSB corresponding bias current 1402 when the average value of the resistance values R _B of the bolometer type infrared sensor 401, FPN correction memory 4
By the output digital data 408 of 09, the bias current I402 can be increased or decreased based on its average value.

From the above, the variation current canceling circuit 4
000 is the resistance value R of the bolometer type infrared sensor 401
_The sensor current I flowing through the bolometer due to the variation of _B
Even if 403 is different for each pixel, the bias current I402
Increases or decreases so as to offset the amount of current variation,
The discharge current I401 from the integrating capacitor 413 is kept constant. Therefore, FPN at the output of the read circuit is reduced, and the circuit D range can be effectively used.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a view showing an infrared sensor F of the bolometer type infrared imaging apparatus according to the second embodiment of the present invention.
FIG. 3 is a circuit diagram of a readout circuit including a PN correction circuit. In the drawing, reference numeral 501 denotes a bolometer-type infrared sensor, 502 denotes a transistor, 503 denotes a bias voltage, 504 denotes a transistor, 505 denotes a bias voltage, 506 denotes a resistor group, and 507.
Is a switch group, 508 is output digital data, 509 is an FPN correction memory, 510 is a reset pulse, 511 is a reset switch, 512 is a reset voltage, 513 is an integration capacitor, 514 is an FET, 515 is a resistor, and 516 is a resistor.
Is a readout circuit output, 517 is a transistor, 518 is a bias voltage, 519 is a resistor, 5000 is a bias current canceling circuit, 5100 is a constant current source circuit, 50000 is a readout circuit, I501 is a discharge current, I502 is a bias current, and I503 is a sensor. The current, I504, is a bias current.

When comparing the second embodiment of FIG. 5 with the first embodiment of FIG. 1, a constant current source circuit 5 comprising a transistor 517, a bias voltage 518, and a resistor 519.
100 is added. Therefore, the sensor current I503 flowing through the bolometer-type infrared sensor 501 includes a discharge current I501 from the integration capacitor 513, a bias current I502 from the bias current canceling circuit 5000, and a bias current I504 from the constant current source circuit 5100. It can be expressed as the following equation.

I503 = I501 + I502 + I504 (4) I501: Discharge current from integration capacitor 513 I502: Bias current from bias current canceling circuit 5000 I503: Sensor current flowing through bolometer type infrared sensor 501 I504: Bias from constant current source circuit 5100 Current Here, a comparison between the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 5 will be shown using specific numerical examples. First, considering the number of bits of the bias current canceling circuit 1000 and the FPN correction memory 109 in the first embodiment, the number of bits determined by the above equations (3.1) and (3.2) is necessary. Become.

On the other hand, in the second embodiment, there are two bias current components, a bias current I502 from the bias current canceling circuit 5000 and a bias current I504 from the constant current source circuit 5100. variations in the resistance value R _B of the sensor 501 (△ R) is the resistance value R assuming there 10% relative to _B, 90% of the equivalent current constant current source circuit with the exception of 10% variation current operating conditions of the readout circuit The bias current I 504 from 5100 flows as a fixed value, and the variation current 1
The current corresponding to 0% is set to flow with the bias current I502 from the bias current canceling circuit 5000. As a result, the resolution of the FPN of the bias current canceling circuit 5000 becomes 10% as compared with the first embodiment, and the bias current canceling circuit 5000 and the FPN correction memory 509 are used.
Can be correspondingly reduced.

As described above, by adding the constant current source circuit 5100 shown in the second embodiment in FIG. 5, the bias current canceling circuit 5000 and the FPN correction memory 50 are added.
Nine bits can be reduced. However, when the bias current canceling circuit 5000 and the constant current source circuit 5100 are used in the read circuit, the bias current canceling circuit 5000
And the Johnson noise of the load resistance of the constant current source circuit 5100 are added to the Johnson noise of the bolometer of the bolometer-type infrared sensor 501 by ^1/2 times (bolometer resistance value / load resistance value). It is desirable that the load resistance value of the canceling circuit 5000 and the constant current source circuit 5100 be larger than the bolometer resistance value.

When the number of bits is increased in the bias current canceling circuits 1000 and 5000 shown in the first and second embodiments, the spread of the resistance values constituting the resistance groups 107 and 507 is greatly increased by the binary weighting. growing. For example, at the time of 8 bits, the resistance value of the LSB is 128 times the resistance value of the MSB. If the spread of the resistance value is to be generated on a chip, it is difficult to obtain sufficient precision without trimming in the case of a thin film resistor, and it is sometimes difficult to realize the resistance value because of a limitation of the chip area.

Therefore, the configuration of the resistor modified so as to exclude components having a wide range of values of the binary weighting resistor is as follows:
This is an R-2R ladder circuit often used in a D / A converter, and includes a bias current canceling circuit 1000 according to the first embodiment shown in FIG. 1 and a second embodiment shown in FIG. The bias current canceling circuit 5000 described above can also be realized by a circuit configuration using the principle of an R-2R ladder circuit as shown in FIG. A third embodiment of the present invention will be described with reference to FIG.

FIG. 6 is a detailed circuit diagram of a bias current canceling circuit used in the imaging apparatus according to the third embodiment of the present invention. In the figure, reference numeral 604 denotes a transistor, 605 denotes a bias voltage, and 606 denotes an R-2R ladder. A resistor network, 607 is a switch group, 608 is output digital data, 609 is an FPN correction memory, 620 is a transistor, 621 is a bias voltage, 6000 is a bias current canceling circuit, and I602 is a bias current.

Referring to FIG. 6, R-2R ladder resistor network 606, switch group 607, transistor 604, bias voltage 605, transistor 620, bias voltage 6
21 constitutes a bias current canceling circuit 6000. Further, as the resistance constituting the R-2R ladder resistance network 606, those having resistance values of R and 2R are used.
Can be realized by connecting two resistors having a resistance value of R in series, so that the R-2R ladder resistor network 6
06 can be composed of one type of resistor having a resistance value of R.
Therefore, generation of the R-2R ladder resistance network 606 can be realized simply and accurately.

Next, considering a specific operation, assuming that the voltage between V _DD and the emitter voltage of the transistor 604 is V 3, the bias current I 602 is determined by the output digital data 608 of the FPN correction memory 609 on the MSB data line. V3 / 2R), MSB-1 data line (V3 / 4
R), MSB-2 data line (V3 / 8R), LSB
, Each current of (V3 / 16R) flows, and the bias current I602 is the sum of the currents of the individual bits. Here, the transistor 620 and the bias voltage 621 are composed of the same components and the same voltage value as the transistor 604 and the bias voltage 605, and the operation principle of the R-2R ladder circuit (the branch current of each network is a binary weighted relation). There is)
As a result, the emitter voltage of the transistor 604 and the emitter voltage of the transistor 620 become the same voltage.

The read-out circuit shown in the first, second and third embodiments can be used to form an on-chip configuration as shown in FIG. FIG. 7 is a partial circuit diagram of an imaging device according to a fourth embodiment of the present invention, and reference numeral 701 in the drawing.
Is a bolometer, 702 is a vertical switch, 703 is a signal read line, 704 is a vertical AND, 705 is a vertical shift register, 706 is a read circuit, 707 is an A / D converter, 708 is a multiplexer, and 709 is a sensor output.

The fourth embodiment will be described with reference to the drawings. The bolometer 701 is connected to the vertical switch 702, and is sequentially selected for each horizontal line by an output pulse of the vertical shift register 705. The signal readout line 703 is
The bolometer 701 is connected to a reading circuit 706 provided for each vertical line, and can read the bolometer 701 simultaneously for one horizontal line during one horizontal period. Here, the read circuit 706 includes the read circuit 10000 shown in FIG. 1 of the first embodiment and the read circuit 50000 shown in FIG. 5 of the second embodiment. The output of each read circuit 706 is converted into a digital signal by the A / D converter 707, and the multiplexer 708 sequentially outputs the digital signal. With this configuration, the sensor output 709 becomes only the digital data of the number of bits of the A / D converter 707, and the sensor can be made smarter and the number of external circuits can be reduced.

In the above description, the bolometer-type infrared imaging apparatus has been mainly described, but the imaging apparatus according to the present invention functions effectively in all imaging apparatuses. For example, in a one-dimensional or two-dimensional sensor using a PN junction as a detector, when a signal corresponding to the amount of incident light has a variation in the output signal of the sensor due to a component (wiring resistance or the like) connected in series with a resistor. The imaging device of the present invention can be applied to such a case.

[0042]

As described above, the first effect of the present invention is that there is no fear of noise deterioration. The reason is that in the conventional FPN correction circuit, the FPN correction signal is fed back to a voltage controlling the current flowing through the bolometer, so that the circuit noise (such as the output noise of the D / A converter) constituting the FPN correction signal is reduced by the Johnson of the bolometer. Although it is difficult to sufficiently reduce small sensor noise such as noise, and there is a risk of noise degradation, in the present invention, the load resistance of the bias current canceling circuit is reduced by the FPN correction signal which is digital data. Switch with a switch and F
Since the PN correction is performed, there is no fear of noise deterioration.

The second effect is that the circuit scale can be reduced. The reason is that the bias current cancellation circuit has D
This is because the / A conversion function is provided, so that a circuit configuration such as a D / A converter is not required separately from the readout circuit, and the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a readout circuit including an FPN correction circuit of an infrared sensor of a bolometer-type infrared imaging device according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of the first embodiment.
(A) is a read circuit output. (B) is a clock of the bolometer type infrared sensor. (C) is a reset pulse. (D) is digital data output from the FPN correction memory.

FIG. 3 is a configuration diagram illustrating an example of a bolometer-type infrared sensor.

FIG. 4 is a detailed circuit diagram of a bias current canceling circuit and a peripheral circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a readout circuit including an FPN correction circuit of an infrared sensor of a bolometer type infrared imaging device according to a second embodiment of the present invention.

FIG. 6 is a detailed circuit diagram of a bias current canceling circuit used in an imaging device according to a third embodiment of the present invention.

FIG. 7 is a partial circuit diagram of an imaging device according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of a conventional infrared imaging device.

[Explanation of symbols]

101, 401, 501, 801 Bolometer type infrared sensor 102, 402, 502, 802 Transistor 103, 403, 503 Bias voltage 104, 404, 504, 604 Transistor 105, 405, 505, 605 Bias voltage 106, 506 Resistor group 107, 507, 607 Switch group 108, 408, 508, 608 Output digital data 109, 409, 509, 609 FPN correction memory 110, 510 Reset pulse 111, 511 Reset switch 112, 512 Reset voltage 113, 513 Integrating capacitor 114, 514 FET 115 515 Resistor 116, 516 Readout circuit output 301 Horizontal shift register 302 Vertical shift register 303 Horizontal AND 304 Vertical AND 305 Horizontal switch 06 vertical switch 307 horizontal signal line 308 vertical signal line 309 common source line 310 bolometer 311 sensor output 406a, 406b, 406c, 406d resistor 407a, 407b, 407c, 407d switch 517 transistor 518 bias voltage 519 resistor 606 R-2R resistor network 620 Transistor 621 Bias voltage 701 Bolometer 702 Vertical switch 703 Signal read line 704 Vertical AND 705 Vertical shift register 706 Read circuit 707 A / D converter 708 Multiplexer 709 Sensor output 803 Bias voltage 804 Integration capacitor 805 Transistor 806 Bias voltage 807 Reset switch 80 809 Reset voltage 810 Transistor 811, 812 Resistance 81 Amplifier 814 Clamp circuit 815 A / D converter 816 Integration circuit 817 Memory 818 Averaging circuit 819 D / A converter 820 Amplifier 821 Capacitor 1000, 4000, 5000, 6000 Bias current canceling circuit 4060 Resistor group 4070 Switch group 5100 Constant current source Circuit 10000, 50000 Readout circuit I101, I401, I501, I801 Discharge current I102, I402, I502, I602, I802
Bias current I103, I403, I503, I803 Sensor current I504 Bias current

Claims (6)

[Claims] 1. A solid-state image sensor in which detectors are arranged in a predetermined arrangement, means for reading an output of the solid-state image sensor,
Means for recording a variation amount of the output of the solid-state imaging device corresponding to each of the detectors, and outputting the recorded variation amount in association with each of the detectors,
An output correction unit for inputting the output and reading out the output of the solid-state imaging device as a correction value. 2. The circuit according to claim 1, wherein said output correction means is a bias current canceling circuit for simultaneously canceling a bias current component of the signal of the solid-state image sensor and a bias current component of the signal of the solid-state image sensor. Imaging device. 3. A combination of a constant current circuit for canceling a bias current component of a signal of the solid-state imaging device and a bias current cancellation circuit for canceling a variation in a bias current component of a signal of the solid-state imaging device. Is,
The imaging device according to claim 1. 4. The bias current canceling circuit includes a resistor group and a switch group having binary weights.
The imaging device according to claim 2. 5. The bias current canceling circuit according to claim 2, wherein
3. A ladder resistor network and a switch group.
Alternatively, the imaging device according to claim 3. 6. The imaging device is an infrared imaging device.
The imaging device according to claim 1.