JPH10294498A - Manufacture of led display - Google Patents
Manufacture of led displayInfo
- Publication number
- JPH10294498A JPH10294498A JP9101719A JP10171997A JPH10294498A JP H10294498 A JPH10294498 A JP H10294498A JP 9101719 A JP9101719 A JP 9101719A JP 10171997 A JP10171997 A JP 10171997A JP H10294498 A JPH10294498 A JP H10294498A
- Authority
- JP
- Japan
- Prior art keywords
- ring
- liquid resin
- led display
- shaped frame
- sealing layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ガラスなどで形成
された平面基板上に、例えばドットマトリクス状として
複数のＬＥＤチップのダイボンドおよび配線が行われ、
更に上記ＬＥＤチップには透明樹脂による封止層が設け
られている構成とされたＬＥＤ表示器に関するものであ
り、詳細には前記ＬＥＤ表示器の製造方法に係るもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method in which a plurality of LED chips are die-bonded and wired in a dot matrix, for example, on a flat substrate made of glass or the like.
Further, the present invention relates to an LED display having a configuration in which a sealing layer made of a transparent resin is provided on the LED chip, and more particularly to a method of manufacturing the LED display.
【０００２】[0002]
【従来の技術】従来のこの種のＬＥＤ表示器９０の製造
方法における封止工程の例を示すものが図５であり、配
線パターン９１ａが形成された平面基板９１の面上に複
数のＬＥＤチップ９２をダイボンドし、更に金線（或い
はアルミニウム線）９３によりワイヤーボンドを行い配
線し、ドットマトリクスなど所定の配置としての配設を
行う。2. Description of the Related Art FIG. 5 shows an example of a sealing step in a conventional method of manufacturing an LED display 90 of this type. A plurality of LED chips are provided on a surface of a flat substrate 91 on which a wiring pattern 91a is formed. The die 92 is die-bonded, and further, wire-bonded with a gold wire (or aluminum wire) 93 for wiring, and a predetermined arrangement such as a dot matrix is performed.
【０００３】しかる後に、前記平面基板９１の面上に例
えば樹脂或いはゴムなどで形成されて前記ＬＥＤチップ
９２の配置に対応する形状とされた型枠９４を固定し、
この型枠９４内にシリコン樹脂、エポキシ樹脂などの透
明な液状樹脂を注入し、自然硬化、加熱硬化など適宜な
効果処理を行い、液状樹脂を硬化させ封止層９５を形成
するものである。Thereafter, a mold 94 made of, for example, resin or rubber and formed in a shape corresponding to the arrangement of the LED chips 92 is fixed on the surface of the flat substrate 91,
A transparent liquid resin such as a silicon resin or an epoxy resin is injected into the mold 94, and an appropriate effect treatment such as natural curing or heat curing is performed, and the liquid resin is cured to form the sealing layer 95.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、前記し
た従来の製造方法においては、封止層９５の形成の際
に、注入時には液状である樹脂に対し位置を保持させる
ために型枠９４を用いるものであるので、第一には、前
記型枠９４を使用することによる素材費の増加、型枠９
４を形成するための金型作成による費用の発生などによ
りＬＥＤ表示器９０がコストアップする問題点を生じて
いる。However, in the above-mentioned conventional manufacturing method, when the sealing layer 95 is formed, the mold 94 is used to hold the position of the liquid resin at the time of injection. Therefore, firstly, an increase in material cost due to the use of the formwork 94,
There is a problem that the cost of the LED display 90 is increased due to generation of a cost due to the production of a mold for forming the LED 4.
【０００５】また、第二には、既にＬＥＤチップ９２の
取付けが行われている平面基板９１に型枠９４の取付け
が行われることで、例えば金線９３の切断などを生じさ
せて分留まりが低下する問題点を生じると共に、例えば
前記平面基板９１がガラスで形成されている場合には、
前記型枠９４を固定するための構成が複雑になり、取付
作業が煩雑化して生産性が低下する問題点を生じ、これ
らの点の解決が課題とされるものと成っている。[0005] Second, by mounting the mold frame 94 on the flat substrate 91 on which the LED chips 92 have already been mounted, for example, the gold wires 93 are cut off, and the fractional break is caused. In addition to causing a problem of lowering, for example, when the flat substrate 91 is formed of glass,
The structure for fixing the formwork 94 becomes complicated, the mounting work becomes complicated, and there is a problem in that the productivity is reduced, and solving these points is an issue to be solved.
【０００６】[0006]
【課題を解決するための手段】本発明は前記した従来の
課題を解決するための具体的な手段として、平面基板上
に複数のＬＥＤチップを配設し、該ＬＥＤチップを透明
樹脂で覆う封止層を形成して成るＬＥＤ表示器の製造方
法において、前記封止層は、前記平面基板上に前記封止
層を形成するべき範囲の内法を有する枠状にフッ素樹脂
によるリング状枠部を形成し、このリング状枠部内に液
状の前記透明樹脂の適量を注入し固化させて形成するこ
とを特徴とするＬＥＤ表示器の製造方法を提供すること
で課題を解決するものである。According to the present invention, as a specific means for solving the above-mentioned conventional problems, a plurality of LED chips are arranged on a flat substrate, and the LED chips are covered with a transparent resin. In the method for manufacturing an LED display comprising a stop layer, the sealing layer is a ring-shaped frame portion made of a fluororesin in a frame shape having a method within a range where the sealing layer is to be formed on the flat substrate. The present invention solves the problem by providing a method for manufacturing an LED display, characterized in that an appropriate amount of the liquid transparent resin is injected into the ring-shaped frame portion and solidified.
【０００７】[0007]
【発明の実施の形態】つぎに、本発明を図に示す実施形
態に基づいて詳細に説明する。図１〜図４は本発明に係
るＬＥＤ表示器１の製造方法を工程の順に示すものであ
り、先ず、図１に示すように配線パターン２ａが形成さ
れた平面基板２の面上に、複数のＬＥＤチップ３がダイ
ボンドされ、続いて金線（或いはアルミ線）４によるワ
イヤーボンドが行われて、ドットマトリクス状など所定
の配置として取付けられるものである点は従来例のもの
と同様である。Next, the present invention will be described in detail based on an embodiment shown in the drawings. 1 to 4 show a method of manufacturing an LED display 1 according to the present invention in the order of steps. First, as shown in FIG. 1, a plurality of wiring patterns 2a are formed on a surface of a flat substrate 2 on which a wiring pattern 2a is formed. The LED chip 3 is die-bonded, followed by wire bonding with a gold wire (or aluminum wire) 4, and the LED chip 3 is mounted in a predetermined arrangement such as a dot matrix, as in the conventional example.
【０００８】ここで、本発明においては、従来例の型枠
に換えて、図２に示すように前記平面基板２の面上にリ
ング状枠部５を形成するものであり、このリング状枠部
５は、フッ素樹脂により以降に前記封止層６を形成する
べき範囲を取り囲むようにして、言い換えれば前記の範
囲を内法とする枠状にシルクスクリーン印刷など適宜な
手段で形成されるものである。Here, in the present invention, a ring-shaped frame portion 5 is formed on the surface of the flat substrate 2 as shown in FIG. 2 instead of the conventional frame. The portion 5 is formed of a fluororesin so as to surround a region where the sealing layer 6 is to be formed thereafter, in other words, is formed by a suitable means such as silk screen printing in a frame shape having the above range as an inner method. It is.
【０００９】尚、この実施形態では理解を容易とするた
めに工程の順序に従って説明を行うものとするので、リ
ング状枠部５はこの時点で形成するものとするが、実際
に実施に当たっては、前記平面基板２の形成時に、前記
配線パターン２ａと同様に予めに形成するものとしてお
いても良いものである。In this embodiment, the description will be made in accordance with the order of the steps for easy understanding. Therefore, the ring-shaped frame portion 5 is formed at this time. However, in actual implementation, When the planar substrate 2 is formed, it may be formed in advance similarly to the wiring pattern 2a.
【００１０】続いて、前記平面基板２は前記ＬＥＤチッ
プ３が搭載された面を水平に保たれ、リング状枠部５の
枠内には、図３に示すようにシリコン樹脂、或いは、エ
ポキシ樹脂など液状樹脂６Ａの適量の注入（滴下）が、
例えば定量の吐出が行えるものとした注入装置１０など
を用いて行われる。Subsequently, the surface of the flat substrate 2 on which the LED chips 3 are mounted is kept horizontal, and a silicon resin or an epoxy resin as shown in FIG. Injecting (dropping) an appropriate amount of the liquid resin 6A,
For example, the injection is performed using an injection device 10 or the like that can discharge a fixed amount.
【００１１】このようにすることで、例えばリング状枠
部５の中央に液状樹脂６Ａが注入されたとしても、この
液状樹脂６Ａは流動性により四方に拡がって行く。そし
て、リング状枠部５に達すると、このリング状枠部５が
形成されたフッ素樹脂の撥水性によりはじかれて、リン
グ状枠部５を越えて拡がるのを阻止されるので、最終的
には液状樹脂６Ａは図４に示すようにリング状枠部５内
で均一の厚さとして層状に保持されるものとなる。By doing so, even if the liquid resin 6A is injected into the center of the ring-shaped frame 5, for example, the liquid resin 6A spreads in all directions due to fluidity. When the ring-shaped frame portion 5 is reached, the ring-shaped frame portion 5 is repelled by the water repellency of the formed fluororesin, and is prevented from spreading beyond the ring-shaped frame portion 5. As shown in FIG. 4, the liquid resin 6A is held in a layered manner in the ring-shaped frame portion 5 with a uniform thickness.
【００１２】この状態で、例えば加熱処理など硬化処理
を行えば、前記液状樹脂６Ａは均一な厚さを保った状態
で硬化するものとなり、即ち、目的とする機能、寸法を
有する封止層６が得られるものと成るのである。尚、言
うまでもないが、封止層６の厚さＴはリング状枠部５内
に注入する液状樹脂６Ａの量（容積、重量）により定ま
るので、所望の厚さＴと成るように注入装置１０などを
調整すれば良い。If a curing treatment such as a heat treatment is performed in this state, the liquid resin 6A will be cured while maintaining a uniform thickness, that is, the sealing layer 6 having the desired functions and dimensions. Is obtained. Needless to say, since the thickness T of the sealing layer 6 is determined by the amount (volume and weight) of the liquid resin 6A to be injected into the ring-shaped frame portion 5, the injection device 10 has a desired thickness T. You just have to adjust the settings.
【００１３】尚、ここで、前記リング状枠部５について
説明を行うと、このリング状枠部５は前記液状樹脂６Ａ
を注入し、それが硬化するまでの間だけ撥水性により液
状樹脂６Ａの流失を防げば良く、それ以後は消失しても
支障を生じることはないものであるので、耐久性などを
考慮する必要はなく、例えば平面基板２に対する付着強
度などはそれ程に必要とされないものである。Here, the ring-shaped frame 5 will be described. The ring-shaped frame 5 is formed of the liquid resin 6A.
It is only necessary to prevent the liquid resin 6A from flowing out by water repellency until it is hardened, and there is no problem even if it disappears thereafter. However, for example, the adhesion strength to the flat substrate 2 is not so required.
【００１４】従って、前記平面基板２が例えばガラス部
材など、塗料、接着剤などに対する密着性が少ない部材
で形成されている場合であっても、容易に実施すること
が可能である。また、前記リング状枠部５は印刷手段な
どで簡便に形成できるので、形成するための素材費など
は僅少であり、また、形成のための金型費用なども僅少
である。Therefore, even when the flat substrate 2 is formed of a member having low adhesion to a paint, an adhesive or the like, such as a glass member, it can be easily implemented. Further, since the ring-shaped frame portion 5 can be easily formed by a printing means or the like, the material cost for forming the ring frame portion 5 is small, and the mold cost for forming the ring frame portion 5 is also small.
【００１５】次いで、上記の製造方法とすることの作用
および効果について説明を行う。本発明により印刷手段
などにより形成したリング状枠部５で液状樹脂６Ａの平
面基板２上での保持を可能としたことで、従来例では必
要とされた型枠が不要となり部品点数の低減が可能とな
ると共に、型枠の平面基板２への取付けのための工数も
不要となる。Next, the operation and effect of the above-described manufacturing method will be described. According to the present invention, the liquid resin 6A can be held on the flat substrate 2 by the ring-shaped frame portion 5 formed by the printing means or the like, so that the mold required in the conventional example becomes unnecessary and the number of parts can be reduced. It becomes possible, and the man-hour for attaching the mold to the flat board 2 is not required.
【００１６】従って、前記した型枠を取付ける際に、既
に平面基板２にはＬＥＤチップ３のダイボンドおよび金
線４によるワイヤーボンドが行われていることで生じ
る、例えば金線４への接触などによる断線事故などは、
完全に排除されるものとなり、分留まりの向上も可能と
なる。Therefore, when the above-mentioned mold is mounted, the die bonding of the LED chip 3 and the wire bonding by the gold wire 4 are already performed on the flat substrate 2. In case of disconnection accident,
It is completely eliminated, and the yield can be improved.
【００１７】[0017]
【発明の効果】以上に説明したように本発明により、封
止層は、平面基板上に封止層を形成するべき範囲の内法
を有する枠状にフッ素樹脂によるリング状枠部を形成
し、このリング状枠部内に液状の透明樹脂の適量を注入
し固化させて形成するＬＥＤ表示器の製造方法としたこ
とで、第一には、従来は液状樹脂が硬化するまでの間、
液状樹脂を保持するためだけの目的で用いられる型枠を
不要とし、部品点数を低減すると共に組立工数も低減し
ＬＥＤ表示器のコストダウンに極めて優れた効果を奏す
るものである。As described above, according to the present invention, the sealing layer is formed by forming a ring-shaped frame portion made of a fluororesin into a frame shape having a method within a range where the sealing layer is to be formed on the flat substrate. By injecting an appropriate amount of a liquid transparent resin into the ring-shaped frame portion and solidifying it to form an LED display, firstly, conventionally, until the liquid resin is cured,
This eliminates the need for a mold used only for holding the liquid resin, reduces the number of parts and the number of assembly steps, and is extremely effective in reducing the cost of the LED display.
【００１８】また、第二には、既にＬＥＤチップ９２の
取付けが行われている平面基板に型枠の取付けを行うこ
とで、例えば不注意の接触などにより金線の切断などを
生じさせる事故の発生を根絶するものとし、これによ
り、工程中に生じる仕損をなくして分留まりの向上にも
優れた効果を奏するものである。Second, by mounting the formwork on the flat substrate on which the LED chip 92 has already been mounted, it is possible to cause an accident such as inadvertent contact or the like to cut a gold wire. The generation is eradicated, thereby eliminating defects caused in the process and improving the yield.
【図１】 本発明に係るＬＥＤ表示器の製造方法の実施
形態のＬＥＤチップの取付工程を示す説明図である。FIG. 1 is an explanatory diagram showing an LED chip mounting process of an embodiment of a method for manufacturing an LED display according to the present invention.
【図２】 同じ実施形態のリング状枠部の形成行程を示
す説明図である。FIG. 2 is an explanatory diagram illustrating a forming process of a ring-shaped frame portion according to the same embodiment.
【図３】 同じ実施形態の液状樹脂の注入行程を示す説
明図である。FIG. 3 is an explanatory view showing a liquid resin injection process of the same embodiment.
【図４】 同じ実施形態の完成状態を示す説明図であ
る。FIG. 4 is an explanatory diagram showing a completed state of the same embodiment.
【図５】 従来の製造方法を示す説明図である。FIG. 5 is an explanatory view showing a conventional manufacturing method.
１……ＬＥＤ表示器 ２……平面基板 ２ａ……配線パターン ３……ＬＥＤチップ ４……金線 ５……リング状枠部 ６……封止層 ６Ａ……液状樹脂 DESCRIPTION OF SYMBOLS 1 ... LED display 2 ... Flat board 2a ... Wiring pattern 3 ... LED chip 4 ... Gold wire 5 ... Ring-shaped frame part 6 ... Sealing layer 6A ... Liquid resin
Claims (1)
し、該ＬＥＤチップを透明樹脂で覆う封止層を形成して
成るＬＥＤ表示器の製造方法において、前記封止層は、
前記平面基板上に前記封止層を形成するべき範囲の内法
を有する枠状にフッ素樹脂によるリング状枠部を形成
し、このリング状枠部内に液状の前記透明樹脂の適量を
注入し固化させて形成することを特徴とするＬＥＤ表示
器の製造方法。1. A method for manufacturing an LED display, comprising: arranging a plurality of LED chips on a flat substrate, and forming a sealing layer covering the LED chips with a transparent resin, wherein the sealing layer comprises:
A ring-shaped frame portion made of a fluororesin is formed on the flat substrate in a frame shape having an inner method within a range where the sealing layer is to be formed, and an appropriate amount of the liquid transparent resin is injected into the ring-shaped frame portion and solidified. A method of manufacturing an LED display, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9101719A JPH10294498A (en) | 1997-04-18 | 1997-04-18 | Manufacture of led display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9101719A JPH10294498A (en) | 1997-04-18 | 1997-04-18 | Manufacture of led display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10294498A true JPH10294498A (en) | 1998-11-04 |
Family
ID=14308121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9101719A Pending JPH10294498A (en) | 1997-04-18 | 1997-04-18 | Manufacture of led display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10294498A (en) |
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