JPH10282523A - Thin-film transistor, liquid crystal display device and production of thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the mask alignment of color filters even when a substrate with which substrate deformation is large is used by forming semiconductor layers along patterns so as not to protrude from the patterns of gate electrodes and insulating films when viewed from above the gate electrodes. SOLUTION: A negative resist is applied on the front surface side of the substrate 10 and source and drain forming regions 14a, 15a and signal line forming regions 14a, etc., intersecting orthogonally with gate lines 11a are exposed by the mask from the front surface side with respect to the substrate 10. As a result, the source and drain forming regions 14a, 15a and the light translucent parts exclusive of the signal line forming regions 14a are exposed. In succession, the parts of an a-Si film 13a are exposed to about half the ordinary exposure from the rear surface of the substrate 10 with the gate lines 11a as a mask. The source and drain forming regions 14a, 15a are superposed on the gate lines 11a at about a half film thickness by developing this resist. In addition, the resist is dissolved at the intersecting parts of the signal line forming regions 14a and the gate lines 11a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device having a color filter.

[0002]

2. Description of the Related Art In recent years, an active matrix type liquid crystal display device in which a thin film transistor (TFT) using an amorphous silicon (a-Si) film or p-Si (polysilicon) is provided as a switching element has attracted attention. A-Si that can be formed at low temperature using an inexpensive amorphous glass substrate
This is because, by forming a TFT array using a film, a reflective display, a large-area, high-definition, high-quality, and inexpensive panel display (flat television) can be realized. By the way, when this kind of display device is used for portable equipment, it is possible to reduce the weight by using plastic for the substrate, but there is a problem that large misalignment is large in a large-area display due to large deformation at both ends. When an active matrix type liquid crystal display device is formed on a substrate such as plastic having large deformation or a large area substrate and a color filter (CF) is formed by pattern matching with these active elements, the substrate deformation is large. Therefore, it is difficult to align a mask with a TFT array for forming a color filter. Further, there is a problem that it is difficult to increase the aperture ratio due to poor alignment accuracy between the color filter and the active element substrate. To this end, it is effective to form the color filters in a self-aligned TFT.

[0003]

The conventional liquid crystal display device has a problem that it is difficult to perform color filter mask alignment when a substrate such as plastic that has large deformation is used. The present invention has been made in view of the above problems, and has as its object to provide a liquid crystal display device capable of performing color filter mask alignment even when a substrate having a large substrate deformation is used.

[0004]

According to another aspect of the present invention, there is provided a thin film transistor comprising: a linear gate electrode formed on a transparent substrate; and a gate insulating film formed on the gate electrode. A thin film transistor comprising: a semiconductor layer; and a source / drain electrode pair formed on the semiconductor layer and in a direction orthogonal to the gate electrode and separated by an insulating film formed on the gate electrode. The semiconductor layer is formed along the gate electrode pattern and the insulating film without protruding from the insulating film when viewed from above the electrode.

According to a second aspect of the present invention, there is provided a liquid crystal display device comprising a gate line formed on a light-transmitting substrate, a gate insulating film formed on the gate line, and a pattern of the gate electrode as viewed from above the gate line. A thin film transistor formed and having a source-drain electrode pair formed on the semiconductor layer and in a direction orthogonal to the gate electrode; and a pixel electrode formed on the light-transmitting substrate and connected to the drain electrode. And an opposing substrate disposed opposite to the translucent substrate and having an opposing electrode formed on a surface on the translucent substrate side,
It is characterized by comprising a counter substrate and a liquid crystal layer formed between the translucent substrates.

According to a third aspect of the present invention, there is provided the liquid crystal display device according to the second aspect, wherein the drain electrode has a groove formed at a connection portion with the pixel electrode. According to a fourth aspect of the invention, in the liquid crystal display device according to the second aspect, a color filter material having electrical conductivity is used as the pixel electrode.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: forming a gate electrode on a light-transmitting substrate; sequentially stacking a gate insulating film, a semiconductor layer, and a metal layer on the gate electrode; Forming a source / drain electrode by separating the metal group layer on a gate electrode, wherein the resist applied on the metal layer is irradiated with light from the back surface of the light-transmitting substrate. A pattern in which only the resist on the gate electrode is exposed and removed by light irradiation from the surface is formed, and the metal layer is etched away from the pattern.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Embodiment 1 will be described with reference to FIGS.
MoT on a glass or plastic transparent substrate 10
a, Cu, Al, Al alloy, MoW, etc. were deposited at 3000 A and etched to form a pattern of a gate line 11a also serving as a gate electrode and a Cs line 11b. Next, SiOx3 is used as the insulating film 12 by the plasma CVD method.
000A and SiNx 500A are sequentially stacked, and a 1000A undoped a-Si film 13a and
A stacked film of the n + a-Si film 13b of 00A was formed, and finally a Mo film (not shown) was deposited at 200A. Other suitable metals other than the Mo film include high melting point metals such as W, Cr, Ta, and Ti having good ohmic properties with the n + a-Si film, alloys mainly containing these metals, and good anodic oxidation properties. A
You may use l, Nb, an alloy mainly including these, and the like. Next, a negative resist is applied to the entire front surface side of the substrate 10, and the source / drain formation regions 14a, 15a and the signal line formation region 14a orthogonal to the gate line 11a (the signal line extends from the source electrode and is integrated). Thus, the substrate 10 is exposed from the front side using a patterned mask. By this first exposure, the light-transmitting portions other than the source / drain formation regions 14a, 15a and the signal line formation region 14a are exposed. Continue with substrate 10
Then, exposure is performed using the gate line 11a as a mask from the back surface, and the portion of the a-Si film 13a is exposed a second time, which is about half of the normal exposure. By the above two exposures, the portion where the gate line 11a and the signal line formation region 14a are orthogonal to each other is not exposed, the source / drain formation regions 14a and 15a are moderately exposed, and the other regions are strongly exposed. .
This exposure step is an important step in this embodiment. By developing this resist, the source / drain formation regions 14a and 15a overlap the gate line 11a with a thickness of about 1/2 and about 1 to 2 μm, and
Since the light does not hit the intersection 14d of the gate line 11a and the resist, the resist dissolves, resulting in a resist pattern without the resist on the gate line 11a. Signal line 14
In order to prevent disconnection of a, the intersection 14d of the gate line 11a / signal line formation region 14a is selectively polymerized by irradiation with ultraviolet light or a laser spot using a mask. Alternatively, the gate line 11a and the signal line formation region 1
In some cases, a slit may be formed in the intersection 14d of 4a, and the gate line 11a may be formed by a plurality of lines having a width equal to or less than the width of light by Fresnel diffraction, and the resist at the intersection may be exposed. Therefore, the signal line forming region 14a on the gate line 11a is covered with the resist. As a result, after the resist is removed, the n + a-Si film 13b is left in the orthogonal portion between the gate line 11a and the signal line forming region 14a.
The upper Mo film is exposed, and the source / drain formation region 14 is exposed.
The remaining film thickness of the resist 17b on the resists 15a and 15a can be reduced to about 1/2 of that of the resist 17a in other regions. Next, after selectively removing Mo exposed at the orthogonal portion, the SiO 2 film 16 is formed by anodizing the n + a-Si film 13b with a 0.1% citric acid solution. Alternatively, in forming the SiOx film 16, the n + a-Si film 13b in the channel portion may be etched by dry etching or CDE of CF4 / O2 before anodic oxidation, and then anodized (FIG. 1).
(A), FIG. 2 (a)). Here, FIG. 2A omits the substrate insulating film and the like, and shows only the wires and electrodes. The same applies to the following plan views, in which only the wirings / electrodes and the portions formed therearound in a self-aligned manner are drawn. Next, the thickness of the resist on the entire surface is reduced to about 1/2 by additional development or ashing.
Then, the resist 17b in the source and signal line formation region 14a is removed to expose the n + a-Si film 13b (FIG. 1B). Then, resist or anodic oxide film Si
The signal line 14c is formed by plating a single-layer or laminated metal such as Cr, Ni, or Cu on a region not covered with Ox16. Here, since the signal lines are the same wirings extending from the drain electrode 14c, the same numbers are given. Plating is Ti
Electroless plating may be performed after performing such surface treatments as described above, or electroplating may be performed by establishing continuity from the end portion of the stacked film of the n + a-Si film 13b and the Mo film (FIG. 1).
(C), FIG. 2 (a)). Then, after the resist 17c is peeled off, the plated metal 14c, 15c, which is the source / drain electrode, and the anodic oxide film 16 are used as a mask to form n
The + a-Si film 13b and the a-Si film 13a are etched by CDE or RIE. Anodization of the channel portion is performed by forming a negative resist on the entire surface, exposing and developing through the a-Si film 13a, removing the resist only on the gate line 11a, and removing the a-Si film 13 corresponding to the gate line 11a.
The surface of a may be anodized. As described above, a self-aligned TFT in which the semiconductor film exists only under the source / drain electrodes 14c and 15c is formed. Of course, since this TFT is used for a pixel electrode switch of a liquid crystal display device, it is formed in an array over the entire surface of the substrate 10, so that an array substrate is formed by the above steps. In some cases, a passivation film may be formed thereover using a material such as SiNx (FIG. 1D). Next, a photosensitive dyeable organic film 17e such as a positive polyvinyl alcohol is coated to a thickness of 1 to 5 μm, preferably 2 to 4 μm. A positive photosensitive group is provided to make the composition positive photosensitive. Exposure from the back surface exposes portions other than the non-light-transmitting portions such as the signal lines 14c and the gate lines 11a. And will remain. Therefore, at this point, the drain electrode 15c
Is partially exposed. The portion of the Cs line 11b is exposed by overlapping exposure. Next, by heating to generate a pattern droop, the drain electrode 15c is deformed so as to cover a part of the drain electrode 15c which is exposed. This deformation process is shown in FIG.
FIG. 5 is an enlarged view showing in detail the connection state between the drain electrode 15c indicated by L in FIG. FIG. 5 (c) is an enlarged view of L, and FIGS. 2 (a) and 2 (b) are cross sections AA and BB, respectively, showing the state immediately after development of the resist and before heating. FIG. 2 (d), FIG.
(E) and FIG. 2 (f) correspond to FIG. 2 (a) and FIG.
FIG. 2B shows the resist deformed state after heating in FIG. In this case, 50 is a passivation film, and 18B is a red pixel electrode of a conductive organic film described later. Using the resist 17e as a mask, a passivation film such as SiN
The x film 50 is etched. Further, the contact portion with the pixel electrode may be subjected to overlapping exposure using another mask to remove the organic film. Thereafter, the resist film on which the pattern is formed is colored. This resist is immersed in a reactive dye in which red, blue and green dyes are mixed and dyed black to obtain a black resist 1
7e. The thickness of the black dyed film and the concentration of the dye are adjusted so that the transmittance of light in the visible region is 5 to 0.01%, usually 1 to 0.1% or less. Next, baking is performed at 100 to 200 C to stabilize the organic film 17 (FIG. 1E, FIG.
b)). Next, apply 3 red pigments to the acrylic negative resist.
The red color filter 18R is formed by mixing 0 to 50% by weight, scattering and printing on the pixel at a predetermined location by, for example, a bubble jet. Next, the blue pigment-dispersed resin is scattered to form a blue color filter 18B, and the green pigment-dispersed resin is scattered to form a green color filter 18G (FIGS. 1F and 2C). This color filter 18R,
18G, 18B pigments include ITO, SnO2, SbO
The conductivity is increased by mixing a filler of transparent conductive particles such as x. The resistivity may be 10E5 to 10E7 Ωcm. The thickness of the pigment may be about the same as or slightly thinner than the black organic film bank 17e. Alternatively, it may be formed higher than the bank and polished last. In the case of polishing, in order to increase the hardness of the black matrix 17e, a material having a high hardness such as carbon, a metal, or a metal compound may be mixed to the extent that the conductivity does not become too low.
It is also effective to flatten the printed CF on the surface of the substrate by pressing the surface with a flat plate of glass or the like after printing. Through the above steps, a TFT array substrate integrated with a color filter is completed. In this array substrate, source / drain electrodes are formed in a self-aligned manner under signal lines and gate lines, and a mask is used in a gate line forming step, a gate line contact forming step around a pixel, and a source / drain electrode forming step. With three sheets, the formation process can be simplified. Although the subsequent steps are not specifically shown, an opposing writing plate having an opposing electrode formed on the surface opposing the array substrate is disposed on the array substrate, and a liquid crystal layer is sandwiched between the opposing writing plate and the array substrate. To complete the liquid crystal display device. Since the manufacturing process requires only three masks, this liquid crystal display device can provide a concept excellent in mass production. Conventionally, the alignment accuracy between the wiring of the array substrate and the mask of the color filter required a margin of 5 to 10 μm for the alignment accuracy between the array substrate and the counter substrate and about 3 to 5 μm for the mask alignment accuracy.
In the present invention, since the deformation due to heating of the resist can be controlled to 1 to 3 μm, the aperture ratio can be sufficiently increased. In addition, the contact between the pixel and the TFT was self-aligned without any alignment. In addition, the pixel electrode and the wiring are aligned in a self-aligned manner, and the aperture ratio can be improved.

(Embodiment 2) Next, Embodiment 2 will be described with reference to FIGS.
It is explained along. This embodiment is different from the first embodiment in that a Cs line is not provided independently but also serves as a gate line. Therefore, a description will be given focusing on a manufacturing process different from that of the first embodiment. MoTa, Cu, A on plastic substrate 10
An alloy, MoW or the like was deposited at 3000 A and etched to form a pattern of the gate line 11a. The material of the gate line 11a may be any metal as long as it has good adhesion to the gate insulating film, but a material having a high reflectance is more preferable. In particular, Ag, Al, Cr,
Cu, Mo, Ta, Nb, and Au are particularly good. Next, SiOx3000 is used as the insulating film 12 by the plasma CVD method.
A, a stack of SiNx500A, undoped a-Si1
3A at 1000A, n + a-Si13b at 500A,
Mo (not shown) was deposited at 500A. Next, Mo / n + a-Si / a-Si / SiNx / Si of the contact portion
Ox was etched to form a contact hole 30.
Further, a signal wiring metal such as Al, Cr, or Mo was sputtered on the entire surface to form the wiring 14 serving as the source / drain electrodes 14c and 15c. Next, a resist was applied to the surface of the substrate 10. Thereafter, a resist 37a was formed through exposure and development steps so as to leave a pattern on the source / drain formation region. Thereafter, the signal wiring metal and the gate insulating film are etched using the resist 37a as a mask, and the semiconductor layer is dry-etched with CF4 / O2 to form an island region of the semiconductor layer. The resist may be positive or negative. FIG. 4A omits the insulating film 14 (FIG. 3).
(A), FIG. 4 (a)). Next, the substrate 10 was heated from the back with a xenon lamp. The gate line portion reflects light, and a-S
Since metals such as i and W have low reflectivity in the visible to infrared regions, they absorb light and are heated, so that the resist 37c in the portion with a gate does not change, but the portion without a gate becomes hotter and the resist polymerizes. Since the film 37b is formed, the resist at the intersection of the gate line and the signal line can be dissolved by developing again (FIGS. 3B and 4B). Using this resist pattern as a mask, the signal line metal of the TFT channel portion, n + a-Si, is etched to obtain
T is completed. The Mo film on the n + a-Si film 13b may be formed after the formation of the contact hole 30.

By forming a TFT in this manner,
In addition to the same effects as in the first embodiment, a TFT having a well-matched source / drain and gate can be formed even when a plastic substrate having large thermal deformation is used, and a TFT array having uniform characteristics in the substrate surface is formed. did it. For this reason LCD
Had a uniform image quality, and a good screen was realized.

As the gate line 11a, visible light (550
Ag), which has a high reflectance in infrared rays (1 μm).
914, 0.987), Al (0.924, 0.970), Cr (0.698, 0.639)
, Cu (0.577, 0.976), Mo (0.582, 0.805), Ta (0.
395,0.992), Nb (0.511,0.875), Au (0.331,0.992)
Is preferred. As a metal on a-Si, Si (0.364, 0.316) and W (0.480,
0.649) and Ti (0.462, 0.570) are preferred. The difference in reflectance between the gate line material and the semiconductor, for example, a-Si may be 30% or more. The gate line material and a semiconductor such as aS
It is effective to heat with light having a wavelength having a large reflectance difference of i. Further, in the case of a continuous light source, the temperature of the non-irradiated portion of the light source for heating from the back surface tends to increase due to thermal diffusion. Therefore, heating with a pulse light source is effective in further expanding the temperature difference. For a normal resist, preferably a novolak-based resist, the resist on the gate line can be selectively developed and removed by setting the temperature difference between the heated part and the non-heated part to 40C or more. The light source may be any wavelength as long as it transmits through the substrate. In particular, in the case of glass, a wavelength from near ultraviolet to near infrared can be used. A continuous wave may be used, but a pulse is more preferable to limit heat conduction. The pulse width is preferably narrow, and is preferably several microseconds to several milliseconds.

(Embodiment 3) This embodiment differs from Embodiment 1 in that a protective film 21 covering the entire surface of the substrate is formed in the final step. It is also effective to flatten the surface of the conductive pigment with a squeegee and form an alignment pattern of liquid crystal on the surface of the protective film 21 at the same time. These pigments include IT
The conductivity is increased by mixing a filler of transparent conductive particles such as O, SnO2, and SbOx. Resistivity is 10E5Ωcm
To 10E7 Ωcm. The thickness of the pigment may be the same as or slightly thinner than the black organic bank. Alternatively, it may be formed higher than the bank and polished last. In the case of polishing, in order to increase the hardness of the black matrix portion, a material having a high hardness such as carbon, a metal or a metal compound may be mixed to such an extent that the conductivity does not become too low. The printing method is not limited to the transfer method, but may be another method.
Further, the surface protection layer 21 may be formed as needed. By forming the TFT in this manner, in addition to the same effect as in the first embodiment, a TFT-LCD in which the array substrate and the color filter are well matched even when using a plastic substrate having large thermal deformation can be formed. A TFT-LCD having a large aperture ratio could be formed in a small number of steps. Therefore LC
The image quality of D was also uniform, and a good screen was realized. Thus, a TFT array and an LCD array are completed.

Next, a high-resolution TFT-LC having a diagonal of 40 inches
This technology was applied to D. Although a plastic substrate was used in the first embodiment, a glass substrate was used in this embodiment. Since glass has a coefficient of thermal expansion of 5E-5, a change of 3 ° C. causes a thermal deformation of 130 μm or more, so that the glass cannot be combined by a normal photolithography process. On the other hand, by the manufacturing method using the back surface exposure and the printing of the color filter according to the present invention, it was possible to almost completely perform self-alignment alignment.

The structure of the TFT array is not limited to this embodiment, and may be any of a normal back channel type in which n + a-Si is etched using a signal line as a mask, or a stopper type in which an etching stopper is provided in a channel portion. Instead of a-Si, polysilicon (p-Si), CdSe, or the like may be used for the semiconductor material. The thickness of each film may be appropriately changed.

[0015]

As described above, the method of forming the black BM and the color filter according to the present invention can be applied to a substrate, such as a plastic substrate or a large substrate, for which mask alignment is difficult by ordinary photolithography. Good matching can be achieved, TFT characteristics in the substrate can be formed uniformly, and image quality can be made uniform.

[Brief description of the drawings]

FIG. 1 is a sectional view of an active matrix type array substrate according to a first embodiment of the present invention.

FIG. 2 is a plan view of the active matrix type array substrate according to the first embodiment of the present invention.

FIG. 3 is a sectional view of an active matrix array substrate according to a second embodiment of the present invention.

FIG. 4 is a plan view of an active matrix type array substrate according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a color filter formed by thermal deformation of an organic film by heating according to the first embodiment of the present invention.

FIG. 6 is a sectional view of an active matrix array substrate according to a third embodiment of the present invention.

[Explanation of symbols]

 10 Substrate 11a Gate line 11b Storage capacitance line 12 Gate insulating film 13a a-Si 13b n + a-Si 14c Source electrode 15c Drain electrode 16 Anodized film 17e …………………………………………………………………………………………?

Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 29/78 616S 617J 618C

Claims (5)

[Claims] 1. A linear gate electrode formed on a light-transmitting substrate, a gate insulating film and a semiconductor layer formed on the gate electrode, and in a direction orthogonal to the gate electrode on the semiconductor layer. And a thin film transistor comprising a source / drain electrode pair separated by an insulating film formed on the gate electrode, wherein the semiconductor layer is formed from the pattern of the gate electrode and the insulating film when viewed from above the gate electrode. A thin film transistor formed along without protruding. A gate line formed on the light-transmitting substrate; a gate insulating film formed on the gate line; and a semiconductor layer formed along the pattern of the gate electrode as viewed from above the gate line. A thin film transistor having a source / drain electrode pair formed thereon and in a direction orthogonal to the gate electrode; a pixel electrode formed on the light transmitting substrate and connected to the drain electrode; And a liquid crystal layer formed between the counter substrate and the light-transmitting substrate. Liquid crystal display device. 3. The liquid crystal display device according to claim 2, wherein the drain electrode has a groove formed at a connection portion with the pixel electrode. 4. The liquid crystal display device according to claim 2, wherein a color filter material having electrical conductivity is used as the pixel electrode. 5. A step of forming a gate electrode on a light-transmitting substrate, a step of sequentially stacking a gate insulating film, a semiconductor layer, and a metal layer on the gate electrode; And forming a source / drain electrode by separating the resist applied to the metal layer by applying light from the back surface of the light-transmitting substrate and light irradiation from the front surface of the gate. A method for manufacturing a thin film transistor, comprising: forming a pattern in which only the resist on an electrode is exposed and removed, and etching and removing the metal layer from the pattern.