JPH10256914A - D/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D/A converter hardly causing overshoot in the analog output while suppressing the power consumption. SOLUTION: This converter is provided with a constant current source 1, switch circuits SW1 and SW2, a switch circuit SW3 connected between the constant current source 1 and the switch circuit SW1, an output resistance 2, a dummy resistor 3, and a control circuit 4, and each switch is switched and controlled by a control signal from the control circuit 4. The switch circuit SW1 is repeatedly turned on and off in accordance with a digital signal, and the switch circuit SW2 is switched at timings approximately opposite to those of the switch circuit SW1. The switch circuit SW3 is turned on only for a prescribed time which starts before turning-on of the switch circuit SW1 and ends after turning-off of the circuit SW1. Thus, a current flows to the dummy resistor 3 only for a prescribed time just before turning-on of the switch circuit SW1 and for a prescribed time just after turning-off of the circuit SW1, and the time when the current flows to the dummy resistance is shortened to reduce the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current addition type D / A
The present invention relates to a converter, particularly a converter having a constant current source and a switch circuit in an output stage.

[0002]

2. Description of the Related Art In a DVD (Digital Video Disk) device or the like, a process of converting a digital signal recorded on a medium into an analog video signal is performed. A D / A converter is usually used for such a process. Can be There are a plurality of types of D / A converters having different circuit configurations. FIG. 7 shows a circuit configuration of an output stage of a current addition type D / A converter, which is one of the types. FIG. 8 is a signal waveform diagram of nodes P to S in FIG.

[0003] The D / A converter shown in FIG.
0, an output resistor 2 and a dummy resistor 3. Each unit 10 includes a constant current source 1 and switch circuits SW1 and SW2 connected to the constant current source 1, and the unit 10 having such a configuration has a predetermined number of bits (for example, 8 bits).
(For bits) are connected in parallel.

The switch circuit SW1 repeatedly turns on and off according to the digital signal to be converted, and the switch circuit SW2 operates at a timing substantially opposite to that of the switch circuit SW1. The switch circuit SW2 is provided to prevent overshoot and undershoot, and can convert a digital signal into an analog signal without the switch circuit SW2. When the switch circuit SW2 is omitted, the circuit is omitted. As shown in FIG.

FIG. 10 is a signal waveform diagram of nodes P, Q, and R in FIG. 9. The operation of the circuit in FIG. 9 will be described with reference to FIG. When the switch circuit SW1 is turned on, a current I ₀ from the constant current source 1 flows to the output resistor 2 through the switch circuits SW1, an analog signal potential (hereinafter, referred to as analog output) I ₀ · R (R is the output Resistance value of the resistor 2).

On the other hand, when the switch circuit SW1 is turned off,
The potential of the connection point Q between the constant current source 1 and the switch circuit SW1 rises to a level close to the power supply voltage VDD, and when the switch circuit SW1 is turned on in that state, a predetermined period until the potential of the connection point Q decreases is obtained. A current larger than the current that should originally flow from the constant current source 1 flows to the connection point Q, and is output to the analog output as shown in FIG.
Overshoot like the waveform R of FIG.

For this reason, in the circuit of FIG. 7, a dummy circuit composed of a switch circuit SW2 and a dummy resistor 3 is provided, and the switch circuit S1 is turned off while the switch circuit SW1 is off.
W2 is turned on and the current from the constant current source 1 is
And the potential of the connection point Q is set to a value close to the output voltage.

[0008]

However, in the circuit of FIG. 7, as can be seen from the waveforms R and S of FIG. 8, the switch circuits SW1 and SW2 are turned on alternately and the switch circuit SW1 is turned off. Since the current from the constant current source 1 flows through the switch circuit SW2, power consumption increases.
That is, the current flowing through the switch circuit SW2 is D / A
Since it does not directly contribute to the conversion, the power consumption used for conversion to analog signals is only 50% of the total power consumption,
A lot of power is wasted.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce the power consumption and to achieve a D / A that does not cause overshoot in the analog output.
It is to provide a converter.

[0010]

According to a first aspect of the present invention, there is provided a current adding type D / A converter in which a current from a constant current source flows through an output resistor to obtain an analog output. A dummy resistor through which a current from the constant current source flows, and a series connection to the output resistor, and switching whether to flow the current from the constant current source to the output resistor based on a first switch control signal. A first switch circuit;
A second switch circuit that is connected in series with the dummy resistor and that switches whether or not a current from the constant current source flows through the dummy resistor based on a second switch control signal; and A switch control circuit that outputs first and second switch control signals, wherein a current from the constant current source flows through the dummy resistor within a predetermined period immediately before the first switch circuit switches from off to on. And a switch control circuit for controlling the switching of the second switch circuit.

The first switch circuit corresponds to the switch circuit SW1, the second switch circuit corresponds to the switch circuit SW2, and the switch control circuit corresponds to the control circuit 4, respectively. I do.

According to a second aspect of the invention, there is provided a third switch circuit connected between the constant current source and the second switch circuit, the third switch circuit being controlled to be switched based on a third switch control signal, The switch control circuit is configured to turn on the third switch circuit at a time earlier by a first period than the time at which the first switch circuit is turned on, and to perform the second period at a time earlier than the time when the first switch circuit is turned off. The third switch control signal is output so that the third switch circuit is turned off at a later time, and the first and second switch circuits are turned on and off at substantially opposite timings. The first and second switch control signals are output.

The invention of claim 2 will be described with reference to FIGS. 1 and 2. The third switch circuit is a switch circuit S
In response to W3, as shown in waveforms A and B of FIG. 2, the third switch circuit SW3 is set to be on for a predetermined period from immediately before the first switch circuit SW1 is turned on to immediately after it is turned off. You.

According to a third aspect of the present invention, in the switch control circuit, the second switch circuit is turned on and the first switch circuit is turned on at a predetermined time earlier than the time when the first switch circuit is turned on. The first and second control signals are output so that the second switch circuit is turned off at substantially the same time as the time.

The invention according to claim 3 is based on, for example, the waveforms A,
As shown in H, the second switch circuit is turned on only for a predetermined period immediately before the first switch circuit is turned on.

According to a fourth aspect of the present invention, the digital signal includes:
An arithmetic unit that performs a predetermined logical operation based on the digital signal delayed for a predetermined period, and the switch control circuit uses the signal obtained by delaying the digital signal for a predetermined period as the first switch control signal. , The output of the arithmetic unit is used as the second switch control signal.

The invention according to claim 4 will be described with reference to FIG. 3. An arithmetic unit corresponds to an AND gate 43, and a signal obtained by delaying a digital signal for a predetermined period is supplied to a delay circuit 41 or 42.
Corresponding to the output of

According to a fifth aspect of the present invention, there is provided a current addition type D / A in which a current from a constant current source flows through an output resistor to obtain an analog output.
In the converter, a first switch circuit connected in series to the output resistor to switch whether or not a current from the constant current source flows to the output resistor;
And a second switch circuit connected between the constant current source and the first switch circuit when the first switch circuit is off. A switch control circuit for controlling switching of the second switch circuit, and a potential between the constant current source and the first switch circuit becoming a predetermined potential immediately before the first switch circuit is turned on. A feedback circuit that feeds back the analog output between the constant current source and the first switch circuit.

Referring to FIG. 5, the first switch circuit is connected to the switch circuit SW1, the second switch circuit is connected to the switch circuit SW4, the switch control circuit is connected to the control circuit 4b, and the feedback is performed. The circuits correspond to the feedback amplifier 5 and the switch circuit SW2, respectively.

According to a sixth aspect of the present invention, the feedback circuit has one end connected to the first and second switch circuits and the other end connected to the output resistor, and is controlled to be switched based on a third switch control signal. A third switch circuit, wherein the switch control circuit is configured to turn on the third switch circuit at a time earlier by a first period than a time when the first switch circuit is turned on, and Outputs the third switch control signal so that the third switch circuit is turned off at a time later by a second period than the time when the first switch circuit is turned off, and the first and second switch circuits are substantially opposite in time. The first and second switch control signals are output so as to be turned on and off at the timing.

Referring to FIG. 5, the third switch circuit corresponds to the switch circuit SW2.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a D / A converter to which the present invention is applied will be specifically described with reference to the drawings.

[First Embodiment] In a first embodiment described below, a switch circuit SW3 is newly added to the conventional D / A converter shown in FIG. Dummy resistor 3 only for a predetermined period immediately before turning on
To control the switching of each of the switch circuits SW1 to SW3 so that a current flows through the switch circuits SW1 to SW3.

FIG. 1 is a circuit diagram showing the configuration of the output stage of the D / A converter according to the first embodiment. The circuit diagram of FIG. 1 shows a unit 10a for one bit, and a plurality of such units 10a are actually connected in parallel. In addition,
In FIG. 1, the same components as those in the related art are denoted by the same reference numerals.

Each unit 10a is composed of a conventional D shown in FIG.
/ A converter, constant current source 1 and switch circuit SW
1, a switch 2, an output resistor 2, a dummy resistor 3, and a control circuit 4. A switch circuit SW3 is connected between the constant current source 1 and the switch circuit SW2, and the switch circuit S
A dummy circuit is formed by W2, the switch circuit SW3, and the dummy resistor 3. These switch circuits SW1 to SW1
SW3 is controlled by the control circuit 4. More specifically, the switch circuit SW1 is controlled by the first switch control signal output from the control circuit 4, the switch circuit SW2 is controlled by the second switch control signal, and the third switch is controlled by the third switch control signal. Each of the switch circuits SW3 is controlled to be switched by a control signal. Further, the control circuit 4 includes a control signal generation unit 40 composed of a combination of logic gates and an inverter 41.

FIG. 2 is a signal waveform diagram of nodes A to E in FIG. 1. The circuit operation of FIG. 1 will be described with reference to FIG.

The digital signal input to the control circuit 4 is
The signal is delayed by a predetermined period τ ₁ in the control circuit 4 and output as a first switch control signal (waveform A in FIG. 2), and the switching of the switch circuit SW 1 is controlled by this signal.
The switching of the switch circuit SW2 is controlled at a timing substantially opposite to that of the switch circuit SW1.

On the other hand, the control circuit 4 changes to the high level a predetermined period τ ₁ before the time when the first switch control signal changes to the high level, and after the first switch control signal changes to the low level. A third switch control signal that changes to a low level after a predetermined period τ ₂ is output to the node B. The switching of the switch circuit SW3 is controlled by the third switch control signal.

If the third switch control signal (node B) changes to a high level at time T ₁ shown in FIG. 2, the switch circuit SW 3 changes to ON accordingly,
Current from the constant current source 1 flows to the dummy resistor 3 via the switching circuit SW3 and SW2, the potential of the connection point C of the constant current source 1 and the switch circuit SW1 is reduced to I ₀ · R.
Here, I ₀ is a current flowing from the constant current source 1, and R is a resistance value of the dummy resistor 3.

[0030] From time T ₁ at time T ₂ of the predetermined period after tau _1, the logic of the first switch control signal (node A) is changed to the high level, the switch circuit SW1 is turned on, the switch circuit SW2 is turned off Changes to As a result, the current from the constant current source 1 flows to the output resistor 2 via the switch circuit SW1, and the analog output changes to a high level.

[0031] Thereafter, the digital signal goes down to the low level, the first switch control signal (node A) is changed to the low level at time T ₃ in response thereto, the switch circuit SW1 is turned off, the switch circuit SW2 is turned on Changes to
The analog output changes to low level. Comes from time T ₃ to time T ₄ after the predetermined period of time tau _2, a third switch control signal (node B) the switch circuit SW3 is turned off changes to the low level, accordingly, the potential of the connection point C Gradually rise.

[0032] Thereafter, the digital signal is changed to the high level again at time T _5, a predetermined period of time tau ₁ from that point to the first switch control signal (node A) is changed to the high level, the dummy resistor 3 Current flows again.

As described above, the current from the constant current source 1 flows through the dummy resistor 3 when the switch circuits SW2 and SW3 are both on. Specifically, the switch circuit S
A predetermined period τ ₁ immediately before W1 is turned on, and a switch circuit S
This is only the predetermined period τ ₂ immediately after W1 is turned off. Therefore, the potential at one end of the dummy resistor 3 (hereinafter, referred to as a dummy output) is as shown by a waveform E in FIG.

In the D / A converter shown in FIG.
When W1 is turned off, the potential of the connection point C between the constant current source 1 and the switch circuit SW1 rises almost to the power supply voltage VDD, but the switch circuit SW3 is turned on just before the switch circuit SW1 is turned on. Since the current from the constant current source 1 flows through the dummy resistor 3, the potential at the connection point C is substantially equal to I
_It decreases to ₀ · R.

[0035] The switch circuit SW1 to switch from on to off the switch circuit SW3 from off after a predetermined period of time tau ₂ is for the purpose of ensuring the hold time of the digital signal, thereby, somewhat into a digital signal Can be converted to an analog signal with high accuracy even if the waveform is distorted.

The power consumption P ₀ of the D / A converter of FIG. 1 is expressed by the following equation (1). P ₀ = R ・ (I ₀ ² · t ₀ + I _dum ² · t _dum ) / T (1) where R is the resistance value of the output resistor 2 and the dummy resistor 3,
I ₀ is the current flowing through the output resistor 2 when the switch circuit SW1 is on, I _dum is the current flowing through the dummy resistor 3 when the dummy circuit is operating, and t ₀ is the switch circuit SW1
Is on, t _dum is the operation period of the dummy circuit, and T is the period of the digital signal.

The power P ₀ of the conventional D / A converter shown in FIG. 7, I ₀ = I _dum, since it is _{t 0 = t du m = T} / 2, P 0 = R · I 0 2 In the present embodiment, a predetermined period τ immediately before the switch circuit SW1 is turned on.
For flow _1, a current in a predetermined time period tau ₂ only dummy resistor 3 immediately after the switch circuit SW1 is turned off, the conventional D /
The operation time of the dummy circuit can be shortened as compared with the A converter, and t
_dum << t ₀ can be set. Therefore, in Expression (1), I _dum · t _dum << I ₀ · t _{0 holds} , and the conventional D
The power consumption can be greatly reduced as compared with the / A converter. Further, the D / A converter of the first embodiment has a configuration in which only the switch circuit SW3 and the control circuit 4 are added to the conventional circuit shown in FIG. 7, so that the design can be easily changed from the conventional circuit.

It should be noted that how long the predetermined periods τ ₁ and τ ₂ shown in FIG. 2 are specifically set depends on the semiconductor process, the structure of the transistor on the semiconductor substrate, and the like. As we improve, τ ₁ and τ
₂ can be set shorter.

[Second Embodiment] The second embodiment has basically the same configuration as the conventional D / A converter shown in FIG. 7, and the switching timing of the switch circuit SW2 is different from the conventional one.

FIG. 3 is a circuit diagram showing the configuration of the output stage of the D / A converter according to the second embodiment, and shows a unit for one bit as in FIG. Switch circuits SW1 and SW
2 is connected to the constant current source 1 in the same manner as the conventional configuration shown in FIG. 7, but the switching timing of the switch circuit SW2 is different from the conventional one.

The control circuit 4a includes delay circuits 41 and 42,
The switch circuit SW1 is composed of an AND gate 43 and an inverter 44. The switch circuit SW1 is switched and controlled by a first control signal output from the delay circuit 41.
2 is switched and controlled by a second control signal output from the AND gate 43.

FIG. 4 is a signal waveform diagram of each part of FIG. The delay circuit 4a outputs a first switch control signal (waveform A in FIG. 4) obtained by delaying the input digital signal (waveform F in FIG. 4) by a predetermined time τ, and switches the switch circuit SW1 in response to this signal. Are switched. The signal (waveform G in FIG. 4) passed through the inverter 44 and the delay circuit 42 and the digital signal D are added by an AND gate 43, and the switch circuit SW2 switches according to the gate output (waveform H in FIG. 4). Controlled.

As described above, in the D / A converter according to the second embodiment, the switch circuit SW2 is first turned on before the switch circuit SW1 is turned on. Therefore, when the switch circuit SW1 is turned on, the constant current source 1 The potential at the connection point C between the switch and the switch circuit SW1 is reduced to I ₀ · R which is the product of the current I ₀ from the constant current source 1 and the resistance value R of the dummy resistor 3,
Overshoot does not occur. Further, since the switch circuit SW2 is turned on for a predetermined period τ immediately before the switch circuit SW1 is turned on, the period during which the current flows through the dummy resistor 3 can be shortened similarly to the first embodiment, and the power consumption can be reduced. Further, the D / A converter of the second embodiment can use the conventional circuit as it is, so that the design can be easily changed and the design cost can be reduced.

Since the switch circuit SW1 is turned on / off based on the first switch control signal obtained by delaying the digital signal by the delay circuit 41, it takes a long time until an analog signal is obtained. . But,
Normally, a low-pass filter (not shown) for reducing noise is connected to the subsequent stage of the D / A converter. Considering the delay time caused by passing through the low-pass filter, D
The delay time in the / A converter is negligibly small.

[Third Embodiment] Although the D / A converters of the first and second embodiments include a dummy circuit having the same configuration as that of the conventional D / A converter, the D / A converter of the third embodiment described below will be described. D /
The A converter includes a dummy circuit having a configuration different from that of the related art. The dummy circuit according to the third embodiment does not include a dummy resistor, and one end of the dummy circuit is connected to the output resistor 2. Further, the dummy circuit functions as a feedback circuit for feeding back the analog signal.

FIG. 5 is a circuit diagram of the output stage of the D / A converter according to the third embodiment, and shows the configuration of a 2-bit unit 10c. The dummy circuit according to the third embodiment includes a switch circuit SW2 connected in parallel to the switch circuit SW1.
And a feedback amplifier 5 connected between the switch circuit SW2 and the output resistor 2, and the dummy resistor 3 as shown in FIGS. 1 and 3 is not provided. Also, a switch circuit S is provided between the switch circuit SW1 and the constant current source 1.
W4 is connected.

In the first and second embodiments, the occurrence of overshoot is suppressed by lowering the potential of the connection point C between the constant current source 1 and the switch circuit SW1 when the switch circuit SW1 is off. In the first place, if the connection point C is in a floating state when the switch circuit SW1 is off, no overshoot occurs. Therefore, in the third embodiment, when the switch circuit SW1 is off, the connection point C
Is set to a floating state, a switch circuit SW4 is provided.

When the switch circuit SW4 is turned off, the connection point C is in a floating state, so that the potential of the connection point C does not rise to the power supply voltage level as in the related art. However, if the connection point C is left floating, the potential of the connection point C gradually decreases due to the discharge, and when the switch circuit SW1 is turned on thereafter, there is a possibility that the rising waveform of the analog output may become dull.
For this reason, in the third embodiment, the feedback amplifier 5 is provided between the switch circuit SW4 and the output resistor 2, so that the potential at the connection point C does not fall below a predetermined level when the switch circuit SW4 is off. .

That is, the dummy circuit of the third embodiment functions as a feedback circuit that feeds back the analog output to the input side of the switch circuit SW1. The feedback amplifier 5
Can be configured with a general-purpose buffer that performs level shifting,
The circuit does not become complicated and the cost does not increase.

FIG. 6 is a signal waveform diagram of each part of FIG. The switching of the switch circuit SW1 is controlled in response to a control signal from the control circuit 4, and the switching of the switch circuit SW2 is controlled at substantially the opposite timing. Further, the switch circuit SW4 has a predetermined period τ during which the switch circuit SW1 is turned on.
₁ before, the switch circuit SW1 is kept on from off until after a predetermined period tau _2.

The reason why the on-period of the switch circuit SW4 is longer than the on-period of the switch circuit SW1 is that the analog output does not overshoot when the switch circuit SW1 is switched from off to on or from on to off. And a digital signal hold time is ensured.

As described above, in the D / A converter according to the third embodiment, since the switch circuit SW4 is provided between the switch circuits SW1 and SW2 and the constant current source 1, the switch circuit SW
When 1 is off, the connection point C can be set to a floating state, and since the connection point C does not rise to near the power supply voltage level, occurrence of overshoot can be suppressed. Further, since the dummy resistor 3 is not required, the circuit can be simplified.

In the D / A converter shown in FIG. 5, since the switch circuit SW4 is turned on before the switch circuit SW1 is turned on, the current from the constant current source 1 flows into the feedback circuit, and Unnecessary power consumption occurs due to the impedance. However, if the speed of the semiconductor element is increased due to the improvement of the semiconductor process in the future, the switching circuits SW1 and SW4 can be switched almost simultaneously, and almost no power consumption occurs in the feedback circuit. Reduction can be achieved.

In the above-described first to third embodiments, specific circuit configurations of the constant current source 1 and the switch circuits SW1 to SW4 are not mentioned, but these are bipolar transistors, PMOS transistors, NMOS transistors, and CMOS transistors. It is configured using transistors and the like.

[0055]

As described above in detail, according to the present invention, it is possible to switch whether or not a current flows through a dummy resistor.
In order to minimize the ON period of the switch circuit of
Power consumption can be greatly reduced as compared with a conventional D / A converter. In addition, during a predetermined period immediately before the first switch circuit is switched from off to on, control is performed to switch the second switch circuit so that the current from the constant current source flows through the dummy resistor. Nothing to do.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an output stage of a D / A converter according to a first embodiment.

FIG. 2 is a signal waveform diagram of nodes AE in FIG.

FIG. 3 is a circuit diagram showing a configuration of an output stage of a D / A converter according to a second embodiment.

FIG. 4 is a signal waveform diagram of each part in FIG. 3;

FIG. 5 is a circuit diagram showing a configuration of an output stage of a D / A converter according to a third embodiment.

FIG. 6 is a signal waveform diagram of each unit in FIG. 5;

FIG. 7 is a circuit diagram showing a configuration of an output stage of a conventional D / A converter including a dummy circuit.

FIG. 8 is a signal waveform diagram of nodes P to S in FIG. 7;

FIG. 9 is a circuit diagram showing a configuration of an output stage of a conventional D / A converter having no dummy circuit.

FIG. 10 is a signal waveform diagram of each unit in FIG. 9;

[Explanation of symbols]

 Reference Signs List 1 constant current source 2 output resistor 3 dummy resistor 4, 4a, 4b control circuit 5 feedback amplifier 10a to 10c unit SW1 to SW4 switch circuit

Claims (6)

[Claims] 1. A current addition type D / A converter in which a current from a constant current source flows to an output resistor to obtain an analog output, wherein a dummy resistor in which a current from the constant current source flows and a serial connection to the output resistor. A first switch circuit that is connected to switch whether or not the current from the constant current source flows to the output resistor based on a first switch control signal; and the first constant current source is connected in series to the dummy resistor. A second switch circuit that switches whether or not a current from the dummy resistor flows through the dummy resistor based on a second switch control signal; and a switch that outputs the first and second switch control signals based on the digital signal. A control circuit, wherein the second switch is configured to allow a current from the constant current source to flow through the dummy resistor within a predetermined period immediately before the first switch circuit switches from off to on. And a switch control circuit for switching control of the switch circuit.
A converter. A second switch circuit connected between the constant current source and the second switch circuit, the switch circuit being controlled to be switched based on a third switch control signal; The third switch circuit is turned on at a time earlier than the time when the first switch circuit is turned on for a first period, and the second switch circuit is turned on at a time later than the time when the first switch circuit is turned off for a second period. The third switch control signal is output such that the third switch circuit is turned off, and the first and second switch circuits are output such that the first and second switch circuits are turned on and off at substantially opposite timings. The D / A converter according to claim 1, wherein the D / A converter outputs a switch control signal. 3. The switch control circuit according to claim 2, wherein said second switch circuit is turned on at a time earlier than a time when said first switch circuit is turned on by a predetermined period, and said switch control circuit is turned on at a time substantially equal to a time when said first switch circuit is turned on. 2. The D / A converter according to claim 1, wherein the first and second control signals are output so that the second switch circuit is turned off at the same time. 4. An arithmetic unit for performing a predetermined logical operation based on the digital signal and a signal obtained by delaying the digital signal for a predetermined period, wherein the switch control circuit delays the digital signal for a predetermined period. The D / A converter according to claim 3, wherein a signal is used as the first switch control signal, and an output of the arithmetic unit is used as the second switch control signal. 5. A D / A converter of a current addition type in which a current from a constant current source flows through an output resistor to obtain an analog output, wherein the D / A converter is connected in series to the output resistor and outputs the current from the constant current source to the output. A first switch circuit for switching whether or not to flow through a resistor; a second switch circuit connected between the constant current source and the first switch circuit; and when the first switch circuit is off. A switch control circuit that controls switching of the second switch circuit so that a potential between the constant current source and the first switch circuit is in a floating state; and immediately before the first switch circuit is turned on. A feedback circuit that feeds back the analog output between the constant current source and the first switch circuit so that a potential between the constant current source and the first switch circuit becomes a predetermined potential; Be prepared A D / A converter, characterized in that: 6. The feedback circuit according to claim 3, wherein one end of the feedback circuit is connected to the first and second switch circuits and the other end is connected to the output resistor, and switching control is performed based on a third switch control signal. A switch circuit, wherein the switch control circuit turns on the third switch circuit at a time earlier by a first period than a time at which the first switch circuit turns on, and turns off the first switch circuit. Outputting the third switch control signal such that the third switch circuit is turned off at a time later than the second period by a second period, and the first and second switch circuits are turned on at substantially opposite timings; 6. The D / A converter according to claim 5, wherein the first and second switch control signals are output so as to be turned off.