JPH10256329A - Method of evaluating semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately evaluate the level of a semiconductor structure by providing an electrode insulated from the semiconductor structure on a part round a junction face and utilizing the state change of the semiconductor structure about a direction parallel to the junction face with varying a voltage applied to the electrode. SOLUTION: On the surface of an n-type Si substrate 1, a Schottky electrode 2 is formed to form a Schottky junction, a gate electrode 4 is provided through a gate oxide film 3 on a plane perpendicular to the Schottky junction face and connected to a gate voltage source 6, and the substrate 1 and electrode 2 are connected to a bias voltage source 5 to inject carriers into the junction face from the voltage source 5 while the capacitive response of the Schottky junction at each gate voltage is measured by a capacitance meter 7 to obtain a deep level distribution in a direction parallel to the junction face, based on the measured result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor evaluation method for evaluating a semiconductor structure having a junction such as a Schottky junction and a pn junction.

[0002]

2. Description of the Related Art Conventionally, an energy level existing in a semiconductor at a distance of energy of about kT or more from a valence band and a conduction band is called a deep level. here,
k is a Boltzmann constant of 1.38 × 10 ^-23 [JK ^-1 ],
T is an absolute temperature, and room temperature is 300 [K].

The following methods are known as methods for evaluating deep levels existing in a semiconductor structure having a junction such as a pn junction or a Schottky junction.

That is, carriers are injected by stimulation with heat or light, and the process of releasing and capturing the carriers is represented by a junction current,
It is measured as a change in junction capacitance. William
(J. Appl. Phys., 37, 3411 (196)
6)), Y. Furukawa et al. (JJ.
A. P. 5, 78 (1968), etc.
D. V. Lang (J. Appl. Phys., 45,
3203 (1974)) Deep Level
Transient Spectroscopy (hereinafter abbreviated as DLTS); R. Weisberg e
t al. (J. Appl. Phys., 39, 514)
9 (1968)
Stimulated Current (TS)
C); C. Cartballes et a
l. (Solid-State Commun., 6,
167 (1968) Thermally Sti
MULATED CAPACITANCE (SC)
An analytical evaluation method using a joining method such as AP is abbreviated.

However, according to these evaluation methods, a deep level distribution in a direction perpendicular to a plane which is equipotential to a voltage applied to the junction can be obtained by analysis, but a distribution in a parallel direction can be obtained. There is a disadvantage that it cannot be done.

As methods for obtaining the local spatial distribution of deep levels without analysis, there are optical DLTS for measuring the transient response by exciting the carrier with light, and measuring the transient response by exciting the carrier with an electron beam. There is known a method of locally exciting a carrier from a deep level using a scanning DLTS.

However, when light or an electron beam is used, carriers are excited in a process different from the case of being thermally excited, or a new defect is induced by light or an electron beam.
It is not necessarily suitable for measuring deep levels in which carriers are exchanged by thermal excitation.

Further, the periphery of the joint surface has a spatially complicated shape, which causes light scattering and irregular reflection.
There is a problem that the spatial resolution of the measurement is lower than that inside the joint surface.

As another bonding method, a DLTS using a MOSFET is known. In this method, as shown in FIG. 43, a forward bias voltage or a reverse bias voltage is applied between the n-type silicon substrate 11 and the p ⁺ -type source / drain Membrane 1
This is a method of measuring the transient response of the capacitance of the MOS capacitor composed of the gate electrode 2 and the gate electrode 13.

When a forward bias voltage is applied between the n-type silicon substrate 11 and the p ⁺ -type source / drain diffusion layer 14, electrons (major carriers) in the n-type silicon substrate 11
Is sucked out from the p ⁺ -type source / drain diffusion layer 14.

Therefore, when observing the transient response of the junction capacitance of the MOS capacitor, the change is caused only by holes (minority carriers). At this time, the energy level of the deep level detected by the measurement is located between the top of the valence band and the Fermi level of the intrinsic semiconductor.

Meanwhile, when a reverse bias voltage is applied between the n-type silicon substrate 11 and p ⁺ type source and drain diffusion layer 14, a hole in the n-type silicon substrate 11 (minority carriers), p ⁺ -type source -It is sucked out from the drain diffusion layer 14.

Therefore, when the transient response of the junction capacitance of the MOS capacitor is observed, the change is caused only by electrons (major carriers). At this time, what is observed is an electron trap (major carrier trap), and the energy level of the detected deep level is located between the bottom of the conduction band and the Fermi level of the intrinsic semiconductor.

However, DLT using MOSFET
In the S measurement, the energy position of the measured level is limited by the source / drain diffusion layer. Therefore, the information obtained on the spatial distribution of the level obtained by the measurement is obtained by the above-described bonding method (DLTS, TSC, TSCAP). ) And the same.

As a bonding method for providing a gate electrode around a bonding surface such as a junction pn junction or a Schottky junction, a gate-controlle as shown in FIG.
d diode (AS Grove & DJF)
itzgerald (Solid State Ele
ctron. , 9, 783 (1966)).

This means that the voltage applied to the gate electrode 13 changes the potential distribution at the junction between the n-type silicon substrate 11 and the p-type diffusion layer (or Schottky electrode) 17 to change the state density of carriers. And controls the current flowing through the pn junction (or Schottky junction). However, even with this method, the distribution of deep levels in a direction parallel to the bonding surface cannot be known.

As semiconductor devices are miniaturized,
The miniaturization of junctions such as pn junctions and Schottky junctions is progressing. At this time, the ratio of the number of atoms in contact with the periphery of the junction to the number of atoms not in contact with the periphery of the junction is high. Further, it is known that what forms a junction is different from the periphery of the junction and the inside thereof, and the periphery of the junction is electrically large in leakage current. It is also considered that gr centers (generated recombination centers) are concentrated around the junction.
Therefore, as the miniaturization of semiconductor devices progresses,
A technique for accurately evaluating the deep level of the junction will be required.

[0018]

As described above, levels in a semiconductor structure having a junction such as a Schottky junction or a pn junction have been conventionally evaluated by various bonding methods such as DLTS. However, an appropriate evaluation method for evaluating a deep level in a direction parallel to a bonding surface has not been proposed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor evaluation method suitable for evaluating a level in a direction parallel to a bonding surface. It is in.

[0020]

[Means for Solving the Problems]

[Structure] In order to achieve the above object, a semiconductor evaluation method according to the present invention (claim 1) includes a first bonding member made of a semiconductor, and a bonding surface joined to the first bonding member. A semiconductor evaluation method for evaluating a semiconductor structure having a junction constituted by a second junction constituent body that forms, wherein at least a part of a periphery of the junction surface is provided with an electrode insulated from the semiconductor structure, While carriers are being injected between the first junction member and the second junction member, a plurality of types of voltages are applied to the electrode, and the electrical connection of the junction at each voltage is increased. A response is measured, and based on the measurement result, a level of the semiconductor structure is evaluated in a direction parallel to the bonding surface.

Preferred embodiments of the present invention are as follows.

(1) In the semiconductor evaluation method (claim 1), a plurality of constant voltages having different amplitudes are applied to the electrodes.

(2) In the semiconductor evaluation method (claim 1), a plurality of types of pulse voltages having different amplitudes are applied to the electrodes.

(3) The semiconductor evaluation method ((1),
In (2)), a pulse voltage is applied to the junction,
A state is formed in which carrier injection is performed between the first joint structure and the second joint structure.

(4) In the above semiconductor evaluation method (Claim 1), a first pulse voltage is applied to the junction to cause a carrier between the first junction member and the second junction member. To form a state where the injection of
The electrode has the same pulse width as the first pulse voltage,
A plurality of types of second pulse voltages having different amplitudes are applied.

(5) In the semiconductor evaluation method (Claim 1), a first pulse voltage is applied to the junction to cause a carrier between the first junction member and the second junction member. To form a state where the injection of
The electrode has a different pulse width from the first pulse voltage,
A plurality of types of second pulse voltages having different amplitudes are applied.

(6) In the semiconductor evaluation method ((5)), the first pulse voltage has a pulse width smaller than that of the second pulse voltage.

(7) In the semiconductor evaluation method ((5)), the first pulse voltage has a pulse width larger than that of the second pulse voltage.

(8) The semiconductor evaluation method (claim 1,
In (1) to (7)), the electrical response of the junction is
A capacitance response, a current response or a voltage response of the junction;
A level distribution in a direction horizontal to the junction surface is determined based on a difference between the capacitance response, the current response, or the voltage response at a reference voltage and that at another voltage.

[Operation] In the present invention, an electrode insulated from the semiconductor structure is provided on at least a part of the periphery of the bonding surface. Therefore, by changing the voltage applied to this electrode, the direction parallel to the bonding surface can be changed. The state of the semiconductor structure changes.

Therefore, while carriers are being injected between the first junction member and the second junction member, a plurality of voltages are applied to the electrodes, and the junction at each voltage is applied. By measuring the electrical response of the semiconductor structure, it becomes possible to accurately evaluate the level of the semiconductor structure in a direction parallel to the bonding surface based on the measurement result.

[0032]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 6 is a diagram showing a semiconductor structure evaluation system according to the embodiment.

[0034] In the figure, 1 denotes a n-type silicon substrate, this is the n-type silicon substrate 1 surface Schottky electrode 2 made of TiSi ₂ is formed, thereby being Schottky junction is formed. The impurity concentration of the n-type silicon substrate 1 is 1 × 10 ¹⁶ cm ⁻³ .

A gate electrode 4 made of TiSi ₂ is provided on a surface perpendicular to the junction surface of the Schottky junction via a gate oxide film 3 made of SiO ₂ . This gate electrode 4 is connected to a gate voltage source 7.

The n-type silicon substrate 1 and the Schottky electrode 2 are connected to a bias voltage source 5 so that a voltage can be applied to the junction surface of the Schottky junction. That is, carriers can be injected between the n-type silicon substrate 1 and the Schottky electrode 2. Further, a capacitance meter 7 is connected in parallel to the bias voltage source 5 so that a change in capacitance of the Schottky junction can be measured.

Next, the method for evaluating the semiconductor structure according to the present embodiment will be explained.

As a bias voltage, a pulse voltage as shown in FIG. 2 is applied to the Schottky junction by the bias voltage source 5 so that injection of electrons occurs. here,
In FIG., V _P = 0V, a V _M = -1V. Also,
The pulse width is 200 μsec.

In this state, a change in the capacitance of the Schottky junction at each gate voltage is observed.

That is, a constant voltage Vf (= 0.54) as shown in FIG.
V) is applied to the gate electrode 4. The time change of the junction capacitance of the Schottky junction at this time is observed by the capacitance meter 7. The observation result is shown in a characteristic curve C _fe of FIG.

The gate voltage source 6 applies a constant voltage Va (= 5 V) as shown in FIG. 3 to the gate electrode 4 as a gate voltage. The time change of the junction capacitance of the Schottky junction at this time is observed by the capacitance meter 7. The observation result is shown in a characteristic curve C _ae of FIG.

Further, a constant voltage Vd (= 0 V) as shown in FIG. 3 is applied to the gate electrode 4 by the gate voltage source 6 as a gate voltage. The change over time of the junction capacitance of the Schottky junction at this time is observed by the capacitance meter 7. The observation result is shown in a characteristic curve C _de of FIG.

The gate voltage source 6 applies a constant voltage Vi (= −5 V) as shown in FIG. 3 to the gate electrode 4 as a gate voltage. The change over time of the junction capacitance of the Schottky junction at this time is observed by the capacitance meter 7. The observation results are shown in the characteristic curve _Cie in FIG.

From the above results, since the characteristic curve is convex upward, the level existing around the Schottky junction is an electron trap, and one type of level mainly depends on the substrate concentration and the bias voltage. It is considered that it exists near the junction (within 1 μm). When the level existing around the Schottky junction is a hole trap, the characteristic curves C _fh , C _ah , C _dh , and C _ih are convex downward as shown in FIG.

FIG. 6 shows an element structure equivalent to the Schottky junction with the MOS gate structure of FIG. FIG. 7 shows a band structure in a BB ′ section of FIG.

When the gate voltage Vg is Vf = 0.54 V corresponding to the flat band voltage, the band structure immediately below the gate electrode 4 is in a flat band state as shown in FIG. Therefore, the carrier density in the n-type silicon substrate 1 near the gate oxide film 3 and the carrier density in the n-type silicon substrate 1 away from the gate oxide film 3 become almost equal. As a result, the Schottky junction near the gate oxide film 3 and the one at a distance from the gate oxide film 3 have the same situation.

Next, the case where the constant voltage applied to the gate electrode 4 is changed with reference to the time when the flat band voltage Vf is applied to the gate electrode 4 will be considered.

When Vg = Va = 5V, the area immediately below the gate electrode 4 is in an accumulation state, and the electron traps existing in the n-type silicon substrate 1 immediately below the gate electrode 4 are filled with electrons attracted by the gate voltage. State.

Therefore, the electron trap existing in the range controlled by the gate voltage is in a state of being filled while the change of the junction capacitance occurs. Therefore, the electron trap does not contribute to the change in the junction capacitance.
The change in the junction capacitance of the Schottky junction is smaller than that when a flat band voltage is applied.

When the flat band voltage is applied to the gate electrode 4, the empty electron trap is filled with the electrons attracted by the gate electrode 4. As a result, the depletion layer of the Schottky junction expands to compensate for this charge. Therefore, the junction capacitance of the Schottky junction is smaller than that when a flat band voltage is applied.

When Vg = Vd = 0 V, the area immediately below the gate electrode 4 is depleted, and the electron traps existing in the n-type silicon substrate 1 immediately below the gate electrode 4 are empty due to the influence of the gate voltage. .

Therefore, the electron trap existing in the range controlled by the gate voltage does not contribute to the change in the junction capacitance, and the change in the junction capacitance is smaller than that when the flat band voltage is applied. .

When the flat band voltage is applied to the gate electrode 4, the filled electron trap becomes empty because electrons are driven away by the gate electrode 4. As a result, the width of the depletion layer of the Schottky junction is reduced. Therefore, the junction capacitance of the Schottky junction is smaller than that when a flat band voltage is applied.

When Va = −5 V, the area immediately below the gate electrode 4 is inverted. At this time, the electron trap existing in the n-type silicon substrate 1 immediately below the gate electrode 4 becomes empty due to the influence of the gate voltage, and spreads further than in the depletion state.

Therefore, a wider range of electron traps is controlled by the gate voltage than in the depletion state. Therefore, the amount of change in the junction capacitance is smaller than in the depletion state.

When the flat band voltage is applied to the gate electrode 4, the filled electron trap becomes empty because the electrons are driven away by the gate electrode 4. further,
Hole injection also occurs. That is, in this case, the positive charges increase by the amount of empty electron traps and the amount of holes injected.
As a result, the width of the depletion layer of the Schottky junction is further reduced. Therefore, the junction capacitance of the Schottky junction is larger than in the depletion state.

The flat band voltage Vf =
When 0.54 V is applied, there is no newly controlled electron trap compared to when the gate electrode 4 is not present. On the other hand, when V _a = 0 V is applied to the gate electrode 4,
In order to deplete in the range of 0.3 μm just below the gate electrode 4,
The electron traps in the region A shown in FIG. 8 are empty during the transition of the junction capacitance.

From this, the capacitance change ΔC when the constant voltage (= flat band voltage) Vf shown in FIG. 4 is applied.
The difference between fe and the capacitance change ΔCde when the constant voltage Vd is applied is proportional to the amount of electron traps existing in the range shown in FIG. Since the difference in the capacitance change can be converted to the number of charges, the density of the electron traps in the region A shown in FIG. 8 can be measured.

Here, the horizontal length of the region A shown in FIG. 8 changes depending on the gate voltage. Therefore, the spatial distribution of deep levels existing around the Schottky junction in the direction parallel to the junction plane is determined from the difference between the change ΔC and the difference ΔCfe of the transient capacitance C measured for each constant voltage (gate voltage). Can be measured.

On the other hand, also in the conventional evaluation system shown in FIG. 44, the junction capacitance changes depending on the gate voltage. However, this change in junction capacitance occurs because the state density of carriers around the junction changes according to the gate voltage.
Even when a deep level does not exist, a slight change in junction capacitance is observed when a gate voltage is applied. Therefore, it is not possible to determine whether a deep level exists around the junction or determine the concentration of the deep level only based on the measurement result of the junction capacitance when the gate voltage is applied.

However, by measuring a transient change in junction capacitance when a constant voltage is applied according to the method of the present invention, a deep level existing around the junction can be detected.

(Second Embodiment) Connection between an object to be measured (n-type silicon substrate 1, Schottky electrode 2) and measuring instruments (bias voltage source 5, gate voltage source 6, capacitance meter 7) in this embodiment. The method is the same as that of the first embodiment.

This embodiment is different from the first embodiment in that the gate voltage source 6 applies a pulse voltage synchronized with the pulse voltage applied to the Schottky electrode 2 to the gate electrode 4. Next, the method for evaluating the semiconductor structure according to the present embodiment will be explained. As a bias voltage, a pulse voltage as shown in FIG. 2 is applied to the Schottky junction by the bias voltage source 5 so that injection of electrons occurs. Here, V _P = 0V, a V _M = -1V.
The pulse width was set to 200 μsec.

In this state, a change in capacitance of the Schottky junction at each gate voltage is observed.

That is, a pulse voltage (Va = 5) as shown in FIG.
V, Vf = 0.54 V, pulse voltage width 200 μsec)
Is applied to the gate electrode 4 in synchronization with the bias voltage.
The time change of the junction capacitance of the Schottky junction at this time is observed by the capacitance meter 7. The observation result is shown in a characteristic curve _Cfa of FIG.

When the amplitude Va of the pulse voltage applied to the gate electrode 4 is 5 V, the area immediately below the gate electrode 4 is in an accumulation state, in which electrons are attracted. At this time, since the pulse voltage shown in FIG. 2 is applied to the Schottky junction, electrons are injected around the Schottky junction.

At the time of electron injection, sufficient electrons are supplied to fill a deep level. Therefore, injection of electrons by the gate electrode 4 has an effect on transient changes in the junction capacitance of the Schottky junction. Absent.

The gate voltage source 6 supplies a gate voltage as a pulse voltage (Vd = 0 V,
(Vf = 0.54 V, pulse voltage width 200 μsec) is applied to the gate electrode 4 in synchronization with the bias voltage. The time change of the junction capacitance of the Schottky junction at this time is observed by the capacitance meter 7. The observation results are shown in the characteristic curve C of FIG.
Shown in _df .

When the amplitude Vd of the pulse voltage applied to the gate electrode 4 is 0 V, the area immediately below the gate electrode 4 is in a depletion state. At this time, since the pulse voltage shown in FIG. 2 is applied to the Schottky junction, electrons are injected around the Schottky junction.

At the time of the transient change in the junction capacitance of the Schottky junction immediately after the injection of the electrons, a very small amount of electrons are captured by the deep level directly below the gate electrode 2 and the deep level near the Schottky junction is reduced. Since electron emission is observed,
The change ΔC _{df in} the junction capacitance when the pulse voltage shown in FIG. 10 is applied to the gate electrode 4 is smaller than the change ΔC _{af in} the junction capacitance when the pulse voltage shown in FIG.

The gate voltage source 6 generates a gate voltage as a pulse voltage (Vi = −5) as shown in FIG.
V, Vf = 0.54 V, pulse voltage width 200 μsec)
Is applied to the gate electrode 4 in synchronization with the bias voltage.
The time change of the junction capacitance of the Schottky junction at this time is observed by the capacitance meter 7. The observation result is shown in a characteristic curve C _if of FIG.

When the amplitude Vi of the pulse voltage applied to the gate electrode 4 is -5 V, the area immediately below the gate electrode 4 is in an inverted state, and the area immediately below the gate electrode 4 is in a depleted state. At this time, since the pulse voltage shown in FIG. 2 is applied to the Schottky junction,
Electrons are injected into (around) the Schottky junction.

Immediately after this, when the junction capacitance of the Schottky junction changes transiently, a small amount of electrons captured by a deep level immediately below the gate electrode 4 and emission of a deep level electron near the Schottky junction are generated. 9, the change ΔC _{if in} the junction capacitance when the pulse voltage shown in FIG. 11 is applied to the gate electrode 4 is larger than the change ΔC _{af in} the junction capacitance when the pulse voltage shown in FIG. Is also smaller.

By the pulse voltage applied to the gate electrode 4, the spatial distribution of deep levels can be obtained as in the first embodiment.

Here, the difference from the first embodiment is that when carriers are injected into the Schottky junction, the value of the gate voltage (Va, Va,
Vd, Vi) is different from the gate voltage value (Vf) when observing a transient change in the junction capacitance of the Schottky junction.

However, even if the gate voltage values (Va, Vd, Vi) are different when controlling the occupation state of the deep level, the transient change in the junction capacitance of the Schottky junction is observed. The value of the gate voltage (Vf) is the same. Therefore, even if the conditions for injecting carriers into the deep level are changed, the state of the system at the time of measuring the transient volume is almost the same, so that a highly reliable spatial distribution of the deep level can be obtained.

In this embodiment, the amplitude of the pulse voltage (gate voltage) at the time of measuring the transient capacitance response is a flat band voltage, but may be an arbitrary voltage as shown in FIGS.

For example, when a zero bias is applied to a portion of the silicon substrate forming the Schottky junction,
In order not to disrupt this potential distribution, the voltage applied to the gate electrode 4 at the time of measuring the transient capacitance is desirably 0V.

Further, a gate voltage as shown in FIGS. 15 to 22 or a voltage as shown in FIGS. 20 to 24 may be applied.

FIGS. 15 to 22 are FIGS. 9 to 11, respectively.
FIGS. 13 and 14 show an example in which the application start time of the pulse voltage applied to the gate electrode is earlier than that of the bias voltage applied to the Schottky electrode by a predetermined time. The application end time is the same.

As a result, the pulse width of the pulse voltage applied to the gate electrode becomes longer, and it becomes possible to measure an electron trap having a longer capture time constant. Conversely, traps with a short capture time constant will be sorted out.

20 to 24 correspond to FIGS. 9 to 1, respectively.
1, which corresponds to FIGS. 13 and 14, in which the application start time of the pulse voltage applied to the gate electrode is delayed by a predetermined time from that of the bias voltage applied to the Schottky electrode. The application end time is the same.

As a result, the pulse width of the pulse voltage applied to the gate electrode is shortened, and measurement of an electron trap having a short time constant of capture becomes possible. Conversely, traps with a long capture time constant will be sorted out.

FIGS. 25 to 42 show various modifications of the evaluation system. In the drawings, FIG. 1A is a sectional view, and FIGS. 1B and 1C are plan views. The evaluation method is the same as in the above embodiment.

FIG. 25 shows a structure in which the MOS gate structure is in contact with the periphery of the Schottky junction on the surface of the n-type silicon substrate 1.

FIG. 26 shows a structure in which the periphery of the junction surface of the Schottky junction is easily affected by the gate voltage.

FIG. 27 shows a structure in which a MOS gate structure is also formed on Schottky electrode 2 and the periphery of the junction surface of the Schottky junction is more easily affected by the gate voltage than in the case of FIG. Is shown.

FIG. 28 shows a structure in which the MOS gate structure is in contact with the periphery of the Schottky junction on the surface of the n-type silicon substrate 1. However, compared to the case of FIG.
There are many parts in contact with the joint surface of the Schottky joint. That is, the range that can be measured is wide. FIG. 29 shows a structure in which the MOS gate structure is in contact with the periphery of the Schottky junction surface on the surface of the n-type silicon substrate 1. The MOS gate structure is formed so as to surround the entire periphery of the junction surface of the Schottky junction, and has a wider measurable range than the case of FIG.

FIG. 30 shows the structure of FIG.
The plane structure of the gate structure and the Schottky junction has a circular pattern to prevent electric field concentration.

FIG. 31 shows a structure in which the MOS gate structure surrounds the periphery equivalent to the (110) plane of the Si crystal and is suitable for examining the orientation dependency.

FIG. 32 shows the structure of FIG.
An example of a structure in which a gate structure is also formed on the Schottky electrode 2 and a voltage is more stably applied around the junction surface of the Schottky junction is shown.

FIG. 33 shows an example in which a MOS gate structure is provided so as to cover the entire surface of Schottky electrode 2 and n-type silicon substrate 1 around it. Even if the Schottky electrode 2 is thus covered, there is no problem because the potential distribution immediately below the Schottky electrode 2 is determined by the potential of the Schottky electrode 2.

FIG. 34 shows a structure in which a MOS gate structure is provided so as to surround the entire junction surface of the Schottky junction in the structure of FIG. 32, and a measurable range is wider than that of FIG.

FIG. 35 shows a structure in which the planar pattern of the MOS gate structure is comb-shaped and the perimeter of the junction surface per unit area is increased.

FIG. 36 shows a structure in which a plurality of minute Schottky electrodes 2 are arranged and formed to increase the perimeter of the bonding surface which can be measured per unit area.
The Schottky electrode 2 is integrated with the wiring 5.
Further, all the Schottky electrodes 2 have the same size and the same pattern. Thus, it is possible to prevent a decrease in measurement accuracy due to a variation in size or pattern.

As shown in FIG. 37, the structure shown in FIG. 35 is such that the planar pattern of the MOS gate structure and the Schottky junction is circular to prevent electric field concentration.

FIG. 38 shows an example in which a MOS gate structure is provided so as to surround a surface perpendicular to the Schottky junction surface. This is more suitable for measuring the spatial distribution of charge traps horizontal to the junction surface than the structure of FIG.

FIG. 39 shows a MOS transistor having the structure shown in FIG.
The plane structure of the gate structure and the Schottky junction has a circular pattern to prevent electric field concentration.

FIG. 40 shows a structure in which the MOS gate structure surrounds the periphery equivalent to the (110) plane of the Si crystal and is suitable for examining the orientation dependency.

FIG. 41 shows a structure in which the gate electrode 4 and the Schottky junction are insulated by air. The gate electrode 4 can be moved up and down by means not shown, and can be fixed at a predetermined height.

FIG. 42 shows an example in which the structure shown in FIG. 1 is formed on an SOI substrate.

The present invention is not limited to the above embodiment.

For example, in the above embodiment, the case of a Schottky junction using titanium silicide as an electrode material and n-type silicon as a semiconductor material has been described. However, the present invention is directed to cobalt silicide, nickel silicide, vanadium silicide A metal such as palladium silicide, aluminum, gold, platinum or palladium with a semiconductor using n-type silicon or p-type silicon as a semiconductor material, or a compound semiconductor such as gallium arsenide or gallium indium phosphide and metal. , A pn junction of silicon, and a pn junction of a compound semiconductor.

In the above embodiment, the evaluation is performed based on the response of the junction capacitance. However, the evaluation can be performed based on the response of the junction current or the response of the junction potential.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0106]

As described in detail above, according to the present invention, an electrode insulated from the semiconductor structure is provided on at least a part of the periphery of the bonding surface, and the voltage applied to this electrode is changed to change the voltage on the bonding surface. By utilizing the fact that the state of the semiconductor structure changes with respect to the parallel direction, it becomes possible to accurately evaluate the level of the semiconductor structure with respect to the direction parallel to the bonding surface.

[Brief description of the drawings]

FIG. 1 is a diagram showing an evaluation system according to a first embodiment.

FIG. 2 is a diagram showing a waveform of a bias voltage applied to a Schottky junction in the first embodiment.

FIG. 3 is a diagram showing a waveform of a gate voltage applied to a gate electrode in the first embodiment.

FIG. 4 is a diagram showing a time change of a junction capacitance of a Schottky junction when a carrier trap is an electron trap;

FIG. 5 is a diagram showing a time change of a junction capacitance of a Schottky junction when a carrier trap is a hole trap;

FIG. 6 is a sectional view showing an element structure equivalent to the Schottky junction with the MOS gate structure of FIG. 1;

FIG. 7 is a diagram showing how the band structure of the device structure of FIG. 6 changes depending on the gate voltage.

FIG. 8 is a cross-sectional view showing a region where an empty electron trap exists during a transient change in junction capacitance.

FIG. 9 is a diagram showing a waveform of a gate voltage applied to a gate electrode in the second embodiment.

FIG. 10 is a diagram showing a waveform of a gate voltage applied to a gate electrode in the second embodiment.

FIG. 11 is a diagram showing a waveform of a gate voltage applied to a gate electrode in the second embodiment.

FIG. 12 is a diagram showing a time change of a junction capacitance of a Schottky junction when a carrier trap is an electron trap;

FIG. 13 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 14 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 15 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 16 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 17 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 18 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 19 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 20 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 21 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 22 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 23 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

FIG. 24 is a diagram showing a waveform of a gate voltage applied to a gate electrode in a modification of the second embodiment.

25 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure of FIG. 1;

26 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

27 is a plan view and a cross-sectional view illustrating a modification of the Schottky junction with the MOS gate structure in FIG. 1;

FIG. 28 is a plan view and a cross-sectional view showing a modification of the Schottky junction with the MOS gate structure of FIG. 1;

29 is a plan view and a cross-sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

30 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

31 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

32 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

33 is a plan view and a cross-sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

34 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

35 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

36 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

FIG. 37 is a plan view and a cross-sectional view showing a modification of the Schottky junction with the MOS gate structure of FIG. 1;

38 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

39 is a plan view and a cross-sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

40 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

41 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

42 is a plan view and a sectional view showing a modification of the Schottky junction with the MOS gate structure in FIG. 1;

FIG. 43 is a view for explaining a conventional joining method.

FIG. 44 is a view for explaining another conventional joining method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... n-type silicon substrate (1st junction structure) 2 ... Schottky electrode (2nd junction structure) 3 ... Gate insulating film 4 ... Gate electrode 5 ... Bias voltage source 6 ... Gate voltage source 7 ... Capacitance meter

Claims (1)

[Claims] 1. A semiconductor structure having a junction constituted by a first junction member made of a semiconductor and a second junction member joined to the junction member and forming an energy barrier at the joint surface. A semiconductor evaluation method for evaluating, wherein an electrode insulated from the semiconductor structure is provided on at least a part of a periphery of the bonding surface, and a carrier is provided between the first bonding member and the second bonding member. While a plurality of voltages are applied to the electrode while the injection is being performed, the electrical response of the junction at each voltage is measured, and based on the measurement result, a direction parallel to the bonding surface is determined. A semiconductor evaluation method, wherein a level of the semiconductor structure is evaluated.