JPH10247704A - Circuit device and its manufacture - Google Patents
Circuit device and its manufactureInfo
- Publication number
- JPH10247704A JPH10247704A JP10100067A JP10006798A JPH10247704A JP H10247704 A JPH10247704 A JP H10247704A JP 10100067 A JP10100067 A JP 10100067A JP 10006798 A JP10006798 A JP 10006798A JP H10247704 A JPH10247704 A JP H10247704A
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- conductor layer
- circuit board
- hole
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は混成集積回路等の回
路装置及びその製造方法に関する。The present invention relates to a circuit device such as a hybrid integrated circuit and a method for manufacturing the same.
【０００２】[0002]
【従来の技術及び発明が解決しようとする課題】半導体
素子等の回路素子を含む混成集積回路装置において、放
熱体等が固着された背の高い回路素子を含む場合には、
この一部又は全部を回路基板の孔に挿入することが考え
られる。この様に回路基板の孔に回路素子を配置する場
合において、回路素子の配置を容易且つ確実に達成でき
れば好都合である。また、発熱の大きい回路素子を使用
する場合には、良好な放熱性が要求される。 また、回
路装置においては、ノイズ防止が必要になる。2. Description of the Related Art In a hybrid integrated circuit device including a circuit element such as a semiconductor element, when a tall circuit element to which a radiator or the like is fixed is included,
It is conceivable to insert a part or all of this into the hole of the circuit board. When arranging the circuit elements in the holes of the circuit board in this way, it is advantageous if the arrangement of the circuit elements can be achieved easily and reliably. In addition, when a circuit element generating a large amount of heat is used, good heat dissipation is required. Further, in a circuit device, it is necessary to prevent noise.
【０００３】そこで本発明の目的は、薄型化を容易に達
成できると共に、容易に製造することができる回路装置
及びその製造方法を提供することにある。An object of the present invention is to provide a circuit device which can be easily made thin and can be easily manufactured, and a method of manufacturing the same.
【０００４】[0004]
【課題を解決するための手段】上記課題を解決し、上記
目的を達成するための装置の発明は、絶縁性回路基板と
回路素子とを備えた回路装置であって、前記回路基板の
一方の主面から他方の主面に至る貫通孔が設けられてお
り、前記回路基板の一方の主面には前記回路素子を接続
するための配線導体層が設けられており、前記回路基板
の他方の主面側に前記貫通孔を閉塞するように他方の主
面側の導体層が配設されており、前記回路素子が前記貫
通孔の中に配置され且つ前記貫通孔を閉塞している他方
の主面側の導体層で支持されており、前記回路素子と前
記回路基板の一方の主面上の前記配線導体層とが導体で
接続されている回路装置において、前記他方の主面側の
導体層は、前記絶縁性回路基板の他方の主面に固着され
た金属シ−トと該金属シ−トにメッキされて成るメッキ
層とから構成されており、前記他方の主面側の導体層の
肉厚は前記絶縁性回路基板の肉厚よりも小さいことを特
徴とする回路装置に係わるものである。なお、請求項２
に示すように親基板を設けることが望ましい。上記目的
を達成するための方法の発明は、一方の主面から他方の
主面に至る貫通孔を有し、前記一方の主面の第１の金属
シ−トが貼り付けられた絶縁性回路基板を用意する工程
と、前記回路基板よりも薄い第２の金属シ−トを用意
し、前記回路基板の前記他方の主面に対して前記貫通孔
を閉塞するように接着する工程と、次に、メッキによっ
て少なくとも前記第１及び第２の金属シ−トの露出面に
金属メッキ層を形成する工程と、前記金属メッキ層を伴
った前記第１の金属シ−トを所望のパタ−ンにエッチン
グして配線導体層を形成する工程と、前記金属メッキ層
を伴った前記第２の金属シ−トの前記貫通孔を閉塞する
部分の上に回路素子を配置する工程と、前記回路素子と
前記配線導体層とを導体で接続する工程とを有している
ことを特徴とする回路装置の製造方法に係わるものであ
る。Means for Solving the Problems The invention of an apparatus for solving the above problems and achieving the above object is a circuit device comprising an insulating circuit board and a circuit element, wherein one of the circuit boards is provided. A through hole extending from the main surface to the other main surface is provided, and a wiring conductor layer for connecting the circuit element is provided on one main surface of the circuit board, and the other of the circuit board is provided with a wiring conductor layer. A conductor layer on the other main surface side is disposed on the main surface side so as to close the through-hole, and the other circuit element is disposed in the through-hole and closes the through-hole. In a circuit device supported by a conductor layer on the main surface side, and the circuit element and the wiring conductor layer on one main surface of the circuit board are connected by a conductor, the conductor on the other main surface side The layer includes a metal sheet fixed to the other main surface of the insulating circuit board and the metal sheet. And a plating layer formed by plating a metal sheet, wherein the thickness of the conductor layer on the other main surface side is smaller than the thickness of the insulating circuit board. It is concerned. Claim 2
It is desirable to provide a parent board as shown in FIG. The invention of a method for achieving the above object is to provide an insulating circuit having a through hole extending from one main surface to another main surface, to which a first metal sheet on the one main surface is attached. A step of preparing a board; a step of preparing a second metal sheet thinner than the circuit board; and bonding the second metal sheet to the other main surface of the circuit board so as to close the through hole. Forming a metal plating layer on at least the exposed surfaces of the first and second metal sheets by plating; and forming the first metal sheet with the metal plating layer in a desired pattern. Forming a wiring conductor layer by etching the circuit element, arranging a circuit element on a portion of the second metal sheet with the metal plating layer that closes the through hole, And a step of connecting the wiring conductor layer with a conductor by a conductor. Those relating to the manufacturing method of the circuit device.
【０００５】[0005]
【発明の作用及び効果】各請求項の発明によれば、回路
基板の貫通孔の中に回路素子を配置し、この貫通孔が回
路基板よりも肉薄の金属シ−トとメッキ層から構成され
る導体層によって閉塞されているので、回路装置の肉薄
化を達成することができると共に、回路素子の配置及び
支持を容易に達成することかでき、回路装置の組立てが
容易になる。また、請求項２の発明によれば、親基板の
導体層によっても貫通孔が閉塞されるので、回路素子の
支持を容易且つ確実に達成することができ、且つ親基板
の導体層を通して放熱させることが可能となる。また、
請求項３の発明によれば、回路装置を容易に製造するこ
とができる。According to the present invention, a circuit element is disposed in a through hole of a circuit board, and the through hole is formed of a metal sheet and a plating layer which are thinner than the circuit board. Since the circuit device is closed by the conductive layer, the thickness of the circuit device can be reduced, the arrangement and support of the circuit element can be easily achieved, and the circuit device can be easily assembled. Further, according to the second aspect of the present invention, since the through-hole is also closed by the conductor layer of the parent substrate, the support of the circuit element can be achieved easily and reliably, and heat is radiated through the conductor layer of the parent substrate. It becomes possible. Also,
According to the third aspect of the invention, the circuit device can be easily manufactured.
【０００６】[0006]
【実施例】次に、図１〜図１０を参照して本発明の実施
例に係わる回路装置を説明する。図１及び図２に示すよ
うに、この回路装置としての混成集積回路１は、誘電体
即ち絶縁体から成る回路基板２と、回路素子としての半
導体素子３と、抵抗又はコンデンサ等の別の回路素子４
とを含む。比較的薄い回路素子４は回路基板２の一方の
主面５の上に配置されているが放熱体６を備えているた
めに比較的に背の高い半導体素子３は、貫通孔７の中に
配置されている。即ち、回路基板２には、一方の主面５
から他方の主面８に至る貫通孔７が形成され、この貫通
孔７の中に直方体の放熱体６が配置され、この放熱体６
の上にろう材９によって半導体チップ１０が固着されて
いる。Next, a circuit device according to an embodiment of the present invention will be described with reference to FIGS. As shown in FIGS. 1 and 2, a hybrid integrated circuit 1 as a circuit device includes a circuit board 2 made of a dielectric or insulator, a semiconductor element 3 as a circuit element, and another circuit such as a resistor or a capacitor. Element 4
And Although the relatively thin circuit element 4 is arranged on one main surface 5 of the circuit board 2, the semiconductor element 3 having a relatively high height due to the provision of the heat radiator 6 is disposed in the through hole 7. Are located. That is, one main surface 5 is provided on the circuit board 2.
A through-hole 7 is formed extending from the heat sink to the other main surface 8, and a rectangular parallelepiped radiator 6 is disposed in the through-hole 7.
A semiconductor chip 10 is fixed to the semiconductor chip 10 by a brazing material 9.
【０００７】回路基板２の一方の主面５には、配線導体
層１１、１２、１３、１４、１５、１６、１７が形成さ
れ、他方の主面８には図２及び図３に示すように第１、
第２及び第３の外部接続用導体層１８、１９、２０及び
内部接続用導体層２１が形成されている。なお、実際に
は回路基板２の一方の及び他方の主面５、８の上に半田
接続に無関係の部分を覆うための半田レジスト層を周知
の技術に従って設けるが、本実施例を示す図面ではこれ
が省略されている。On one main surface 5 of the circuit board 2, wiring conductor layers 11, 12, 13, 14, 15, 16, 17 are formed, and on the other main surface 8, as shown in FIGS. First,
The second and third external connection conductor layers 18, 19, 20 and the internal connection conductor layer 21 are formed. In practice, a solder resist layer for covering a portion unrelated to solder connection is provided on one and the other main surfaces 5 and 8 of the circuit board 2 according to a known technique, but in the drawings showing this embodiment, This has been omitted.
【０００８】半導体チップ１０は本実施例の場合、電力
用の電界効果トランジスタであって、ソース電極が内部
接続導体としてのリード線２２によって配線導体層１１
に接続され、ドレイン電極がリード線２３によって配線
導体層１２に接続され、ゲート電極がリード線２４によ
って配線導体層１３に接続されている。内部接続導体と
してのリード線２２、２３、２４はそれぞれワイヤボン
ディング方法で設けられている。In this embodiment, the semiconductor chip 10 is a field effect transistor for power, and its source electrode is connected to the wiring conductor layer 11 by a lead wire 22 as an internal connection conductor.
The drain electrode is connected to the wiring conductor layer 12 by a lead wire 23, and the gate electrode is connected to the wiring conductor layer 13 by a lead wire 24. The lead wires 22, 23, and 24 as internal connection conductors are provided by a wire bonding method.
【０００９】回路基板２に設けられた貫通孔７の壁面に
はノイズ防止用導体層２５が設けられ、これが主面５上
の配線導体層１１に接続されている。A noise preventing conductor layer 25 is provided on the wall surface of the through hole 7 provided in the circuit board 2, and is connected to the wiring conductor layer 11 on the main surface 5.
【００１０】回路基板２の他方の主面８の第１の外部接
続用導体層１８は、接着層２６によって回路基板２の他
方の主面８に固着された銅シートから成る金属シート４
３と金属メッキ層３５とから成る。この第１の外部接続
用導体層１８は、図２から明らかなように貫通孔７を回
路基板２の他方の主面８側で閉塞する部分２７を有す
る。回路基板２の他方の主面８における配線導体層２１
も金属シート４３とメッキ層３５とで形成され、また図
３に示す第２及び第３の外部接続用導体層１９、２０も
金属シートとメッキ層で形成されている。図１に示す配
線導体層１５、１６は回路基板２の側面の溝２８、２９
の導体層３０、３１によって図３の回路基板２の他方の
主面８の外部接続用導体層１９、２０に接続されてい
る。また、図１の配線導体層１７はスルーホール３２の
導体層３３によって図３の他方の主面８の導体層２１に
接続されている。The first external connection conductor layer 18 on the other main surface 8 of the circuit board 2 is made of a metal sheet 4 made of a copper sheet fixed to the other main surface 8 of the circuit board 2 by an adhesive layer 26.
3 and a metal plating layer 35. The first external connection conductor layer 18 has a portion 27 that closes the through hole 7 on the other main surface 8 side of the circuit board 2 as is apparent from FIG. Wiring conductor layer 21 on the other main surface 8 of circuit board 2
The second and third external connection conductor layers 19 and 20 shown in FIG. 3 are also formed of a metal sheet and a plating layer. The wiring conductor layers 15 and 16 shown in FIG.
3 are connected to the external connection conductor layers 19 and 20 on the other main surface 8 of the circuit board 2 in FIG. Further, the wiring conductor layer 17 in FIG. 1 is connected to the conductor layer 21 on the other main surface 8 in FIG.
【００１１】回路基板２の一方の主面５における配線導
体層１１、１２、１３、１４、１５、１６、１７は、図
１０から明らかなように金属シート４３と金属メッキ層
３５とから成る。The wiring conductor layers 11, 12, 13, 14, 15, 16, 17 on one main surface 5 of the circuit board 2 are composed of a metal sheet 43 and a metal plating layer 35 as is apparent from FIG.
【００１２】第１の外部接続用導体層１８の閉塞部分２
７の上には図２から明らかなように金属メッキ層３６が
設けられ、この上に放熱体６が半田３７によって固着さ
れている。The closed portion 2 of the first external connection conductor layer 18
As is clear from FIG. 2, a metal plating layer 36 is provided on 7, and the heat radiator 6 is fixed thereon by solder 37.
【００１３】図１〜図３の混成集積回路１は図４に示す
絶縁性親基板３８の上に配置される。親基板３８にはグ
ランドに接続された第１の導体層３９の他に、第２及び
第３の導体層４０、４１が設けられ、更に回路素子（図
示せず）が配設されている。The hybrid integrated circuit 1 shown in FIGS. 1 to 3 is arranged on an insulating parent substrate 38 shown in FIG. In addition to the first conductor layer 39 connected to the ground, second and third conductor layers 40 and 41 are provided on the mother board 38, and circuit elements (not shown) are further provided.
【００１４】図５及び図６は親基板３８の上に混成集積
回路１を配置した状態を図１及び図２に対応して示すも
のである。これから明らかなように混成集積回路１の回
路基板２の他方の主面８の第１の外部接続用導体層１８
は半田４２によって親基板３８のグランド導体層３９に
固着されている。また、図３に示す第２及び第３の外部
接続用導体層１９、２０も図４及び図５に示す親基板３
８の導体層４０、４１に半田（図示せず）によって接続
されている。混成集積回路１の外部接続用導体層１８、
１９、２０は回路基板２の他方の主面８にあるので、表
面実装方法によって同時に半田接続することができる。FIGS. 5 and 6 show a state in which the hybrid integrated circuit 1 is arranged on the parent substrate 38, corresponding to FIGS. 1 and 2. FIG. As is clear from this, the first external connection conductor layer 18 on the other main surface 8 of the circuit board 2 of the hybrid integrated circuit 1
Is fixed to the ground conductor layer 39 of the parent board 38 by solder 42. The second and third external connection conductor layers 19 and 20 shown in FIG. 3 also correspond to the parent substrate 3 shown in FIGS.
8 are connected to the conductor layers 40 and 41 by soldering (not shown). The external connection conductor layer 18 of the hybrid integrated circuit 1;
Since 19 and 20 are on the other main surface 8 of the circuit board 2, they can be connected by soldering simultaneously by the surface mounting method.
【００１５】図７〜図１０は、回路基板２に導体層１１
〜２１等を形成する方法を示す。まず、図７に示すよう
に例えば厚さ約０．８ｍｍの回路基板２の一方の主面５
の上に厚さ約１８μｍの銅シートから成る金属シート３
４を貼り付け、貫通孔７を形成したものを用意する。ま
た、貫通孔７に対応した貫通孔２６ｂを有する熱硬化性
樹脂から成る接着シート２６ａを用意し、更に、厚さ約
７０μｍの銅シートから成る金属シート４３を用意す
る。次に、回路基板２と接続シート２６ａと金属シート
４３とを積層し、プレスし、加熱することによって金属
シート４３を回路基板２に接着シート２６ａで固着す
る。また、スルーホール３２を形成する。次に、無電解
メッキと電解メッキを順次に施すことによって図９に示
すように金属シート３４、４３の上及び回路基板２の露
出面に金属メッキ層３５を形成する。これにより貫通孔
７の壁内及びスルーホール３２の壁面の導体層３５及び
底面の金属メッキ層３６も形成される。次に、回路基板
２の一方の主面５及び他方の主面８の選択的エッチング
によって図１〜図３及び図１０に示すように所定パター
ンの導体層１１〜２１を形成する。FIG. 7 to FIG. 10 show that the conductor layer 11 is formed on the circuit board 2.
2 to 21 and the like will be described. First, as shown in FIG. 7, one main surface 5 of a circuit board 2 having a thickness of about 0.8 mm, for example.
Metal sheet 3 comprising a copper sheet having a thickness of about 18 μm
4 to which a through hole 7 is formed is prepared. Further, an adhesive sheet 26a made of a thermosetting resin having a through hole 26b corresponding to the through hole 7 is prepared, and a metal sheet 43 made of a copper sheet having a thickness of about 70 μm is prepared. Next, the circuit board 2, the connection sheet 26a, and the metal sheet 43 are laminated, pressed, and heated to fix the metal sheet 43 to the circuit board 2 with the adhesive sheet 26a. Further, a through hole 32 is formed. Next, by performing electroless plating and electrolytic plating sequentially, a metal plating layer 35 is formed on the metal sheets 34 and 43 and on the exposed surface of the circuit board 2 as shown in FIG. Thereby, the conductor layer 35 on the wall of the through hole 7 and the wall surface of the through hole 32 and the metal plating layer 36 on the bottom surface are also formed. Next, conductor layers 11 to 21 having a predetermined pattern are formed as shown in FIGS. 1 to 3 and 10 by selective etching of one main surface 5 and the other main surface 8 of circuit board 2.
【００１６】本実施例によれば次の効果が得られる。 （イ） 薄型化するために回路基板２の貫通孔７の中に
半導体素子３を配置する時に、導体層１８によって閉塞
された部分２７の上に半導体素子３を置くことができる
ので、半導体素子３の高さ方向の位置決めを容易に達成
することができるばかりでなく、半導体素子３の装着を
容易に達成することができる。 （ロ） 放熱体６が設けられ、これが導体層１８の上に
配置されているので、放熱体６のみでなく、導体層１８
による放熱効果も得ることができる。 （ハ） 導体層１８の貫通孔７を閉塞する部分２７は外
部接続用導体層１８の延長部として形成されているの
で、特別な工程を伴なわずに容易に得ることができる。 （ニ） 親基板３８の導体層３９も貫通孔７の下に配置
される構成であるので、この導体層３９による放熱効果
を得ることができるばかりでなく、半導体素子３の安定
的支持が達成される。 （ホ） 放熱体６を高さ方向のスペーサとして働かせ、
半導体チップ１０の表面の高さ位置を導体層１１、１
２、１３の高さ位置にほぼ揃えているので、ワイヤボン
ディングによりリード線２２、２３、２４を容易に接続
することができる。 （ヘ） 貫通孔７の壁面に導体層２５を設けたので、こ
れによって半導体素子３の電磁及び／又は静電シールド
が達成され、半導体素子３に対するノイズの侵入及びこ
こからのノイズの放射を防ぐことができる。 （ト） 混成集積回路１を親基板３８に対して表面実装
方法で容易に装着することができる。According to this embodiment, the following effects can be obtained. (A) When the semiconductor element 3 is arranged in the through hole 7 of the circuit board 2 to reduce the thickness, the semiconductor element 3 can be placed on the portion 27 closed by the conductor layer 18. Not only can the positioning of the semiconductor element 3 in the height direction be easily achieved, but also the mounting of the semiconductor element 3 can be easily achieved. (B) Since the heat radiator 6 is provided and disposed on the conductor layer 18, not only the heat radiator 6 but also the conductor layer 18
Can also provide a heat radiation effect. (C) Since the portion 27 of the conductor layer 18 that closes the through hole 7 is formed as an extension of the external connection conductor layer 18, it can be easily obtained without any special process. (D) Since the conductor layer 39 of the parent substrate 38 is also arranged below the through-hole 7, not only the heat radiation effect by the conductor layer 39 can be obtained, but also the semiconductor element 3 can be stably supported. Is done. (E) The radiator 6 acts as a spacer in the height direction,
The height position of the surface of the semiconductor chip 10 is set to the conductor layers 11, 1
The lead wires 22, 23, and 24 can be easily connected by wire bonding since they are almost aligned at the height positions of 2 and 13. (F) Since the conductor layer 25 is provided on the wall surface of the through-hole 7, electromagnetic and / or electrostatic shielding of the semiconductor element 3 is achieved, thereby preventing noise from entering the semiconductor element 3 and radiating noise therefrom. be able to. (G) The hybrid integrated circuit 1 can be easily mounted on the mother board 38 by a surface mounting method.
【００１７】[0017]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） 半導体チップをＦＥＴ以外のＩＣチップ、ダイ
オードチップ等にすることができる。 （２） 導体層１８を回路基板２に非固着の金属板から
成る導体層とすることができる。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The semiconductor chip can be an IC chip other than the FET, a diode chip, or the like. (2) The conductor layer 18 can be a conductor layer made of a metal plate that is not fixed to the circuit board 2.
【図１】本発明の実施例の混成集積回路の一部を示す平
面図である。FIG. 1 is a plan view showing a part of a hybrid integrated circuit according to an embodiment of the present invention.
【図２】図１のＡ−Ａ線の切断面を示す図である。FIG. 2 is a view showing a cross section taken along line AA of FIG. 1;
【図３】図１の混成集積回路の一部を示す底面図であ
る。FIG. 3 is a bottom view showing a part of the hybrid integrated circuit of FIG. 1;
【図４】親基板の一部を示す平面図である。FIG. 4 is a plan view showing a part of a parent board.
【図５】親基板に図１の混成集積回路を装着した回路装
置の一部を示す平面図である。FIG. 5 is a plan view showing a part of a circuit device in which the hybrid integrated circuit of FIG. 1 is mounted on a parent substrate.
【図６】図５のＢ−Ｂ線の切断面を示す図である。FIG. 6 is a view showing a cross section taken along line BB of FIG. 5;
【図７】図１の混成集積回路のための回路基板と接着シ
ートと金属シートを示す断面図である。FIG. 7 is a sectional view showing a circuit board, an adhesive sheet, and a metal sheet for the hybrid integrated circuit of FIG. 1;
【図８】回路基板と接着シートと金属シートを一体化し
たものを示す断面図である。FIG. 8 is a cross-sectional view showing a circuit board, an adhesive sheet, and a metal sheet integrated.
【図９】図８のものにスルーホールを形成したものを示
す断面図である。FIG. 9 is a cross-sectional view showing a structure in which through holes are formed in the structure shown in FIG.
【図１０】回路基板の一方及び他方の表面に所定パター
ンの導体層を形成したものを示す断面図である。FIG. 10 is a cross-sectional view showing a circuit board in which a conductor layer having a predetermined pattern is formed on one surface and the other surface.
１ 混成集積回路 ２ 回路基板 ３ 半導体素子 ４ 回路素子 ５ 一方の主面 ６ 放熱体 ７ 貫通孔 ８ 他方の主面 ９ ろう材 １０ 半導体チップ １１〜１７ 導体層 １８ 第１の外部接続用導体層 １９ 第２の外部接続用導体層 ２０ 第３の外部接続用導体層 REFERENCE SIGNS LIST 1 hybrid integrated circuit 2 circuit board 3 semiconductor element 4 circuit element 5 one main surface 6 radiator 7 through hole 8 the other main surface 9 brazing material 10 semiconductor chip 11 to 17 conductor layer 18 first external connection conductor layer 19 Second conductor layer for external connection 20 Third conductor layer for external connection
Claims (3)
路装置であって、 前記回路基板の一方の主面から他方の主面に至る貫通孔
が設けられており、 前記回路基板の一方の主面には前記回路素子を接続する
ための配線導体層が設けられており、 前記回路基板の他方の主面側に前記貫通孔を閉塞するよ
うに他方の主面側の導体層が配設されており、 前記回路素子が前記貫通孔の中に配置され且つ前記貫通
孔を閉塞している他方の主面側の導体層で支持されてお
り、 前記回路素子と前記回路基板の一方の主面上の前記配線
導体層とが導体で接続されている回路装置において、 前記他方の主面側の導体層は、前記絶縁性回路基板の他
方の主面に固着された金属シ−トと該金属シ−トにメッ
キされて成るメッキ層とから構成されており、前記他方
の主面側の導体層の肉厚は前記絶縁性回路基板の肉厚よ
りも小さいことを特徴とする回路装置。1. A circuit device comprising an insulative circuit board and a circuit element, wherein a through hole is provided from one main surface of the circuit board to the other main surface thereof. A wiring conductor layer for connecting the circuit element is provided on the main surface of the circuit board, and a conductor layer on the other main surface side is arranged on the other main surface side of the circuit board so as to close the through hole. Wherein the circuit element is disposed in the through-hole and supported by a conductor layer on the other main surface that closes the through-hole, and one of the circuit element and the circuit board is provided. In a circuit device in which the wiring conductor layer on the main surface is connected by a conductor, the conductor layer on the other main surface is a metal sheet fixed to the other main surface of the insulating circuit board. And a plating layer formed by plating the metal sheet. A circuit device, wherein the thickness of the conductor layer on the main surface side is smaller than the thickness of the insulating circuit board.
面積の表面及び裏面を有する親基板を備えており、 前記親基板の表面に前記回路基板の前記他方の主面側の
導体層を接続するための導体層が形成されており、 前記親基板の前記導体層は前記絶縁性回路基板の前記他
方の主面側の導体層を介して前記貫通孔の実質的に全部
を覆うように形成されていることを特徴とする請求項１
記載の回路装置。2. The semiconductor device according to claim 1, further comprising a parent substrate having a front surface and a rear surface having a larger area than the insulating circuit substrate, and connecting the conductor layer on the other main surface side of the circuit substrate to the front surface of the parent substrate. And the conductor layer of the mother board is formed so as to cover substantially the entire through hole via the conductor layer on the other main surface side of the insulating circuit board. 2. The method according to claim 1, wherein
The circuit device as described.
を有し、前記一方の主面の第１の金属シ−トが貼り付け
られた絶縁性回路基板を用意する工程と、 前記回路基板よりも薄い第２の金属シ−トを用意し、前
記回路基板の前記他方の主面に対して前記貫通孔を閉塞
するように接着する工程と、 次に、メッキによって少なくとも前記第１及び第２の金
属シ−トの露出面に金属メッキ層を形成する工程と、 前記金属メッキ層を伴った前記第１の金属シ−トを所望
のパタ−ンにエッチングして配線導体層を形成する工程
と、 前記金属メッキ層を伴った前記第２の金属シ−トの前記
貫通孔を閉塞する部分の上に回路素子を配置する工程
と、 前記回路素子と前記配線導体層とを導体で接続する工程
とを有していることを特徴とする回路装置の製造方法。3. A step of preparing an insulated circuit board having a through hole extending from one main surface to the other main surface and having the first metal sheet on the one main surface attached thereto. A step of preparing a second metal sheet thinner than the circuit board and bonding the second metal sheet to the other main surface of the circuit board so as to close the through-hole; Forming a metal plating layer on the exposed surfaces of the first and second metal sheets; and etching the first metal sheet with the metal plating layer into a desired pattern to form a wiring conductor layer. Forming a circuit element on a portion of the second metal sheet with the metal plating layer that closes the through hole; and forming the circuit element and the wiring conductor layer. And a step of connecting with a conductor. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10100067A JP3104749B2 (en) | 1998-03-27 | 1998-03-27 | Circuit device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10100067A JP3104749B2 (en) | 1998-03-27 | 1998-03-27 | Circuit device and method of manufacturing the same |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7171406A Division JP3061102B2 (en) | 1995-06-14 | 1995-06-14 | Circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10247704A true JPH10247704A (en) | 1998-09-14 |
| JP3104749B2 JP3104749B2 (en) | 2000-10-30 |
Family
ID=14264128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10100067A Expired - Fee Related JP3104749B2 (en) | 1998-03-27 | 1998-03-27 | Circuit device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3104749B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009076750A (en) * | 2007-09-21 | 2009-04-09 | Daikin Ind Ltd | Module |
| JP2013009017A (en) * | 2012-10-12 | 2013-01-10 | Daikin Ind Ltd | Module |
| WO2016121340A1 (en) * | 2015-01-29 | 2016-08-04 | 日本電気株式会社 | High frequency module and method for manufacturing high frequency module |
| JP2017059757A (en) * | 2015-09-18 | 2017-03-23 | 日本電気株式会社 | Semiconductor device and semiconductor device manufacturing method |
| JP2018006463A (en) * | 2016-06-29 | 2018-01-11 | 京セラ株式会社 | Substrate for mounting semiconductor device and semiconductor device |
| JP2018073992A (en) * | 2016-10-28 | 2018-05-10 | 京セラ株式会社 | Semiconductor element mounting substrate and semiconductor device |
| WO2022145250A1 (en) * | 2021-01-04 | 2022-07-07 | ローム株式会社 | Semiconductor apparatus |
-
1998
- 1998-03-27 JP JP10100067A patent/JP3104749B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009076750A (en) * | 2007-09-21 | 2009-04-09 | Daikin Ind Ltd | Module |
| JP2013009017A (en) * | 2012-10-12 | 2013-01-10 | Daikin Ind Ltd | Module |
| WO2016121340A1 (en) * | 2015-01-29 | 2016-08-04 | 日本電気株式会社 | High frequency module and method for manufacturing high frequency module |
| JP2017059757A (en) * | 2015-09-18 | 2017-03-23 | 日本電気株式会社 | Semiconductor device and semiconductor device manufacturing method |
| JP2018006463A (en) * | 2016-06-29 | 2018-01-11 | 京セラ株式会社 | Substrate for mounting semiconductor device and semiconductor device |
| JP2018073992A (en) * | 2016-10-28 | 2018-05-10 | 京セラ株式会社 | Semiconductor element mounting substrate and semiconductor device |
| WO2022145250A1 (en) * | 2021-01-04 | 2022-07-07 | ローム株式会社 | Semiconductor apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3104749B2 (en) | 2000-10-30 |
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