JPH10242309A - Nonvolatile semiconductor memory cell array and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory cell array and manufacturing method thereof. SOLUTION: The cell has a local source electrode 38 in addition to a conventional floating gate 33, a control gate 34, a cell source electrode 36 and a cell drain electrode 37, thereby improving the device operation and reducing the no. of contact windows 40 of the cell array. This is effective to reduce the size of the cell array. One isolated region 39 is added in two metal lines, respectively, thereby avoiding crosstalk after reducing the size of the memory array and to improve its reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory cell array.
emicon conductor Memory Cell
Ally) and its manufacturing method: In particular, by having a design with a kind of local source increased, the array coupling ratio (cou) is increased.
The present invention relates to an apparatus having an increased pling ratio and a method for producing the same.

[0002]

2. Description of the Related Art FIG. 1 is a sectional view of a conventional stacked nonvolatile semiconductor memory cell, and a manufacturing method thereof is as follows. That is, first, a tunnel oxide layer 2 and a first polysilicon layer 3 are formed on the semiconductor wafer 1, and then a necessary pattern is defined by using a conventional lithography and etching technique. Further, on this pattern, the first dielectric layers 4 and 1
A second layer of polysilicon 5 is deposited. Usually,
The composition of the first dielectric layer 4 has an ONO sandwich structure of silicon oxide / nitrated silicon / silicon oxide. Thus, the gate electrode of this memory cell is formed.
Among them, the gate electrode further includes a floating gate 3A.
And the control gate 5A.

Then, necessary impurity ions are implanted into a wafer region not covered with the gate electrode to form a source electrode 6.
Then, a second dielectric layer 8 is further deposited (usually, the second dielectric layer is composed of silicon oxide or nitrated silicon). Finally, lithography and etching techniques are performed. Using one contact window 9 (contact) above the drain electrode 7
(window) was opened, and the structure of the nonvolatile semiconductor memory cell was completed as described above.

Next, FIG. 2 is a layout diagram of a conventional stacked nonvolatile semiconductor memory cell, and an area indicated by reference numeral 10 in the figure is an isolation area.

As can be seen from the above description, the traditional stacked nonvolatile semiconductor memory cell design requires that one contact window be opened between each two nonvolatile semiconductor memory cells, and thus the memory The size of the cell was relatively limited. On the other hand, the silicon substrate (S region in FIG. 2) may be subjected to a trench in the already etched portion of the first polysilicon layer in a self-etching process, thereby reducing the continuity of the source line. The effect has occurred. In addition, as device dimensions are continually shrinking, the crosstalk between two metal lines becomes very close.
alk) is more likely to occur. Thus, the traditional non-volatile semiconductor memory cells described above have drawbacks, which have affected the reliability of the device.

[0006]

SUMMARY OF THE INVENTION The present invention overcomes the above disadvantages and increases its array coupling ratio by providing a single local source pole design compared to traditional designs. An object of the present invention is to provide a kind of nonvolatile semiconductor memory cell array and a method for manufacturing the same.

Another object of the present invention is to provide a kind of nonvolatile semiconductor memory cell array design which can reduce the size of the memory cell and increase the density without having to open the contact window of the drain electrode. I have.

Another object of the present invention is to provide a kind of nonvolatile semiconductor memory cell array which has a simple structure and is easy to manufacture.

It is still another object of the present invention to provide a nonvolatile semiconductor memory cell array which is easy to operate at a low operating voltage and is easy to carry.

According to the present invention, furthermore, one isolation region is additionally provided in two metal wires, so that even if the device size is reduced, crosstalk does not occur and the reliability of the device can be improved. It is an object of the present invention to provide a nonvolatile semiconductor memory cell array.

[0011]

According to a first aspect of the present invention, there are provided a plurality of floating gates forming rows and columns on a silicon substrate, and a plurality of floating gates formed in columns on the floating gates and continuously arranged. A control gate, a plurality of local bit lines located on the silicon substrate in a row, and a plurality of cells located in the silicon substrate below the local bit line, intersecting the row and being separated by a floating gate. A plurality of local source electrodes, which are arranged in a row intersecting with the source and cell drain electrodes and the columns and the cell drain electrodes, are located in the silicon substrate, are located in the rows and are located between the local bit lines, and their existence. A nonvolatile semiconductor memory cell array comprising a plurality of isolation regions for isolating a cell drain electrode and a local source electrode adjacent to each other in a row to be formed.

According to a second aspect of the present invention, there is provided the nonvolatile semiconductor memory cell array according to the first aspect, wherein all of the local source poles are connected to a common local source pole.

The invention of claim 3 provides (A) a p-type silicon substrate. (B) forming a field oxide layer region for isolation on the p-type silicon substrate. (C) one tunnel oxide layer and a second oxide layer. (D) Form a polysilicon floating gate pattern using lithography and etching techniques (E) Further, a first dielectric layer, metal silicide Forming a control gate pattern on the floating gate after successively depositing a layer and a second dielectric layer. (F) In the selected region of the p-type silicon substrate described above, n
Forming cell source electrode and cell drain electrode by implanting type ions (G) Depositing one layer of cell source electrode and drain electrode oxide layer (H) Depositing one more relatively thick oxide layer and vertical anisotropy Forming a spacer by plasma etching (I) Depositing a single conductive layer and simultaneously forming a local bit line and a local source electrode using lithography and etching techniques, including the above steps (A) to (I). Thus, a method for manufacturing a nonvolatile semiconductor memory cell is provided.

According to a fourth aspect of the present invention, there is provided the method for manufacturing a nonvolatile semiconductor memory cell according to the third aspect, wherein the thickness of the first polysilicon layer is set to be between 500 and 2000 angstroms.

[0015] The invention according to claim 5, wherein the thickness of the metal silicide layer is between 1000 and 3000 angstroms.
According to a third aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory cell.

According to a sixth aspect of the present invention, the first dielectric layer has a sandwich structure of silicon oxide / nitrated silicon / silicon oxide, each of which has an equal thickness of 100 to 300 angstroms. This is a method for manufacturing a volatile semiconductor memory cell.

According to a seventh aspect of the present invention, the n-type ions to be implanted are arsenic ions, the ion implantation energy amount is between 20 to 80 keV, and the implantation ion amount is 1E15 to 5
The method for manufacturing a nonvolatile semiconductor memory cell according to claim 3, wherein the method is between E15 ions / square centimeter.

The invention according to claim 8 is the method for manufacturing a nonvolatile semiconductor memory cell according to claim 3, wherein the material of the conductive layer is any one of polysilicon, tungsten, tungsten silicon, and titanium silicon.

[0019]

FIG. 3 is a layout diagram of a preferred embodiment of a nonvolatile semiconductor memory cell array according to the present invention. The cell array includes an upper selection line 31 for performing a cell address selection function and an upper selection line 31 for performing a cell address selection function. A plurality of floating gates 33 arranged in rows and columns on the silicon substrate, a plurality of control gates 34 arranged in columns on the floating gates 33 and continuously arranged, and A plurality of local bit lines 35 (Local Bit Lines) located on the substrate and forming a row
a plurality of cell source poles 36 and cell drain poles 37 located below the local bit line 35 and forming intersecting rows, both of which are separated by a floating gate 33; A plurality of local source poles 38, which are arranged in a row interlaced with the drain poles 37, are located between the local bit lines 35 in a row, and separate the adjacent cell drain poles 37 and local source poles 38 in the existing column. A plurality of isolated regions 39, a local word line and an external data line (data line) (not shown)
A plurality of contact windows 40, or more.

As shown in FIG. 4, the common local source line 32 has one common lower selection 30 (botto).
m select), in which WL (0), W
L (2),..., WL (n−2), WL (n−1) are word lines, and Data (0),.
(M-1) is a data line, and the word line and the data line are arranged so as to intersect to form an array structure.

FIG. 5 is a layout diagram of another nonvolatile semiconductor memory cell array of the present invention. The structure of this embodiment is basically the same as that shown in FIG. 3, except that the local source pole is separated. As shown in FIG. 6, in this embodiment, each local source pole 38
Are one independent control line BS (0),...
BS (m-1).

FIG. 7 is a sectional view of the cell of the present invention cut in the direction of the word line BB. The starting material of the present invention is a p-type silicon substrate 41. First, an isolation field oxide layer 42 and a tunnel oxide layer 46 are formed on the p-type silicon substrate 41.
Subsequently, a layer of photoresist 43 is applied over the field oxide layer 42 and the tunnel oxide layer 46, and then an active region and an isolation region are defined using lithography and etching techniques. In the active region, one cell channel and one cell source / drain electrode (cell source / drain) are provided in the active region.
drain).

The above-mentioned field oxide layer 42 is formed by using a thermal oxidation method (Thermal Growth).
It is formed by oxidizing silicon atoms on the surface of the mold silicon substrate 41. The temperature of the thermal oxidation is between 1100 and 1200 ° C. to form an oxide layer between 3000 and 6500 angstroms thick. The above-described tunnel oxide layer 46 is also formed by a thermal oxidation method, and has a thickness between 50 and 100 angstroms.

FIG. 8 is also a sectional view of the cell of the present invention cut in the direction of the word line BB. Subsequently, after a first polysilicon layer 47 is deposited, a floating gate pattern is defined using lithography and etching techniques,
Further, a first dielectric layer 49 having a silicon oxide / nitrated silicon / silicon oxide ONO sandwich structure is deposited on the pattern. Each of them has a thickness between 100 and 300 Å, and a polycide layer 51 and a second dielectric layer 53 are sequentially deposited.
Finally, again using lithography and etching technology,
A control gate is defined and a word line pattern is formed.

The above-mentioned first polysilicon layer 47 is usually
Formed by low pressure chemical vapor deposition method of simultaneously doping the polysilicon formation (LPCVDF), the reaction gas with _{(15% PH 3/85%} SiH 4) (5% PH 3/9
A gas mixture of 5% N ₂ ), a reaction pressure of 1 torr, a reaction temperature of about 550 ° C., and a thickness between 500 and 2000 Å. The first polysilicon layer is plasma-etched using magnetic field-enhanced reactive ion etching (MARIE) or electron cyclotron resonance (ECR) plasma etching, or a conventional reactive ion etching (RIE) technique. In the area of integrated circuit technology, magnetic field enhanced reactive ion etching (MARIE) is generally used, and the reaction gas is a mixture of Cl ₂ , SF ₆ and HBr. The above-mentioned polycide layer 51 is usually made of metal silicide such as tungsten silicon or titanium silicon formed by a deposition method, and has a thickness between 1000 and 3000 angstroms. The above-mentioned second dielectric layer 53 is made of silicon oxide or nitrated silicon (Si ₃ N ₄ ) usually formed by using low pressure chemical vapor deposition (LPCVD),
Its thickness is between 1000 and 3000 angstroms.

9 to 13 are cross-sectional views cut in the direction of the local bit line CC. First, FIG. 9 shows a doping step of a source electrode and a cell drain region of a flash or EPROM memory cell. Usually, arsenic (As ⁷⁵ ) ions 55 are implanted by ion implantation, and the ion implantation energy amount is from 20. It is between 80 keV and the amount of implanted ions is between 1E15 and 5E15 ions / cm 2.

Thereafter, as shown in FIG. 10, a single cell source / drain oxide layer 57 (cell source) is formed above the region of the cell source electrode 36 and the drain electrode 37.
/ Drain oxide), and a spacer oxide layer 59 is deposited as shown in FIG. The above-described step of forming the cell source and drain oxide layers 57 is also an operation of mixing impurities in the source and the drain, and is performed under a pure nitrogen environment at a temperature of about 900 to 1000 ° C.
The process proceeds for about 30 minutes, and the impurities of the source and the drain are accurately distributed as designed. The above-mentioned spacer oxide layer 59 is usually made of tetraethoxyl silane (TEOS) formed by plasma enhanced chemical vapor deposition (PECVD),
Its thickness is between 2000 and 4000 angstroms.

Next, as shown in FIG. 11, first, a photoresist pattern 61 is formed using lithography technology, the oxide layer above the source electrode is protected, and an extra layer is formed using vertical anisotropic plasma etching technology. The oxide layer is removed to form an oxide layer 59 that supports the spacer. The oxide layer is usually etched by magnetic field enhanced reactive ion etching (MARIE), and the reaction gas is usually CF ₄ , CHF ₃ and Ar.

Finally, FIGS. 12 and 13 show that a local bit line (Local Bit Line) and a local source electrode are formed at the same time, and one conductive layer 63 is formed to a thickness of 2
After forming between 000 and 4000 angstroms, local bit lines and local source poles are defined using lithography and etching techniques. The material of the above-mentioned conductive layer 63 is polysilicon, tungsten or a metal silicide such as tungsten silicon or titanium silicon. FIG. 12 is a sectional view taken along a local bit line, and FIG. 13 is a sectional view taken along a local source pole.

Finally, the operation principle of the cell of the present invention will be described with reference to Table 1 below. When the cell performs a programming operation, the local bit line (ie, cell drain pole 37) portion is always at a positive low potential (LV) and the word line (ie, control gate 34) portion is at a negative high potential (-). HV), the electrons are floating gate 33
Then, it enters the cell drain electrode 37. This is as shown in part (A) of FIG. Conversely, when the cell performs an erase operation, the source and the local bit line (ie, the cell drain electrode) are both at 0 V, the word line (control gate) is at a high potential (HV), and electrons are floating from the channel. It enters the gate 33 and erases the original data. This is as shown in FIG. When this cell performs a read operation, both the word line (control gate) and the cell drain electrode have a positive low potential (+ L
V).

[Table 1]

[0031]

As described above, the nonvolatile semiconductor memory cell array and the method of manufacturing the same according to the present invention have a design in which a traditional floating gate, control gate, cell source electrode, and cell drain electrode are formed. Source poles have been added, thereby improving the operation of the device, and this design can reduce the number of contact windows in the cell array, which is effective in reducing the size of the cell array. In this case, one isolation region is additionally provided in the metal line, thereby preventing the occurrence of crosstalk after the size reduction of the cell array and improving its reliability.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a traditional stacked nonvolatile semiconductor memory cell.

FIG. 2 is a layout diagram of a traditional stacked nonvolatile semiconductor memory cell.

FIG. 3 is a layout diagram of a nonvolatile semiconductor memory cell array having a common local source pole according to an embodiment of the present invention.

FIG. 4 is an equivalent electric circuit diagram of FIG. 3;

FIG. 5 is a layout diagram of a nonvolatile semiconductor memory cell array having independent local source poles according to another embodiment of the present invention.

6 is an equivalent electric circuit diagram of FIG.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a nonvolatile semiconductor memory cell of the present invention.

FIG. 8 is a cross-sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory cell of the present invention.

FIG. 9 is a cross-sectional view illustrating a method for manufacturing a nonvolatile semiconductor memory cell of the present invention.

FIG. 10 is a sectional view showing the method for manufacturing the nonvolatile semiconductor memory cell of the present invention.

FIG. 11 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory cell of the present invention.

FIG. 12 is a sectional view showing the method for manufacturing the nonvolatile semiconductor memory cell of the present invention.

FIG. 13 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory cell of the present invention.

FIG. 14 is an operation display diagram of the nonvolatile semiconductor memory cell of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 31 upper selection line 32 common local source line 33 floating gate 34 control gate 35 local bit line 36 cell source electrode 37 cell drain electrode 38 local source electrode 39 isolation region 40 contact window 30 common lower selection 41 p-type silicon substrate 42 field oxide layer Reference Signs List 46 tunnel oxide layer 43 photoresist 47 first polysilicon layer 49 first dielectric layer 51 polycide layer 53 second dielectric layer 57 cell source and drain oxide layer 59 spacer oxide layer 61 photoresist pattern 63 conductive layer

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 27/115

Claims (8)

[Claims] A plurality of floating gates arranged in rows and columns on a silicon substrate; a plurality of control gates arranged in columns on the floating gates and continuously arranged; and a plurality of control gates arranged in a row on the silicon substrate. A plurality of local bit lines, a plurality of cell source poles and a plurality of cell drain poles located in the silicon substrate below the local bit lines and interleaved and separated by a floating gate. A plurality of local source poles arranged in a row intersecting with the cell drain pole, and a plurality of local source poles located in the silicon substrate, located between the local bit lines, and adjacent cell drain poles and local sources in the existing column. A non-volatile semiconductor memory cell array comprising a plurality of isolated regions for separating poles. 2. The nonvolatile semiconductor memory cell array according to claim 1, wherein all of the local source poles are connected to a common local source pole. (A) providing a p-type silicon substrate; (B) forming a field oxide layer region for isolation on the p-type silicon substrate; and (C) forming one tunnel oxide layer and a first polysilicon layer. (D) forming a pattern of a polysilicon floating gate by using lithography and etching techniques; (E) further forming a first dielectric layer, a metal silicide layer, and a second dielectric layer After the layers are continuously deposited, a control gate pattern is formed on the floating gate. (F) In the selected region of the p-type silicon substrate described above, n
Forming cell source electrode and cell drain electrode by implanting type ions (G) Depositing one layer of cell source electrode and drain electrode oxide layer (H) Depositing one more relatively thick oxide layer and vertical anisotropy Forming a spacer by plasma etching (I) Depositing a single conductive layer and simultaneously forming a local bit line and a local source electrode using lithography and etching techniques, including the above steps (A) to (I). A method for manufacturing a nonvolatile semiconductor memory cell. 4. The method of claim 3, wherein the thickness of the first polysilicon layer is between 500 and 2000 angstroms. 5. The thickness of the metal silicide layer is from 1000 to 3
The method of claim 3, wherein the non-volatile semiconductor memory cell is between 2,000 Å. 6. The non-volatile semiconductor memory cell according to claim 3, wherein the first dielectric layer has a sandwich structure of silicon oxide / nitrated silicon / silicon oxide, each of which has an equal thickness of 100 to 300 Å. Manufacturing method. 7. An n-type ion to be implanted is an arsenic ion,
4. The method for manufacturing a nonvolatile semiconductor memory cell according to claim 3, wherein the ion implantation energy is between 20 and 80 keV, and the ion implantation is between 1E15 and 5E15 ions / cm 2. 8. The method for manufacturing a nonvolatile semiconductor memory cell according to claim 3, wherein a material of the conductive layer is any one of polysilicon, tungsten, tungsten silicon, and titanium silicon.