JPH10239709A - Liquid crystal display device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower the electric resistance, to assure the ease of etching, and to prevent the disconnection, etc. due to a film stress, by forming an alloy layer of Cr and Mo as a conductor layer, forming an oxidized film on its surface, and incorporating Mo therein at a prescribed ratio to Cr. SOLUTION: A gate line GL is formed of a single layer of conductive film g1. The alloy layer of the Mo and Cr formed by sputtering is used as the conductive film g1. An oxidized film OX (contg. Cr2 O3 , CrO2 , MoO2 , MoO3 , CrMoO4 , etc.) of the alloy layer is formed thereon. The Mo is incorporated at 20 to 55wt.% of the Cr into the alloy layer. The first conductive film d1 at the data line DL is formed of the alloy layer of the Mo and Cr similarly to the gate line GL and the oxidized film OX of the alloy layer is formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an active matrix type liquid crystal display device having a conductor layer structure with high processing accuracy suitable for high definition and a method of manufacturing the same.

[0002]

2. Description of the Related Art For example, in an active matrix type liquid crystal display device, a liquid crystal side surface of one of a pair of transparent substrates arranged to face each other via a liquid crystal extends in the x direction and extends in the y direction. A pixel region is formed in each region surrounded by a scanning signal line arranged side by side and a video signal line extended in the y direction and insulated from the scanning signal line and arranged in the x direction.

Each of these pixel regions has a thin film transistor turned on by a scanning signal from a scanning signal line and a transparent pixel electrode to which a video signal from a video signal line is applied via the turned on thin film transistor. Have been.

In this case, a signal wiring layer formed on a transparent substrate, such as a scanning signal line and a video signal line, is formed by selectively etching a conductive film formed of an appropriate material on the surface of the transparent substrate using a photolithography technique. It is formed according to a predetermined pattern by a method.

In recent years, it has become known that alloys of Cr (chromium) and Mo (molybdenum) are used as materials for these signal wiring layers.

For example, Japanese Unexamined Patent Publication No. Hei 4-20930 (hereinafter referred to as Document 1) discloses that Al (aluminum)
Or a laminate of an Al alloy and a Mo alloy,
A conductor layer structure is disclosed in which the alloy contains 0.5 to 10% by weight (wt%) of Cr (for this reason, Mo contains 90 to 99.5% by weight with respect to Cr).

In Japanese Patent Application Laid-Open No. 4-24925 (hereinafter referred to as Document 2), Mo is a main component and at least 0.5 to 10 wt% of Cr (also in this case, Mo is also referred to as Mo).
Is contained in 90 to 99.5 wt% with respect to Cr)
A conductor layer structure is disclosed.

In Japanese Patent Application Laid-Open No. Hei 7-301822 (hereinafter referred to as Document 3), as described in the third column from the 30th line to the 35th line, Mo is 15% lower than Cr. To 85 atomic percent atom% (25 to 91 w
(corresponding to t%) is disclosed.

This is because it has been found that when an alloy layer of Mo and Cr is used, since it has low resistance and low stress, it is extremely effective as a wiring material for a large screen.

[0010]

However, when each signal line is formed by selective etching of such an alloy layer of Mo and Cr by photolithography, the signal line is not formed in a predetermined pattern. It has been pointed out that the line width is reduced, and that the side walls thereof are formed so as to be formed.

That is, a mask for selectively etching the alloy layer of Mo and Cr is formed by selectively exposing and developing a photoresist film formed on the surface of the alloy layer. It was confirmed that the adhesion to the alloy layer was not sufficient.

For this reason, when the alloy layer of Mo and Cr is etched with an appropriate etchant using the mask,
The etching solution permeates the interface between the alloy layer and the mask, and an excessive etching action acts on the alloy layer, thereby causing the above-mentioned adverse effects.

Further, it has been found that such an adverse effect is found not only in the alloy layer of Mo and Cr but also in the metal layer made of Mo.

The present invention has been made in view of such circumstances, and an object of the present invention is to perform selective etching by a photolithography technique capable of forming a conductive layer composed of an alloy layer of Mo and Cr in a predetermined pattern. It is to provide a conductor layer to be formed.

Another object of the present invention is to provide a conductor layer formed by selective etching by photolithography, which can form a conductive layer made of Mo in a predetermined pattern.

Another object of the present invention is to provide a conductive layer structure formed of Cr itself and having a film stress of 1000 or less.
This is considered to remove the adverse effects such as disconnection caused by this film stress.

In this case, when the film stress of the conductor layer structure of the alloy layer of Mo and Cr is set to zero or a value close to zero, the electric resistance is low, but the etching rate is low and the pattern workability is low. Bad things are confirmed.

However, even if the film stress of the conductor layer structure is not necessarily set to zero or a value very close to it, if the underlying layer forming the conductor layer structure is flat without irregularities, or even if there is irregularity, By taking various simple measures, it has been found that the harmful effects such as disconnection can be solved, the electric resistance can be reduced, and the easiness of etching can be ensured.

Therefore, the present invention has been made in view of such circumstances, and it is an object of the present invention to reduce the electric resistance and ensure the easiness of etching, and to prevent disconnection due to film stress. It is an object of the present invention to provide a conductor layer structure that is not allowed to be caused.

[0020] Incidentally, there is a portion in other references in Reference 3 that the film stress of the conductor layer structure can be made almost zero.
As described in column 35, lines 39-39), "in practical applications,... Implemented on conductive lines containing 40 to 60 atomic percent (55 to 75 wt%) molybdenum." It has been confirmed by the present inventors that this should be the case.

[0021]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention basically uses an alloy layer of molybdenum and chromium as a conductor layer. Is characterized in that an oxide film is formed by subjecting the surface to an oxidation treatment.

Here, performing the oxidizing treatment means excluding an oxide film spontaneously formed on the conductor layer, and means that an oxide film is actively formed on the conductor layer. .

It has been found that by forming an oxide film of the conductive layer on the surface of the conductive layer thus formed, it is possible to sufficiently secure the adhesion to the photoresist film.

Therefore, when the conductive layer is selectively etched according to a desired pattern using the photoresist film as a mask, the etchant does not permeate the interface between the conductor layer and the photoresist film. A conductive layer can be formed along the pattern of the mask.

Further, the present invention basically comprises an alloy layer of Cr and Mo formed on a substrate, wherein Mo is a C
20 to 55 wt% with respect to r.

Thus, the content ratio of Mo to Cr is 2
The reason why the above object can be achieved by setting the content to 0 to 55 wt% will be described below.

First, FIG. 12 shows that a conductive layer made of an alloy layer of Cr and Mo is formed on the main surface of a transparent substrate used as an envelope of a liquid crystal display device by a sputtering method.
FIG. 4 is a graph showing the specific resistance (μΩcm) of each conductive layer when the Mo is formed by changing the composition ratio (wt%) of Mo as shown by the plot in the figure.

In this graph, a sputtering device actually used in the manufacture of a liquid crystal display device was used, the power was 6500 W, and the pressure in the bell jar was 1.5.
mTorr, the temperature of the transparent substrate was 130 ° C., and the film thickness was 2
The measurement was performed by forming a 00 nm conductive layer.

As is apparent from the figure, the content of Mo to Cr is 20 to 55 wt%, preferably 30 to 55 wt%.
It is clear that by setting the content in the range of wt%, the specific resistance can be significantly reduced, as apparent from comparison with the content in the surrounding area. For example, diagonal 12-1
On a 3 inch screen, it is known that the specific resistance of the gate line material is sufficient if the sheet resistance is about 0.6 ohm / square. If the upper limit of the film thickness is 350 nm, it is about 22 μΩcm or less. Is fine.

FIG. 13 is a graph showing a change in the etching rate (nm / s) of each conductive layer formed under the same conditions as in FIG. In this case, as an etching solution, ceric ammonium nitrate (15 wt.
%), An aqueous solution of hydrogen peroxide (5 wt%) and the rest were pure water, and the temperature was 49 ° C.

As is clear from the figure, when the content ratio of Mo to Cr is in the range of 30 to 55 wt%, the etching rate can be 0.7 to 2 nm / s, and the etching processability is sufficient. It will be a satisfactory range.

FIG. 14 shows a gate Cr pattern without a taper and a stepped base layer made of a laminated film of an SiN insulating film and an a-Si semiconductor film, and then an alloy of Cr and Mo with a different composition formed thereon. This is a result of forming a conductor layer composed of layers under the same conditions as in FIG. 12, forming a stripe pattern that can cross over the gate Cr pattern at right angles, and measuring the crossover resistance. From this figure, it can be seen that the content ratio of Mo to Cr should be in the range of 30 to 80 wt% in order to make the overriding resistance ratio 1.2 or less. That is, when combined with FIG. 15, the film stress becomes -20.
It is understood that when the pressure is set to 0 to 200 MPa, an increase in resistance to overcoming can be suppressed.

FIG. 15 is a graph showing the change in the film stress (MPa) of each conductor layer formed under the same conditions as in FIG.

As can be seen from the figure, by setting the content ratio of Mo to Cr in the range of 20 to 55 wt%, the film stress cannot be reduced to zero, but a value close to that, that is, 500 to 100 MPa. Will be able to

It has been confirmed that disconnection due to film stress in the conductor layer can be sufficiently prevented even when the absolute value of the film stress is in the range of 500 to 100 MPa, for example, when formed on a flat substrate surface. ing.

The disconnection of the conductor layer caused by the film stress in the above range is particularly problematic, for example, at a step in a crossing portion of the conductor layer when the conductor layer is crossed with another conductor layer.

However, the disconnection at the step portion over the step is made by making the step portion a gentle step, for example, by forming a taper which widens the side wall surface of the other conductive layer toward the substrate surface side. Measures can be easily taken. That is, by forming a taper having a divergent width of about 70 degrees on the gate, the film stress can be reduced from -200 to -5.
The over-resistance ratio was able to be suppressed to 1.2 or less in the range of 00 MPa.

As described above, the absolute value of the film stress is 500 to 1
The portion where the conductor layer in the range of 00 MPa causes adverse effects such as disconnection is not over the entire conductive layer,
Since it is only in some special parts, in this part, it is solved by taking some other simple means, and at the same time, it is intended to ensure low resistance of the conductive layer and easy etching processing Things.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a conductor layer structure according to the present invention is applied to an active matrix liquid crystal display device will be described below with reference to the drawings.

FIG. 1 is a diagram showing a plane pattern of each layer constituting the TFT substrate TFTSUB, and shows one pixel and its surrounding area. FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. 1, and FIG. 3 is a cross-sectional view taken along line 3-3 of FIG.

The display panel includes a TFT substrate TFTSUB in which a thin film transistor, a pixel electrode ITO (Indium-Tin-Oxide) 1, various wirings and the like are formed on one surface of a transparent glass substrate SUB1, and another TFT substrate. The transparent glass substrate SUB2 includes an opposing substrate OPSUB in which a common electrode ITO2, a color filter FIL, and the like are formed on one surface of the transparent glass substrate SUB2, and a liquid crystal layer LC in which a gap between the opposing substrates is filled.

An image signal voltage is applied between the transparent conductive layer ITO1 and the common electrode ITO2 to control the electro-optical state of the liquid crystal layer LC between both electrodes, thereby changing the light transmission state of this portion of the display panel. And a predetermined image is displayed.

Opposite substrate OPSUB side of liquid crystal panel or TF
A backlight is installed on the TFT substrate TFTSUB side, and light transmitted through the pixel portion of the liquid crystal panel is observed from the side opposite to the backlight.

<< TFT Substrate >> Next, the structure of the TFT substrate TFTSUB will be described in detail with reference to FIGS. A plurality of parallel gate lines (scanning signal lines or horizontal signal lines) GL and a plurality of parallel data lines (video signal lines or vertical signal lines) formed so as to intersect with the gate lines are formed on the surface of the TFT substrate. ) DL is provided. A region surrounded by two adjacent gate lines GL and two adjacent data lines DL is a pixel region, and a transparent conductive film ITO1 is formed almost entirely over this region.
A thin film transistor (a region shown by a broken line in FIG. 1) as a switching element is formed in a convex portion (a convex portion in FIG. 1) of a gate line facing each pixel electrode, and its source electrode SD1 is Connected to pixel electrode. The scanning voltage applied to the gate line GL is applied to the gate electrode of the TFT constituted by a part of the gate line,
T is turned on, and the image signal supplied to the data line DL at that time is written to the transparent conductive film ITO1 via the drain electrode (part of the data line DL in this embodiment) and the source electrode SD1.

<< Gate Line GL >> As shown in FIGS. 2 and 3, in the first embodiment, the gate line GL is formed of a single-layer conductive film g1. The thickness of the conductive film g1 is 60
An alloy layer of Mo and Cr formed by sputtering of 0 ° or more (about 2000 ° in Example 1) is used,
Further, the oxide film OX (Cr ₂ O ₃ , CrO ₂ , Mo) of the alloy layer is formed on the surface (defined as a concept excluding the side surface).
O ₂ , MoO ₃ , CrMoO _4, etc.).

Here, the alloy layer is made of Mo with respect to Cr.
Contains molybdenum of 20 to 55 wt% or more, and has an oxide film OX formed on its surface.
Contains oxygen of 40 atomic% or more (atom%).

Such a gate line GL is formed through the following steps.

First, over the entire surface of the transparent substrate SUB1,
Mo, for example, by sputtering or evaporation
A film composed of an alloy layer of Cr and Cr is formed, and then the surface of the film is subjected to an oxidation treatment.

The oxidation treatment method may be, for example, any of an oxygen plasma method (oxygen ashing method), a surface radiation heating method, a substrate heating method, an ultraviolet irradiation treatment method, an ozone treatment method, and the like. It is necessary to actively form an oxide film containing much more oxygen than a specific oxide film.

The oxide film OX formed as described above
Is formed as one containing 40 atomic% or more of oxygen.

Thereafter, a photoresist is applied to the entire surface of the film made of the alloy layer of Mo and Cr to form a uniform photoresist film, for example, a positive photoresist film. In this example, AZ TFP650-H2 (trade name: manufactured by Hoechst Hechist) was used as the photoresist film.

Then, the photoresist film is cured by baking. As this baking, for example, first, pre-baking is performed at 110 ° C. for 160 seconds, and then,
Post bake is performed at 120 ° C. for 280 seconds.

In this case, it has been confirmed that the photoresist film is formed on the upper surface of the film (an alloy layer of Mo and Cr) having the oxide film OX formed on the surface thereof, with a higher adhesion than before. ing. It is considered that this is because oxygen in the oxide film OX acts as a medium to sufficiently bond carbon in the photoresist film and metal in the film.

Next, the photoresist film is selectively exposed through a photomask on which a pattern of the gate line GL is drawn.

Then, the photoresist film subjected to the selective exposure is developed. As a developer in this case, for example, an organic alkali NMD-3 PH12 (trade name: manufactured by Tokyo Ohkasha)
Was used.

In this case, it has been confirmed that the photoresist film remaining by the development still maintains the adhesion to the film.

Next, using the remaining photoresist film as a mask, the coating (an alloy layer of Mo and Cr) exposed from the photoresist film is selectively etched.
In this case, as an etching solution, ceric ammonium nitrate (15 wt%), perchloric acid (5 wt%) and water (80 wt%)
Was carried out at a liquid temperature of 40 ° C. using a mixture of the above (manufactured by Tokyo Ohkasha).

Thereafter, the photoresist film is removed with an appropriate removing solution, whereby the gate line GL is formed in the pattern shown in FIG.

In this case, an oxide film OX is still formed on the surface of the gate line GL, but this oxide film OX is a low-resistance conductive oxide film, as described later in detail. For this reason, it is necessary to leave it as it is without removing it (in the case of removing it, the number of steps increases).

FIG. 18 shows the amount of side etching with respect to the over-etching rate of the gate line GL formed in this manner, and the characteristics shown by white circles in FIG. 18 are obtained. For comparison, the characteristics in the case where the oxide film OX is not formed are indicated by squares, but it is clear that a desired wiring pattern can be obtained without a significant side etch compared to this case. .

Here, in the gate line GL having such a configuration, the oxidation state of the oxide film OX formed on the surface thereof was examined using a so-called X-ray photoelectron spectrometer.

FIGS. 16A and 16B are graphs showing the results, and the analysis conditions and the like are shown in FIG. 16C.

FIGS. 16 (a) and (b) show, respectively,
When the binding energy is changed from a small state to a large state, the characteristic between 220 eV and 240 eV and 560
It shows characteristics between eV and 590 eV.

When the surface of the gate line GL is not subjected to the oxidizing process, the oxidizing process is performed in contrast to the characteristics shown in FIG. 16A and FIG. It has been found that when applied, the black dots have characteristics of continuous dots.

In FIGS. 16A and 16B, reference numeral 9 denotes a substrate not subjected to oxygen treatment, 10 denotes a substrate subjected to oxygen ashing, 11 denotes a peak of Mo3d5 / 2, and 12 denotes Mo3d3 / 2. , 13 is M0
(Hexavalent) 3d5 / 2 peak, 14 is Mo (hexavalent) 3d
3/2 peak, 15 is Cr2p3 / 2 peak, 16
Is Cr2p1 / 2 peak, 17 is Cr (trivalent) 2p3
A / 2 peak and 18 represent a peak of Cr (trivalent) 2p1 / 2.

The oxidation state of the oxide film OX formed on the surface of the gate line GL having such a configuration was examined using a so-called scanning Auger electron spectrometer.

FIGS. 17A and 17B are graphs showing the results, and the analysis conditions and the like are shown in FIG. 17C.

FIG. 17A shows a change in the composition with respect to the ion milling time when the surface of the gate line GL is subjected to the oxidation treatment, and FIG.
Shows the change of the composition with respect to the ion milling time when the surface of the gate line GL is not oxidized.

In FIGS. 17A and 17B, reference numeral 7 denotes Cr, 8 denotes Mo, 9 denotes O, and 10 denotes C.

An extension is formed on the gate line GL so as to extend to the formation region of the thin film transistor TFT, and this extension constitutes a gate electrode of the thin film transistor TFT.

The gate line GL (including the gate electrode) is not shown in FIGS.
The side wall surface along the longitudinal direction is tapered so as to expand toward the TFT substrate TFTSUB side. The reason for this is that the data line DL described later is connected to the gate line GL.
This is for preventing the occurrence of disconnection due to the film stress in a portion that goes over the gate line GL in the case where the gate line GL is formed using the same material as that described above. That is, since the gate line GL is formed with the above-described taper, even if the film stress of the data line DL is in the range of 500 to 100 MPa, the gate line GL can be formed without occurrence of disconnection in the above-described portion.

<< Thin Film Transistor TFT >> As shown in FIG. 3, a gate line GL made of a conductive film g1 is formed on a transparent glass substrate SUB1, and an insulating film, a semiconductor layer and the like described later are formed above the gate line GL. T
An FT is configured. When a bias voltage is applied to the gate line GL, the channel resistance between the source and the drain (data line DL) of the thin film transistor decreases,
When the bias voltage is set to zero, the channel resistance operates so as to increase. A gate insulating film GI made of silicon nitride is provided on a gate electrode which is a part of the gate line GL, and an i-type semiconductor layer AS made of amorphous silicon to which impurities are not intentionally added and impurities are added thereon An N-type semiconductor layer d0 made of amorphous silicon is formed.
This i-type semiconductor layer AS forms an active layer of the thin film transistor. Further, a source electrode SD1 and a drain electrode (a part of the data line DL constitutes a drain electrode in the embodiment. The drain electrode is hereinafter referred to as a data line DL unless otherwise specified), and a thin film transistor and a thin film transistor are formed thereon. I do.

As the gate insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected.
It is formed to a thickness of 0 to 500 nm (about 350 nm in this embodiment).

The i-type semiconductor layer AS is formed with a thickness of 50 to 250 nm (about 200 nm in this embodiment).
The N-type semiconductor layer d0 is thinly formed with a thickness of 50 nm or less, is provided for forming an ohmic contact with the i-type semiconductor layer AS, and is formed of an amorphous silicon semiconductor doped with phosphorus (P).

The names of the source electrode and the drain electrode are originally determined by the polarity of the bias between them. In the liquid crystal display device of the present invention, the source electrode and the drain electrode are exchanged because their polarities are inverted during the operation. However, in the following description, one is fixedly called a source electrode and the other is called a drain electrode for convenience.

<< Data Line >> As shown in FIGS. 2 and 3, the data line DL is formed by a gate insulating film GI on a transparent glass substrate SUB1 and an i-type semiconductor layer A on the gate insulating film GI.
The N-type semiconductor layer d0 and the first conductive film d1 are formed on the S and N-type semiconductor layers d0, and have a laminated structure having substantially the same plane pattern in the cross-sectional structure. The substantially same plane pattern is a feature for processing the N-type semiconductor layer d0 in this portion using the first conductive film d1 of the data line DL as a mask, as will be described in a later manufacturing method. Among these layers or films, the first conductive film d1 mainly contributes to electric conduction and transmits a signal.

Further, in this embodiment, as shown in FIGS. 2 and 9, the i-type semiconductor layer AS is also subjected to pattern processing in the third photolithography step, so that the line width is slightly below the data line DL and along the data line DL. Are formed thicker.

The semiconductor layers (N-type semiconductor layer d0 and i-type semiconductor layer AS) formed below and along the data line DL serve as buffer layers and have the effect of relaxing the film stress of the data line DL. .

For this reason, even if the above-mentioned taper is not formed in the gate line GL, the gate line GL can be formed without a disconnection at a portion over the gate line DL.

In this embodiment, the first conductive film d1 in the data line DL is an alloy of Cr and Mo, and is formed of a conductor layer having a Mo content of 20 to 55 wt% with respect to Cr. Like the gate line GL, the data line DL is formed of an alloy layer of Mo and Cr, and has an oxide film OX (Cr ₂ O ₃ , CrO ₂ , M
oO ₂ , MoO ₃ , CrMoO _4, etc.).

The oxide film OX formed on the surface
Contains 40 atomic% or more of oxygen.

The data line DL is formed through the same steps as those for forming the gate line GL.

Therefore, the same effect as that described in the description of gate line GL can be obtained in data line DL.

Then, as in the case of the gate line GL, when the state of oxygen in the oxide film is examined using an X-ray photoelectron spectrometer and a scanning Auger electron spectrometer, FIG. 16 and FIG. The result similar to the result shown in was obtained.

An extension is formed on the data line DL so as to extend to the region where the thin film transistor TFT is formed, and this extension constitutes a drain electrode of the thin film transistor TFT. In addition, the source electrode SD1 is formed so as to be separated from the drain electrode simultaneously with the formation of the data line DL.

The source electrode SD1 is formed so as to extend to the formation region of the pixel electrode ITO1, which will be described in detail later.
The extended portion is configured to be able to make contact with a pixel electrode ITO1 described later in detail. Such a conductor layer is selectively etched in a pattern thereof (ceric ammonium nitrate (15 wt%) as an etchant).
And a mixed solution of hydrogen peroxide aqueous solution (5 wt%).
The etching rate at the time of performing the etching is within the range shown in FIG. 13, so that the etching process can be facilitated. Further, the specific resistance of the conductor layer is within the range shown in FIG. 12 and the over-ride resistance ratio is within the range shown in FIG. 14, so that the resistance can be reduced.

<< Source Electrode >> As shown in FIG. 3, the source electrode SD1 is formed on the N-type semiconductor layer d0 and is constituted by the first conductive film d1. The first conductive film d1 has a thickness of 6
It is formed of a metal film of 0 to 300 nm (about 200 nm in this embodiment).

As shown in FIGS. 1 and 3, the source electrode SD1 is formed on the i-type semiconductor layer AS formed inside one pixel region.
And at the end of the source electrode SD1 at least at the end of the i-type semiconductor layer AS.
Are processed wider than the source electrode SD1. Also,
The transparent conductive layer ITO1 composed of the second conductive film d2 on the upper side has an opening C formed in the protective insulating film PSV1.
N (hereinafter referred to as a contact hole) through the source electrode S
D1 and is formed on the protective insulating film PSV1. Since the protective insulating film PSV1 is interposed in such a structure, the second conductive film d2 does not break at the step of the first conductive film d1, which is the lower source electrode SD1, without disconnection.
The step can be successfully overcome. This will be described in more detail in a later manufacturing method. In particular, such an effect becomes remarkable when ITO is used as the second conductive film d2 as in the present embodiment. In the case of ITO which is polycrystalline, the etching rate of the crystal grain is different from that of the crystal grain boundary, and the grain boundary is fast. Therefore, when the cross section of the lower part of the second conductive film d2 is not processed into a good shape, a grain boundary where the etching proceeds more easily on this lower step is likely to occur, and the disconnection is easily caused from that part in the etching step.

In Japanese Patent Application Laid-Open No. 61-161764, when a semiconductor is etched on a semiconductor film using a metal film as a mask, the etching speed of the semiconductor film is higher than that of the metal film. It is formed in the shape of an eave, and the transparent conductive film is easily broken at this portion. On the other hand, in the present embodiment, the disconnection of the ITO at the step portion is very unlikely to occur as described above.

<< Pixel Electrode >> The pixel electrode is formed of a transparent conductive film ITO1 such as indium tin oxide which is the second conductive film d2. This is connected to the source electrode SD1 of the thin film transistor. The transparent conductive film ITO1 is formed by a sputtering film of ITO and has a thickness of 30 to
It is 300 nm (140 nm in this embodiment).

In the pixel region on the upper surface of the protective film PSV1, a pixel electrode made of, for example, an ITO film is formed.
This pixel electrode can be electrically connected to the source electrode SD1 through the contact hole CN.

In this case, the source electrode SD1 formed at the same time as the data line DL has an oxide film OX formed on its surface, but this oxide film OX is a low-resistance conductive oxide film. Therefore, the contact with the pixel electrode can be achieved without removing the oxide film. Therefore, there is an effect that the number of manufacturing steps is not increased.

The contact resistance in this case is shown in FIG. 19, and it is clear that the contact resistance with the pixel electrode 6 is 3 to 5 × 10 ⁵ Ωcm ² even in the presence of the oxide film OX, and there is no adverse effect.

<< Protective Film >> As shown in FIGS. 1 and 3, TF
The surface of the T substrate TFTSUB on the side where the thin film transistor TFT is formed has a contact hole CN connecting the source electrode SD1 and the pixel electrode, and a gate terminal portion and a drain terminal portion provided on the periphery of the TFT substrate as described later. Except for being covered with the protective film PSV1.

<< Storage Capacitor Cadd, Parasitic Capacitance Cgs >> The storage capacitor Cadd is a gate line GL on which a TFT is formed.
The gate line GL and the gate insulating film GI in the previous stage
And a transparent conductive film I sandwiching a laminated film of the protective insulating film PSV1
It consists of the capacity of the intersection area with TO1. This storage capacitor Cadd has a function of preventing the capacitance of the liquid crystal layer LC from attenuating and a voltage drop when the TFT is off.

The parasitic capacitance Cgs is a capacitance in an intersecting region between the gate line GL at the next stage, which is the gate line GL on which the TFT is formed, and the transparent conductive film ITO1 across the stacked body of the gate insulating film GI and the protective insulating film PSV1. Be composed. Further, as shown in FIG. 2, the Cadd and Cgs are set such that the second conductive film d2 has a predetermined interval on the gate line GL.

As described above, by providing the parasitic capacitance Cgs, the gate line GL and the transparent conductive film IT can be compared with a structure in which the next-stage gate line GL and the second conductive film d2 are not overlapped.
It is not necessary to cover the gap of O1 with the black matrix BM formed on the opposing substrate OPSUB, and the aperture ratio is improved.

<< Light-shielding electrode SKD and square-shaped storage capacitor TCa
dd >> As shown in FIGS. 1 and 2, the light shielding electrode SKD is a TFT
The conductive film g1 forming the gate line GL is formed on the transparent glass substrate SUB1 of the substrate TFTSUB.

The light-shielding electrode SKD has a planar structure and is formed of a transparent conductive film ITO along the data line DL as shown in FIG.
1 and is formed so as to cover the lower part of the data line DL. On the other hand, as shown in FIG. 2, the light-shielding electrode SKD has a data line DL in cross section.
And the gate insulating film GI, the i-type semiconductor layer AS, and the N-type semiconductor layer d0. Therefore, the possibility that the light-shielding electrode SKD and the data line DL are short-circuited is small. Further, the transparent conductive film ITO1 and the light shielding electrode SKD are insulated and separated by the gate insulating film GI and the protective insulating film PSV1.

Like the parasitic capacitance Cgs, the light-shielding electrode SKD has a function of improving the area of the transmitting portion of the pixel electrode with respect to the area of one pixel, that is, the aperture ratio, and improving the brightness of the display panel. In the display panel shown in FIG.
The backlight is set on one of the TFT SUBs having the TFT substrate SUB1. In the following, for convenience, the backlight is T
A case where the light is emitted from the FT substrate SUB1 and observed from the opposing substrate OPSUB side is shown. The irradiation light passes through the glass substrate SUB1 of the opposite substrate, and enters the liquid crystal layer LC from a portion where the wiring line formed by sputtering on one surface of the glass substrate SSUB1 is not formed. This light is controlled by a voltage applied between the transparent common electrode ITO2 formed on the opposite substrate and the transparent conductive film ITO1 formed on the TFT substrate.

When the display panel is in the normally white mode, the light shielding electrode SKD and the parasitic capacitance Cgs are used as in this embodiment.
Is not formed, the opposing substrate OPSUB requires a wide black matrix BM.
Light leakage not controlled by voltage passes through the gap between the data line DL or the gate line GL and the transparent conductive film ITO1, and the contrast of display is reduced. In addition, the upper substrate and the lower substrate, that is, the opposing substrate OPSUB and the TFT substrate TFTSUB are bonded together with a liquid crystal interposed therebetween, and a large alignment margin is required. Become smaller.

Further, the light-shielding electrode SKD and the gate line GL have a function of temporarily reflecting the backlight, returning the light to the light guide plate below the backlight, and reflecting and transmitting the light again to the opening. In the structure of this embodiment, the screen becomes brighter than the aperture ratio. In particular, data line DL
In the structure in which the i-type semiconductor layer AS and the N-type semiconductor layer d0 are formed below the semiconductor layer, since the semiconductor layer has a function of a light absorption layer,
If the light-shielding electrode SKD is not formed further below the lower semiconductor layer of the data line DL, the reflectance decreases and the screen becomes darker.

In the present embodiment, since the semiconductor below the data line DL is processed using the data line DL as a mask, the first conductive film d1 of the data line does not cross the step of the semiconductor layer, and the disconnection failure is prevented. It has the effect of reducing. Therefore, the combination of the light-shielding electrode SKD and the data line DL in the present embodiment is an effect newly obtained in obtaining an effect of brightening the screen.

<< Gate Terminal GTM >> FIG. 4 is a plan view of a portion from the vicinity of the end of the gate line GL on the TFT substrate to the gate terminal GTM which is a connection portion with the drive circuit, and FIG. It is sectional drawing in 5 cutting lines.

The gate terminal GTM is made of the second conductive film d2, and the second conductive film d2 is exposed to the outside. The transparent conductive film of the gate terminal GTM is formed simultaneously with the transparent conductive film ITO1 forming the pixel electrode and the data line.
The second conductive film d2 has a larger pattern than the conductive film g1. This is to prevent chemicals, moisture, and the like from entering and corroding the conductive film g1 made of Cr. In this structure, only the transparent conductive film ITO1 is exposed to the outside except for the protective film PSV1.
ITO, as its name implies, is an oxide and is remarkably resistant to oxidizing reactions that cause corrosion, and thus this structure is yield and reliable.

As can be seen from FIG. 5, the laminated film of the gate insulating film GI and the protective film PSV1 has a gate terminal GT.
Etching is performed collectively at the boundary with the M portion and at the contact hole CN portion. That is, in this portion, the gate insulating film GI and the protective film PSV1 are etched into the same plane shape. This is because the gate insulating film GI and the protective film PSV1 are patterned using the same photomask. However, as can be seen from FIG. 3, the contact hole CN in the display section is different in that the contact hole CN is a single layer of the protective film PSV1. Therefore, as described above, the source electrode SD1
Must be resistant to etching of the protective film.

Further, the ITO is connected to the gate terminal GT without disconnection.
In order to form M, the lower step protective film PSV1 and the gate insulating film GI must be formed into a good tapered shape with a step shape. The manufacturing method described in JP-A-61-161764 and the apparatus described in JP-A-2-157727 do not consider the above points.

<< Drain Terminal GTM >> FIG. 6 is a plan view of a portion from the vicinity of the end of the data line D1 on the TFT substrate to the drain terminal DTM which is a connection portion with an external drive circuit, and FIG. FIG. 7 is a sectional view taken along section line 7-7 of FIG.

The drain terminal DTM is the same as the gate terminal G described above.
It is formed of the transparent electrode d2 for the same reason as in the case of TM. Since the drain terminal portion is connected to an external circuit, the protective film PSV1 is removed together with the gate insulating film GI into the same planar shape. The second conductive film d2 is formed in a pattern wider than the first conductive film d1.

In FIG. 7, which is a cross-sectional structure, the i-type semiconductor layer AS is formed wider at the end of the data line DL than at the data line D1, similarly to the above-mentioned source electrode SD1. Thus, the structure is such that disconnection of the transparent conductive film ITO1 at the step of the data line DL is reduced. Further, the contact hole CN portion is the same as the contact hole CN in the display unit of FIG.
It must be a single layer, and the data line DL thereunder must be resistant to etching of the protective film.

FIG. 8 is a plan view showing a schematic structure around the display panel. In the peripheral portion of the TFT substrate TFTSUB (SUB1), a plurality of gate terminals GTM are arranged side by side corresponding to each gate line to form a gate terminal group Tg. Similarly, a plurality of drain terminals DT correspond to each data line.
M are arranged side by side to form a drain terminal group Td.
In addition, INJ in FIG. 8 is a portion where the sealing pattern Sl for bonding the opposing substrate SUB2 is not provided, and after the two substrates are bonded, the liquid crystal is sealed therein.

<< Optical Substrate OPSUB >> As shown in FIG. 2, one surface of the transparent glass substrate SUS22 has red, green,
A blue color filter FIL, a protective film PSV2, a common transparent pixel electrode ITO2, and an alignment film OPRI1 are sequentially laminated. A polarizing plate POL2 is attached on the other surface of the transparent glass substrate SUB2, and the transmitted light is polarized by the polarizing plate POL1 on the other surface of the TFT substrate TFTSUB on which the TFT is not formed.

Although the black matrix light-shielding film BM is not formed on the glass substrate SUB2 in the same figure, in practice, the TFT portion shown in FIG. It is formed of a Cr sputtering film or a laminate of Cr oxide and Cr, or a resin material.

<< Method of Manufacturing TFT Substrate TFTSUB >> Next, a method of manufacturing the above-described TFT substrate TFTSUB of the liquid crystal display device will be described with reference to FIGS.

FIG. 9 is a flowchart summarizing the flow of the manufacturing process using the names of the respective processes. Each process is summarized in a certain sub unit, and (A), (B),
(C) and so on. From (A) to (F)
The sectional structure in each of the sub-steps up to FIG. 10 corresponds to FIG. Here, the cross-sectional structure excluding the step (B) is a cross-sectional structure immediately after the thin film is etched in each step. For the sake of explanation, the photoresist used as a mask is left on each cross section without being peeled off on the thin film. is there. These figures are cross-sectional views of the vicinity of the thin film transistor-pixel electrode connection portion of the TFT substrate (corresponding to the cross-sectional view of FIG. 3). FIG. 3 shows a cross-sectional structure corresponding to the final step in FIG. Steps (A), (B),
Each of the sub-steps (C), (D), (E), and (F) includes a photoprocessing step. Here, in the present invention, the photoprocessing step refers to a series of operations from application of a photoresist, through selective exposure using a mask to development thereof. As is apparent from FIG. 9, in the present invention, T
The FT substrate is manufactured through five photoprocessing steps.

The steps will be described below in order.

A transparent glass substrate SUS1 is prepared, and an alloy film of Cr and Mo is formed on the entire surface of one surface thereof by sputtering, the alloy film containing 20 to 55% by weight of Mo with respect to Cr. Thereafter, a surface oxidation treatment is performed. Next, after a mask having a predetermined pattern is formed by a photoresist PRES by a photoprocessing (first photo), the alloy film and the oxide film OX are selectively etched (as an etching solution, ceric ammonium nitrate (15 wt.
%) And a mixed solution with an aqueous hydrogen peroxide solution (5%)),
A conductive film g1 having a predetermined pattern is formed (step (A), FIG. 10). At this time, this constitutes the gate line GL and the light-shielding electrode SKD.

In this case, the conductive film g1 has a film stress of 5
Despite being in the range of 100 to 100 MPa, it was confirmed that since the film was formed on a flat surface, disconnection or the like due to the film stress was not found at all.

Here, in FIG. 10, the angle of the end face of the gate line GL pattern with respect to the substrate is vertically displayed for simplicity. In this embodiment, however, an appropriate amount of nitric acid is added to a ceric ammonium nitrate aqueous solution as an etching solution. By using the solution, the end face of the pattern was slightly tapered. As a result of the measurement, the taper angle was about 70 degrees.

Next, the conductive film g of the transparent glass substrate SUB1
1 on a silicon nitride film GI, i by a plasma CVD apparatus.
A-type amorphous Si film AS and an N-type semiconductor layer d0 are sequentially formed. Further, Cr and Mo are successively formed by a sputtering method.
This is the first conductive film d1 (step (B), FIG. 11). Further, a surface oxidation treatment is performed. In this embodiment, as the alloy film, like the gate line GL,
A material containing 20 to 55 wt% of Mo with respect to Cr was used. This material has a film stress of 500 to 100.
It was confirmed that it was easy to get over the step portion of the base without disconnection despite being in the range of MPa. For example, a silicon nitride film GI and an i-type amorphous Si film AS are formed on a step formed by the end of the gate line GL (g1) pattern in FIG.
A drain line DL (d1) at a step over a step formed by coating a stacked film of the semiconductor layer and the N-type semiconductor layer d0.
When a pure Cr film is used, the resistance is likely to increase due to disconnection or overcoming failure at that portion. this is,
This was because the stress of the Cr film was high, and the film stress could not be reduced no matter how the sputtering conditions were adjusted. It has been found that such a problem hardly occurs when the above-described alloy film of Cr and Mo is used instead. Further, it has been confirmed that the above-described problem of resistance increase due to disconnection of the drain line or poor crossover can be almost completely prevented by giving a taper to the end of the gate line GL (g1) pattern.

After a mask having a predetermined pattern is formed of a photoresist PRES by a photoprocessing (second photo), an alloy film of Cr and Mo is selectively etched to form a conductive film d1 having a predetermined pattern. Subsequently, the N-type semiconductor layer d0 is dry-etched and removed using the photoresist PRES (step (C)).

At this time, the Cr alloy film is removed by wet etching, and the etched end of the Cr alloy film is usually set back from the end of the photoresist PRES by about 0.1 to 1 μm. Further, the N-type semiconductor layer d0 has a thickness of 5 as described above.
Since the dry etching is very thin (less than 00 °) and the etching is strongly anisotropic, the amount of recession from the edge of the photoresist PRES is as small as about 0.3 μm, the lower portion of the source electrode SD1 is not etched, and Does not.

Next, after a mask having a predetermined pattern is formed with a photoresist PRES by photoprocessing (third photo), the i-type semiconductor layer AS is removed by etching (step (D)). At this time, the i-type semiconductor layer AS is stopped at the surface of the gate insulating film GI by selective etching with the gate insulating film GI.

At this time, the photoresist PRES pattern is wider than the source electrode at the end of the source electrode SD1.
The transparent conductive film formed later is patterned so as not to be disconnected at the end of the source electrode. Conversely, the data line Dl, the gate line GL, and the data line DL shown in FIG. Processing is performed using the conductive layer d1 as a mask. As a result, the i-type semiconductor layer AS does not protrude from the data line near the data line where the photoresist PRES is not formed.
High-accuracy processing can be performed, and there is an effect that the aperture ratio can be improved and the gate capacitance required for reducing the delay time of the gate wiring can be reduced.

In order to confirm the effect of preventing the disconnection of the transparent conductive film by making the photoresist pattern wider than the source electrode at the end of the source electrode, the photoresist PRES pattern of the i-type semiconductor layer AS was not set wider than the source electrode SD1. Etching was performed using the conductive film d1 of the electrode as a mask. In this case, the thickness of the i-type semiconductor layer AS is N
Since it is thicker than the mold semiconductor layer d0, the semiconductor layer below the end of the source electrode SD1 recedes, and this becomes an eave shape.
As a result, the rate of disconnection of the transparent conductive film ITO1 to be formed later at this step became extremely high.

Next, the silicon nitride was deposited by a plasma CVD apparatus.
A protective insulating film PSV1 made of an N film is formed. After a mask of a photoresist PRES is formed by photoprocessing (fourth photo), the protective insulating film PSV1 is etched to remove the contact hole CN and the protective film PSV1 of the wiring terminal portion (step (E)).

Next, a second conductive film d2 made of an ITO film was deposited by a sputtering method. The target is In
A sputtering gas in which 10 wt% of SnO ₂ was added to ₂ O ₃ was used, the pressure was 0.67 Pa, and the film thickness was 140 nm. After forming a mask with a photoresist PRES by photoprocessing (fifth photo), the second conductive film d2 is selectively etched to leave an ITO pattern on the transparent conductive film ITO1 or the like (step (F)).

As described above, according to the conductive layer structure of the present invention, the material of the conductive layer is an alloy of Cr and Mo, and the Mo is contained in an amount of 20 to 55 wt% with respect to Cr, thereby reducing the resistance. In addition, it is possible to remove the adverse effects such as disconnection due to the film stress, while ensuring the ease of formation and etching.

In the above-described embodiment, as a measure to prevent disconnection due to the film stress of the data line DL, the gate line GL is used.
Are provided with a taper, and a semiconductor layer as a buffer layer is formed below the data line DL.

However, the present invention is not limited to such a configuration, and one of measures is to provide either a taper in the gate line GL or a semiconductor layer as a buffer layer below the data line DL. You may do so.
This is because one of the measures is sufficient as a measure against disconnection due to the film stress of the data line DL.

In the first embodiment, the gate line GL and the data line D are made of an alloy of Cr and Mo, and a conductive layer material containing 20 to 55 wt% of Mo with respect to Cr.
L. In this case, since it is not necessary to select different conductor layers for each of the gate line Gl and the data line Dl, the manufacturing can be simplified. However, it goes without saying that only one of the gate line GL and the data line DL may be used.

In the first embodiment, the oxide film OX on the surface of the alloy of Cr and Mo is formed on the gate line GL and the data line DL. However, it goes without saying that only one of the gate line GL and the data line DL may be used.

In the first embodiment, the data line DL is formed of an alloy layer of Cr and Mo as in the case of the gate line GL. However, the present invention is not limited to this.
Needless to say, it may be constituted by a sequentially laminated body of r and Mo.

FIG. 11 is a diagram showing such a configuration, and corresponds to FIG.

In the case of the second embodiment, since the data line DL must be formed over the step formed by the gate line GL, even if the first Cr layer is cut off, the data line DL is formed in two layers. Mo to form as eyes
The disconnection can be automatically repaired by the layer, and the probability of disconnection of the video signal line can be greatly reduced.

Also in this case, the Mo layer d1 formed on the uppermost layer of the data line DL (the Cr layer d1
By forming the oxide film OX on the surface (where a is formed), the same effect as when an oxide film is formed on the surface of the alloy layer of Cr and Mo can be obtained.

However, even with the Mo layer d1, the adhesion to the photoresist film is not good, and the oxide film OX is formed on the surface thereof.
This is because it has been confirmed that the formation of the compound can significantly improve the adhesion to the photoresist film.

In the embodiments described above, the present invention is applied to the liquid crystal display device, but the present invention is not necessarily limited to only the liquid crystal display device. For example, it goes without saying that the present invention can be applied to a semiconductor device having a wiring layer made of an alloy layer of molybdenum and chromium, or a semiconductor device having a wiring layer made of molybdenum.

In addition, it goes without saying that the present invention can be applied to a case where a Mo layer or a conductor layer made of an alloy layer of Mo and Cr is generally formed by selective etching using a photolithography technique.

[0140]

As is apparent from the above description,
According to the conductor layer structure of the present invention, it is possible to reduce the electric resistance and ensure the ease of the etching process,
Disconnection or the like due to film stress can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan pattern diagram of one pixel of a TFT substrate and a layer around the pixel in a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal display panel of Example 1 to which the present invention is applied (a cross-sectional view taken along line 2-2 in FIG. 1).

FIG. 3 is a cross-sectional view of the vicinity of a thin film transistor and a pixel electrode of the TFT substrate of Example 1 to which the present invention is applied (3 in FIG. 1);
-3 line sectional view).

FIG. 4 is a plan view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL.

FIG. 5 is a sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate line GL.

FIG. 6 is a plan view showing the vicinity of a connection between a drain terminal GTM and a data line GL.

FIG. 7 is a cross-sectional view showing the vicinity of a connection portion between a drain terminal GTM and a data line GL.

FIG. 8 is a plan view for explaining a configuration of a peripheral portion of a matrix of the display panel.

FIG. 9 is a flowchart showing a method for manufacturing a TFTC substrate to which the present invention is applied.

FIG. 10 is a sectional view corresponding to steps A to F in FIG. 9;

11 is a cross-sectional view of the vicinity of a thin film transistor and a pixel electrode of a TFT substrate according to a second embodiment of the present invention (cross-sectional view taken along line 3-3 in FIG. 1).

FIG. 12 is a graph showing specific resistance according to the composition ratio of Mo to Cr.

FIG. 13 is a graph showing an etching rate according to a composition ratio of Mo to Cr.

FIG. 14 is a graph showing a riding resistance ratio according to the composition ratio of Mo to Cr.

FIG. 15 is a graph showing film stress according to the composition ratio of Mo to Cr.

FIG. 16 is a diagram showing a measurement result of a scanning signal line applied as one embodiment of the present invention.

FIG. 17 is a diagram showing a measurement result of a scanning signal line applied as one embodiment of the present invention.

FIG. 18 is a graph showing the effect of the present invention.

FIG. 19 is a diagram showing the effect of the present invention.

[Explanation of symbols]

SUB1, SUB2: transparent glass substrate, GL: gate line (scanning signal line), DL: data line (video signal line), OX: oxide film, GI: gate insulating film, A
S ... i-type semiconductor layer, d0 ... N-type semiconductor layer, SD1 ...
... Source electrode, ITO1 ... Transparent conductive film, g1 ... Conductive film, d1 ... First conductive film, d2 ... Second conductive film, TFT
.... Thin film transistors.

Claims (14)

[Claims] 1. A pair of transparent substrates, at least one of which is disposed to face each other with a liquid crystal interposed therebetween, extends on the liquid crystal side surface of one of the substrates and extends in the x direction and is juxtaposed in the y direction. A gate line and a data line extending in the y direction and juxtaposed in the x direction via the gate line and the insulating film are formed, and a gate is provided in each of the pixel regions surrounded by the gate line and the data line. A liquid crystal display device comprising: a thin film transistor that is turned on by a scanning signal supplied via a line; and a pixel electrode to which a video signal supplied from a data line is applied via the turned on thin film transistor. The lines are Cr and Mo
And a conductor layer, an oxide film is formed on the surface of the conductor layer, and Mo is 20 to 20% of Cr.
A liquid crystal display device characterized by containing 55 wt%. 2. A pair of transparent substrates, at least one of which is disposed opposite to each other with a liquid crystal interposed therebetween, extends on the liquid crystal side surface of one of the substrates and extends in the x direction and is juxtaposed in the y direction. A gate line and a data line extending in the y direction and juxtaposed in the x direction via the gate line and the insulating film are formed, and a gate is provided in each of the pixel regions surrounded by the gate line and the data line. A liquid crystal display device comprising: a thin film transistor that is turned on by a scanning signal supplied via a line; and a pixel electrode to which a video signal supplied from a data line is applied via the turned on thin film transistor. The line has a conductor layer made of an alloy layer of Cr and Mo. The conductor layer has an oxide film formed on its surface, and Mo has a content of 20 to 5w
A liquid crystal display device characterized by containing t%. 3. A pair of transparent substrates, at least one of which is disposed opposite to each other with a liquid crystal interposed therebetween, extends on the liquid crystal side surface of one of the substrates and is arranged in the x direction and juxtaposed in the y direction. A gate line and a data line extending in the y direction and juxtaposed in the x direction via the gate line and the insulating film are formed, and a gate is provided in each of the pixel regions surrounded by the gate line and the data line. A liquid crystal display device comprising: a thin film transistor that is turned on by a scanning signal supplied via a line; and a pixel electrode to which a video signal supplied from a data line is applied via the turned on thin film transistor. The line is composed of a laminated body with another metal layer having the conductor layer of Mo or its alloy as the uppermost layer, and the conductor of Mo or its alloy is The liquid crystal display device characterized by the surface of the oxide film is formed. 4. An oxide film on the surface has a concentration of 40 atomic%.
4. The liquid crystal display device according to claim 1, wherein the oxygen atom is contained. 5. The thin film transistor according to claim 1, wherein a conductive layer of a source electrode and a drain electrode of the thin film transistor is formed of the same material as the data line, and an oxide film is formed on a surface thereof. The liquid crystal display device according to the above. 6. The liquid crystal display device according to claim 1, wherein the conductive layer is electrically connected to another conductive layer via the oxide film on the surface. 7. The liquid crystal display device according to claim 6, wherein the other conductive layer is a transparent conductive film formed on a protective film. 8. The conductive layer of a source electrode of the thin film transistor is formed of the same material as the data line, has an oxide film formed on a surface thereof, and is formed on the protective film via the surface oxide film and a through hole. 4. An electrical connection with the formed transparent conductive film.
The liquid crystal display device according to any one of the above. 9. The liquid crystal display device according to claim 3, wherein the other metal is Cr. 10. The liquid crystal display device according to claim 1, wherein the gate line is tapered so that a side wall surface along a longitudinal direction of the gate line widens toward the substrate side. . 11. The liquid crystal display device according to claim 1, wherein the alloy layer of Cr and Mo contains 30 to 55 wt% of Mo with respect to Cr. 12. The data line according to claim 1, wherein a semiconductor layer formed simultaneously with a semiconductor constituting the thin film transistor is formed along a longitudinal direction thereof as a base layer. The liquid crystal display device according to the above. 13. A liquid crystal display device comprising: a liquid crystal;
A gate line extending in the x direction and juxtaposed in the y direction on a liquid crystal side surface of one of the pair of transparent substrates, at least one of which is disposed in the y direction via the gate line and the insulating film; And a data line extending in the x direction is formed, and a thin film transistor turned on by a scanning signal supplied through the gate line in each of the pixel regions surrounded by each gate line and the data line And a method of manufacturing a liquid crystal display device having a pixel electrode to which a video signal supplied from a data line is applied via the turned-on thin film transistor, wherein the gate line or the data line is formed by conducting an alloy layer of Cr and Mo An oxide film is formed on the surface of the conductor layer, and Mo is 20 to 55% of Cr.
(1) A liquid crystal display device comprising: a liquid containing ceric ammonium nitrate as a main component as an etchant for collectively etching an alloy layer of Cr and Mo and an oxide film on the surface thereof. Method. 14. A liquid crystal display device comprising:
A gate line extending in the x direction and juxtaposed in the y direction on a liquid crystal side surface of one of the pair of transparent substrates, at least one of which is disposed in the y direction via the gate line and the insulating film; And a data line extending in the x direction is formed, and a thin film transistor turned on by a scanning signal supplied through the gate line in each of the pixel regions surrounded by each gate line and the data line And a method of manufacturing a liquid crystal display device having a pixel electrode to which a video signal supplied from a data line is applied via the turned-on thin film transistor, wherein the gate line or the data line is formed by conducting an alloy layer of Cr and Mo And Mo is 20 to 5 with respect to Cr.
The conductor layer has an oxide film formed on the surface thereof by any one of an oxygen plasma method, a surface radiation heating method, a substrate heating method, an ultraviolet irradiation method, and an ozone UV treatment method. A method for manufacturing a liquid crystal display device, comprising: