JPH10223518A - Fabrication of device and aligner therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the effect of vernier insertion error among masks in replacing a mask by putting a second mark separately and independently from a mask when a second pattern on the mask is aligned with a first pattern on a substrate and superpose-exposed. SOLUTION: A wafer 3 is mounted on a wafer stage 5 subjected to drive control in XY direction through a laser interferometer 81 and a drive control means 103 while a mask 1 is located at a position conjugate to the wafer 3 optically through a projection optical system 2. A substrate on which a first pattern image and a second mask image are formed is then subjected to exposure of second pattern and mark and the superposition error is detected. Subsequently, the second pattern on the mask is aligned with the first pattern image formed on the substrate and superpose-exposed. The first mask image and the second mark are in specified positional relationship and a first mark, located separately and independently from the mask for forming the first pattern image, is exposed simultaneously with the first pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device manufacturing method for aligning a second pattern on a mask with respect to a first pattern image formed on a substrate and exposing the device in a superposed manner, and an exposure method usable for the device. Related to the device.

[0002]

2. Description of the Related Art Recently, the semiconductor device manufacturing technology has been remarkably advanced, and the fine processing technology has been remarkably developed.
In particular, optical processing technology is mainly the use of a reduction projection exposure apparatus with a submicron resolution and a so-called stepper. To further improve the resolution, the numerical aperture (NA) of the optical system has been increased and the exposure wavelength has been reduced to a single wavelength. ing.

[0003] Further, a conventional one-size scanning type exposure apparatus using a catoptric projection optical system is improved, a refraction element is incorporated in the projection optical system, and a reflection element and a refraction element are combined.
Alternatively, a scanning exposure apparatus that synchronously scans both a mask stage and a stage of a photosensitive substrate (wafer stage) at a speed ratio according to a reduction magnification by using a reduction projection optical system including only a refraction element has been attracting attention. .

An example of this scanning type exposure apparatus will be described with reference to FIG.

In FIG. 1, a mask 1 on which an original image is drawn is supported by a mask stage 4, and a wafer 3 as a photosensitive substrate is supported by a wafer stage 5. The mask 1 and the wafer 3 are placed at optically conjugate positions via the projection exposure system 2, and a slit-like exposure light 6 extending in the Y direction in the drawing from an illumination system (not shown) illuminates the mask 1 and projects it. Exposure system 2
The image is formed on the wafer 3 with a size corresponding to the projection magnification. The scanning exposure scans the mask 1 and the wafer 3 by moving both the mask stage 4 and the wafer stage 5 with respect to the projection optical system 2 in the X direction at a speed ratio corresponding to the optical magnification with respect to the projection optical system 2. Then, the entire surface of the device pattern 21 on the mask 1 is transferred to the transfer region 22 on the wafer 3.

In the semiconductor manufacturing process, particularly, in the exposure process, the etched wafer 3 and the pattern of the mask 1 are aligned using a stepper such as the above-mentioned scanning exposure apparatus, and then are subjected to overlay exposure.

At this time, in order to measure the overlay accuracy and the offset error, a pattern (vernier) for measuring the positional deviation is drawn on the wafer 3 and an inspector visually inspects the vernier using a microscope or the like. Alternatively, a semiconductor manufacturing method for automatically printing and measuring the overlay accuracy of a pattern has also been implemented.

[0008]

In the manufacture of devices that require alignment, when overlay accuracy inspection is required, that is, when the above-described semiconductor manufacturing method or the like is performed using the above scanning exposure apparatus, A printing pattern 41 for measuring the amount of displacement is put on the mask 1 on the wafer. However, when the mark 41 is drawn on the mask 1, a drawing error always occurs for each mask. For example, when the drawing error is reduced to ± 0.05 μm and reduced by ５, the error on the wafer is ± 10 nm. At this time, it is said that the measurement accuracy is required to be 1/10 or less of the alignment accuracy. Now, in an exposure apparatus using a mask having a writing error of 0.35 μm or less, alignment accuracy is 60
nm or less is required. That is, the error on the wafer when the size is reduced by 1/5 is 70 nm or less, which does not satisfy the alignment accuracy. However, the shift amount due to the drawing error has a constant value, that is, an offset. Therefore, when the printing pattern 41 is drawn on the mask 1,
When measuring the overlay accuracy of the printed pattern,
Each time the mask 1 is replaced with another mask, a mask drawing error of the displacement amount inspection mark must be considered.
That is, the drawing error of the mask side shift amount inspection mark depends on each mask, and the drawing error changes each time the mask is changed.

In this case, a mask drawing error of a deviation amount inspection mark existing for each mask is further managed. On the other hand, in semiconductor manufacturing, dozens of reticles are used for one product, and there are many types of products. Therefore, since an extremely large amount of values managed for each mask must be input, a large amount of data management is required, which is disadvantageous in device management.

According to the present invention, by writing a vernier at a position independent of the mask 1 (for example, on the dummy mask 8), a large amount of data management can be performed by eliminating the influence of a vernier drawing error for each mask due to the replacement of the mask 1. The purpose is to reduce.

[0011]

In order to achieve the above object, the present invention provides a method for aligning a second pattern on a mask with a first pattern image formed on a substrate, preferably by scanning exposure. Wherein a first mark image for overlay error detection having a fixed positional relationship with the first pattern image is formed on the substrate. On the mark image, a second mark for overlay error detection having a fixed positional relationship with the second pattern is simultaneously exposed, and the positional relationship between the first mark image and the transferred image of the second mark on the substrate is determined. In the method for detecting an overlay error between the first pattern and the second pattern based on the first mark, a mark provided at a position separated and independent from the mask is used as the second mark.

In this device manufacturing method, the exposure of the second pattern and the second mark is usually performed on the test substrate on which the first pattern image and the first mark image are formed through the same process as the substrate as the product. Is performed to detect the overlay error, and in consideration of the result, the second pattern on the mask is aligned with the first pattern image formed on the substrate to be a product, and the overlay is exposed.

The first mark image exposed on the substrate is usually in a fixed positional relationship with the second mark, and has a first pattern used to form a first pattern image. Is formed by simultaneously exposing a first mark provided at a separate and independent position from the first pattern. Here, the alignment of the second pattern with respect to the first pattern image is performed by separating / separating from any mask.
This is performed using alignment marks which are provided at independent positions and have a fixed positional relationship with the first mark and the second mark.

The formation of the first pattern image and the first mark image and the formation of the second pattern image and the second mark image and the detection of the overlay error are performed for a plurality of shot positions, respectively. On the basis of the overlay error, an offset value in alignment when exposing the second pattern is obtained, and overlay accuracy is determined.

Further, according to the present invention, in an exposure apparatus for exposing a plurality of mask patterns onto a substrate so as to sequentially overlap each other, a pattern of each layer is detected in order to detect an overlay error between adjacent layers on the substrate. Marks for overlay error detection, which are exposed simultaneously during exposure, are not printed on each mask,
This mark is provided on the apparatus, and is characterized in that the mark is commonly used for detecting an overlay error between adjacent layers. This exposure apparatus is usually a step-and-
It is a repeat type exposure apparatus, preferably a scanning type exposure apparatus.

The marks provided in the exposure apparatus preferably include two types of marks in which the positional relationship between the images is detected after exposure in order to detect an overlay error between adjacent layers.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 is an overall configuration diagram showing a device manufacturing apparatus according to one embodiment of the present invention.

In FIG. 1, a mask 1 on which an original image is drawn is placed on a mask stage 4 which is driven and controlled in the X and Y directions by a laser interferometer 80 and a drive control means 103. It is supported by the illustrated apparatus main body. The wafer 3, which is a photosensitive substrate, is mounted on a wafer stage 5 that is driven and controlled in the X and Y directions by a laser interferometer 81 and a drive control unit 103, and the wafer stage 5 is supported by an apparatus main body (not shown). .
The mask 1 and the wafer 3 are placed at optically conjugate positions via the projection optical system 2, and a slit-like exposure light 6 extending in the Y direction in the figure from an illumination system (not shown) illuminates the mask 1. Then, an image is formed on the wafer 3 via the projection exposure system 2 at a size corresponding to the projection magnification. The scanning exposure is performed by scanning both the mask 1 and the wafer 3 by moving both the mask stage 4 and the wafer stage 5 in the X direction with respect to the slit-shaped exposure light 6 at a speed ratio according to the optical magnification. 1 is transferred to a transfer area (pattern area) 22 on the wafer 3. This scanning exposure is performed by using the mask stage 4 with respect to the slit exposure light 6.
The mask 8 and the wafer 3 are also scanned by moving both the wafer stage 5 and the wafer stage 5 in the X direction at a speed ratio corresponding to the optical magnification, and the entire device pattern 23 on the mask 8 is transferred to the transfer area (pattern area) on the wafer 3. ) For example, transfer to 24.

Here, in this embodiment, when the mask 1 is printed on the wafer 3, a reduction of 1/4 to 1/5 is applied.
The mask used in such a case is hereinafter referred to as a reticle.

In this embodiment, a coater CO, a stepper ST and a developer DE are connected in series in order to automate the inspection of the alignment accuracy and the offset error during the exposure of the wafer 3. However, the stepper ST, the coater CO, and the developer DE as shown in FIG.
The wafers may be transferred by robot between them. Coater CO
Has a mechanism for applying a resist to a wafer to be inspected. The stepper ST has a mechanism for exposing the pattern of the reticle RT to the deviation amount measurement mark 24 formed on the inspection wafer and a mechanism for performing measurement. Developer D
E has a mechanism for developing the inspection wafer exposed by the stepper ST.

Inspection of the wafer is performed according to a command from the control device.
The inspection wafer placed at the entrance of the coater CO is automatically moved while moving between the mechanisms. The alignment accuracy and the process offset calculated from the measured shift amount are input to the control unit CU of the stepper ST, and are used as alignment correction values for the product wafer. The inspection wafer is a wafer that has undergone the same process as the product wafer.

Next, a detailed automatic inspection process according to the present embodiment will be described with reference to FIG. 1 while referring to FIG. 2, FIG. 3, FIG. 4, and FIG. However, the following first to fourth steps are controlled by the stepper control unit CU, and each device and the stepper control unit CU are connected to a communication cable.

The first step (S001 to S00) in FIG.
In 3), the wafer to be inspected is placed on the wafer set table WST (S001). The wafer passes through the transfer path 9 and is coated with a resist by a resist coating device (coater) CO (S002), and the transfer path 10 And is placed on the wafer stage 5 by the automatic hand HAS (S003).

The second step (S004-S007)
This is a step of exposing a pattern drawn on the mask 1 to a resist applied on a wafer. The position of the wafer placed on the wafer stage is adjusted by the off-axis optical system OE (S004). Based on the measurement, the alignment of the wafer mark with respect to the reference mark in the off-axis optical system OE is measured for several shots in the wafer,
This measured value is statistically processed to correct the coordinate system of the wafer (S005). Then, the wafer is exposed at the first shot position. When the exposure is completed, the wafer stage is moved to the next exposure position. Stage movement described here,
The repetition of alignment, exposure and stage movement is called step and repeat (S006). A pattern area exposed at one time is called a shot.

The step and repeat (S0
At the time of exposure in step (06), this scanning type exposure apparatus exposes a reticle side displacement amount measurement mark (FIG. 2A) used in a fourth step to be described later on a wafer side mark (FIG. 2 (B)). 5). That is, the reticle stage 4 and the wafer stage 5 are both moved in the X direction at a speed ratio corresponding to the optical magnification with respect to the slit exposure light 6 to scan the reticle 8 and the wafer 3, and the reticle on the reticle 8 is scanned. The side displacement amount measurement mark (FIG. 2A) is transferred to a transfer area (pattern area) 24 on the wafer 3 which does not affect the device creation of the pattern 21. Here, FIG. 5 shows a step structure and a mark image of the reticle measurement mark and the wafer measurement mark. In FIG. 5, the width of the slit 6 is transferred so as to include the reticle measurement mark, but this width does not need to include the reticle measurement mark. Is).

When the step-and-repeat is completed and the exposure of the wafer is completed, the wafer is sent from the wafer chuck to the carry-in passage 11 of the developing device by the recovery hand HAR, and the process proceeds to the third step (S007).

In the third step, the wafer sent to the carry-in passage 11 is sent to the developing machine DE for development (S008). When the development is completed, the wafer is sent to the carry-in passage 13 via the carry-in passage 12, and the process proceeds to a fourth step which is an inspection process.

In the fourth step (S009 to S014), the wafer is sent to the carry-in passage 10 through the carry-in passage 9 used in the first step without applying a resist in the coater CO, and is again supplied by the supply hand HAS. The wafer is placed on the wafer stage (S009), and the position of the wafer is adjusted by the off-axis optical system OE (S010).
Based on this, alignment measurement is performed for several shots in the wafer, the measured values are statistically processed, the coordinate system of the wafer is corrected (S011), and the alignment accuracy is reduced by the amount of displacement on the wafer in the second step. Inspection is performed using the inspection mark (S012).

Inspection of this alignment accuracy (S012)
As shown in FIG. 4, while the second movable stage 5 is step-and-repeat in order from the first shot to the last shot of the wafer (SB001), an image of the displacement amount measurement mark is first captured by the sensor to perform auto-focusing. Then, the distance between the stage and the projection lens is set to an optimum distance (SB002), and then the deviation amount measurement mark is measured by image processing (SB003), and the measured value is stored in the control unit CU.

The wafer whose measurement has been completed is collected by the collection hand HA.
At R, the wafer is sent from the wafer chuck to the carry-in passage 11 of the developing device.
2 and the wafer is taken out from the wafer receiving table WEN (S013).

Next, the stepper control unit CU calculates the triple value 3σ of the variance σ, which is the auto alignment accuracy, and the offset, which is the average value of the deviation measurement values, from the accumulated deviation amount measurement values. Output. Here, when the 3σ value greatly exceeds the allowable range, a warning is output to the operation terminal CS (not shown) to notify the inspection worker. If the 3σ value is within the allowable range, the process offset of the inspected wafer is normally detected. This process offset is automatically set in the stepper control unit CU as a value for driving correction of the reticle stage 4 during alignment (S014). However, although not described here, when a system called an online system for automatically moving the stepper ST, the coater CO, and the developer DE from outside the clean room is used, information such as a process offset is notified to a host computer of the online system. Will be.

Next, the detection of the mark position and the calculation of the shift amount (S012) in the fourth step of the inspection process will be described with reference to FIG.

First, a method for positioning the reticle and the wafer will be described. Assuming that the center of the reticle-side mark in FIG. 5 is R1, R2, the offset of the reticle drawing error is RI, and the center of the reticle mark is RC, the reticle mark center RC is obtained by the following equation (1).

[0034]

(Equation 1) Further, assuming that the shift amount between the center of the reticle mark and the center of the wafer side mark is E and the center of the wafer side mark is WC, the shift amount E is obtained by the following equation (2).

[0035]

(Equation 2)

Next, the above-described method of calculating the process offset and determining the alignment accuracy will be described. If N is the total number of shots, E is the measured deviation, and M is the process offset, the process offset M is

[0037]

(Equation 3) And the variance σ of the alignment accuracy is

[0038]

(Equation 4) Is required. The alignment of the inspected wafer is evaluated by 3σ.

Here, if the measurement mark shown in FIG. 2A is drawn on the reticle 1, the offset RI of the drawing error must be considered each time the reticle 1 is changed. However, according to the present embodiment, the offset RI of the drawing error can be determined by considering only the offset of the drawing error of the reticle 8 in FIG. 1 by using the shift amount inspection mark at a position independent of the reticle 1. is there.

Here, an example of the method of evaluating the alignment has been described, but it is not always necessary to perform the evaluation in the same manner. For example, in the present embodiment, the mask pattern as shown in FIG. 2A is given. However, if the mask pattern is located at a position which is not affected by the drawing error of the device creation mask, as shown in FIG. It may be a simple mask pattern. In this embodiment, the mask pattern is drawn on the mask stage 4 (for example, on the dummy mask 8). However, if the mask pattern is not dependent on the mask 1, the mask pattern is drawn optically via the projection optical system. It is also possible to place a mask pattern on a conjugate illumination system (not shown).

(Embodiment 2) Another embodiment of the present invention in a semiconductor manufacturing line will be described with reference to FIG.
This will be described with reference to the flowchart shown in FIG.

In this embodiment, the device manufacturing apparatus used is the same as that used in the first embodiment.
Is indicated by

In the inspection of the wafer in this embodiment,
Inspection wafers placed at the entrance of the coater CO are automatically moved while moving between the mechanisms according to a command from the control device. The alignment accuracy and the process offset calculated from the measured shift amount are input to the control unit CU of the stepper ST, and the process offset is used as an alignment correction value for the product wafer. The inspection wafer is a wafer that has undergone the same process as the product wafer (similar to the first embodiment).

The first step (S101 to S10) in FIG.
In 3), the wafer to be inspected is placed on the wafer set table WST (S101), and the wafer passes through the transfer path 9 and is coated with a resist by a resist coating device (coater) CO (S102), and the transfer path 10 And is mounted on the wafer stage 5 by the automatic hand HAS (S103).

The second step (S104-S105)
This is a step of exposing a pattern drawn on the mask 1 to a resist applied on a wafer. In the present embodiment, the exposure in this step (S104) is referred to as first exposure.

The operation of the exposure apparatus in the first exposure is the same as that in the second exposure (S006 in FIG. 3) of the first embodiment. However, in the first exposure, the scanning type exposure apparatus performs a sixth step described later. The reticle side displacement amount measurement mark (main scale in FIG. 6: FIG. 6A) to be used is exposed. That is,
The reticle-side deviation amount measurement mark on the reticle 8 (FIG. 6)
(A) is also transferred to a transfer area (pattern area) 24 on the wafer 3 which does not affect the device creation of the pattern 21.

Here, FIG. 8 shows a step structure of the measurement mark,
This image is shown. In FIG. 8, the width of the slit 6 is transferred so as to include the main scale. However, the width of the slit 6 does not need to include the main scale. Is). In FIG. 8, this 1
Although only the main scale is transferred at the time of st exposure, the width of the slit 6 is sufficiently large, and the sub-scale may be transferred at the same time as the main scale is transferred.

In the third step, the wafer sent to the carry-in passage 11 is sent to the developing machine DE for development (S106). When the development is completed, the wafer is sent to the carry-in passage 13 via the carry-in passage 12, and the process proceeds to a fourth step which is an inspection process.

In the fourth step (S107 to S112), the wafer is sent to the carry-in passage 10 without being coated with the resist by the coater CO through the carry-in passage 9 used in the first step, and again supplied by the supply hand HAS. The wafer is placed on the wafer stage (S108), and the position of the wafer is adjusted by the off-axis optical system OE (S109).
Based on this, the above 1s for several shots in the wafer
The alignment is measured using the image of the alignment mark on the wafer simultaneously exposed at the time of t exposure, and the measured value is statistically processed to correct the coordinate system of the wafer (S11).
0). Then, the reticle is shifted by a certain amount with respect to the wafer so that the main scale and the vernier in FIG. 6 overlap at the first shot position, and the sub-meter (FIG. 6A) is overlapped and exposed. When this exposure is completed, the wafer stage is moved to the next exposure position, and step and repeat are performed (S111).
This step-and-repeat exposure in the present embodiment is referred to as 2nd exposure (the vernier scale is transferred by the 2nd exposure).

When the step-and-repeat is completed and the exposure of the wafer is completed, the wafer is sent from the wafer chuck to the carry-in passage 11 of the developing device by the collection hand HAR, and the process proceeds to the fifth step (S112).

In the fifth step, similarly to the third step, the wafer sent to the carry-in path 11 is sent to the developing machine DE for development (S113). When the development is completed, the wafer is sent to the carry-in passage 13 via the carry-in passage 12, and the process proceeds to a sixth step which is an inspection process.

In the sixth step (S114 to S119), the wafer is sent to the carry-in passage 10 through the carry-in passage 9 used in the first and fourth steps without applying a resist in the coater CO, and the supply hand HAS The wafer is again mounted on the wafer chuck (S114), and the position of the wafer is adjusted by the off-axis optical system OE (S115) in the same manner as in the fourth step, and alignment measurement is performed for several shots within the wafer based on the position. The values are statistically processed to correct the coordinate system of the wafer (S116). Then, the alignment accuracy in the fourth step is inspected using the deviation amount inspection mark on the wafer (S117).

That is, as shown in FIG.
While the second movable stage is step-and-repeat in order from the shot to the last shot (SB001), the image of the displacement amount measurement mark is first captured by the sensor, and autofocus is performed, and the distance between the stage and the projection lens is set to the optimum distance. Are set (SB002), and then the deviation amount measurement mark is measured by image processing (SB00).
3), and accumulate the measured values inside the control unit CU.

The wafer whose measurement has been completed is collected by the collection hand HA.
In R, the wafer is sent from the wafer chuck to the carry-in passage 11 of the developing device, and in the developing device DE, the wafer is sent to 12 without performing the developing operation, and the wafer is taken out from the wafer receiving table WEN (S
118).

Next, the stepper control unit CU calculates a triple value 3σ of the variance σ, which is the auto alignment accuracy, and an offset which is an average value of the deviation measurement values, from the accumulated deviation amount measurement values. Output.

Here, if the 3σ value is significantly outside the allowable range, a warning is output to an operation terminal (not shown) to notify the inspection operator. If the 3σ value is within the allowable range, the process offset of the inspected wafer is normally detected. This process offset is
At the time of alignment, a value for drive correction of the reticle stage 4RS is automatically set in the stepper control unit CU (S119).

The detection of the mark position and the calculation of the shift amount are obtained in the same manner as in the first embodiment. Also in the case of the second embodiment, when FIG. 6A is drawn on the reticle 1, every time the reticle 1 is changed, the offset of the drawing error must be considered.

However, if a mark for inspecting the amount of displacement which does not depend on the reticle 1 is used, only the reticle 8 shown in FIG.

(Embodiment 3) In Embodiments 1 and 2, the process of "development" is included in the flowchart (FIG. 3: S00).
8, FIG. 7: S106, S113). However, in the case of a shift amount inspection or the like, a process called a “latent image” for performing the shift amount inspection is performed by measuring a change in the resist due to exposure without performing the developing process. "Latent image"
In this case, the development processing shown in FIGS. 3 and 7 is eliminated.

Although the embodiments of the present invention have been described above, the present invention does not depend on the processing or sequence of these flows. In other words, the present invention provides a method for manufacturing a device that requires alignment, in a case where an overlay accuracy inspection is required, in a position independent of the mask 1 (for example, a dummy The device is manufactured by using the mask side inspection mark drawn on the mask 8).

[0061]

As described above, according to the present invention,
In the manufacture of a device requiring alignment, a mask side inspection mark is drawn on the mask stage 4 (for example, on the dummy mask 8) independent of the mask 1 when calculating an overlay accuracy inspection or calculating a process offset. Accordingly, no matter what mark is used as the deviation amount inspection mark, a large amount of data management can be reduced except for the influence of the inspection mark drawing error for each mask due to the replacement of the mask 1.

[Brief description of the drawings]

FIG. 1 is a schematic view of a main part of an exposure apparatus according to the present invention.

2A is a diagram illustrating a reticle-side displacement amount inspection plate according to the first embodiment, and FIG. 2B is a diagram illustrating a wafer-side displacement amount inspection mark according to the first embodiment.

FIG. 3 is a flowchart illustrating an inspection process of an overlay inspection according to the first embodiment.

FIG. 4 is a flowchart illustrating detection of a mark position and calculation of a shift amount in FIGS.

FIG. 5 is a diagram showing a step structure of a measurement mark of a dummy reticle used in Example 1 and an image of the mark.

FIG. 6A is a diagram illustrating a reticle-side displacement amount inspection plate according to the second embodiment, and FIG. 6B is a diagram illustrating the overprinted wafer-side displacement amount inspection mark according to the second embodiment.

FIG. 7 is a flowchart illustrating an inspection process of an overlay inspection according to the second embodiment.

FIG. 8 shows a step structure of a measurement mark of a dummy reticle used in Example 2 and an image of the mark.

FIG. 9 is an example of a schematic view of a main part of the present invention.

FIG. 10A is an example of marks on a reticle side displacement amount inspection plate other than the first and second embodiments of the present invention;
(B) is an example of a wafer side shift amount inspection mark other than the first and second embodiments of the present invention.

[Explanation of symbols]

1: mask, 2: projection exposure system, 3: wafer, 4: mask stage, 5: wafer stage, 6: slit exposure light, 7, 101: mark detecting means, 8: dummy reticle, 9 to 13: carry-in passage , 21: device pattern on a mask, 22: device pattern on a wafer, 24: pattern transfer area, 41, 42: burn-in pattern for measuring the amount of displacement, 80, 81: laser interferometer, 102: arithmetic processing means, 103: drive Control means, HAR: collection hand, H
AS: Auto hand, CO: Coater, ST: Stepper,
DE: Developer, WEN: Wafer receiving table, W
ST: wafer set table, OE: off-axis optical system, CU: control device.

Claims (11)

[Claims] 1. A device manufacturing method comprising: aligning a second pattern on a mask with a first pattern image formed on a substrate, and exposing the second pattern on the mask, wherein the first pattern image is formed on the substrate. A first mark image for detecting an overlay error having a fixed positional relationship with the pattern image is formed, and upon the exposure, an overlay having a fixed positional relationship with the second pattern is formed on the first mark image. A second mark for alignment error detection is exposed at the same time, and a superposition between the first pattern and the second pattern is performed based on a positional relationship between the transferred image of the first mark and the transferred image of the second mark on the substrate. A device manufacturing method for detecting an error, wherein a mark provided at a position separated and independent from the mask is used as the second mark. 2. A test substrate on which the first pattern image and the first mark image are formed through the same process as that of a substrate to be a product is exposed to the second pattern and the second mark to be overlapped. Detecting an alignment error, taking into account the result, aligning the second pattern on the mask with the first pattern image formed on the substrate to be a product, and exposing the second pattern on the mask. The device manufacturing method according to claim 1. 3. The first mark image has a fixed positional relationship with the second mark, and is separated / independent from a mask having a first pattern used to form the first pattern image. 3. The device manufacturing method according to claim 1, wherein the first mark provided at the set position is formed by exposing the first mark simultaneously with the first pattern. 4. The positioning of the second pattern with respect to the first pattern image is provided at a position separated and independent from any mask, and has a fixed positional relationship with the first mark and the second mark. 4. The method for manufacturing a device according to claim 3, wherein the method is performed using a mark for use. 5. The method according to claim 1, wherein the formation of the first pattern image and the first mark image and the formation of the second pattern image and the second mark image and the detection of the overlay error are performed at a plurality of shot positions, respectively. 5. The device manufacturing method according to 4. 6. The device manufacturing method according to claim 1, wherein said exposure is scanning exposure. 7. The method according to claim 5, further comprising: obtaining an offset value in alignment when exposing the second pattern, and judging overlay accuracy, based on the overlay error for each shot position. Device manufacturing method. 8. An exposure apparatus for exposing a plurality of mask patterns on a substrate so as to sequentially overlap with each other, and simultaneously exposing the patterns of each layer to detect an overlay error between adjacent layers on the substrate. Mark on the device, not on each mask, for overlay error detection
An exposure apparatus characterized in that the mark is commonly used to detect an overlay error between adjacent layers. 9. The mark according to claim 8, wherein the marks include two kinds of marks whose positional relationship between the images is detected after exposure in order to detect an overlay error between adjacent layers. Exposure equipment. 10. The exposure apparatus according to claim 8, wherein the exposure apparatus is of a step-and-repeat type. 11. The exposure apparatus according to claim 8, wherein the exposure apparatus is a scanning type.