JPH10209075A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize low resistance of the source/drain section of a MOS transistor. SOLUTION: A silicon oxide film 103 for element isolation, a gate oxide film 104, a gate electrode 105, a side wall spacer 106 and a source/drain 107 are formed on a silicon substrate 101. Subsequently, a metal film or metal silicide film or stacked film 108 of them are deposited to the entire part. Here, the chemical mechanical polishing is conducted in such a manner that the gate electrode 105 does not disappear and the metal film or metal silicide film or stacked layer film 108 of these are left only on the source/drain 107. More specifically, using the polishing solution where grinding particle of alumina is dispersed in the chemicals which is adjusted to pH 4 or so with an organic acid and a polishing cloth consisting of foamed polyulethane, the wafer is rotated at 50rpm under the condition that the wafer surface is pressurized by about 400 to 500g per unit square cm. As a result, the source/drain is formed in the low resistance condition.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for manufacturing a semiconductor device, and more particularly, to a method for forming a metal film, a metal silicide film, or a laminated film thereof on a source / drain of a MOS transistor by using a chemical mechanical polishing method. The present invention relates to a manufacturing method and an apparatus for realizing low resistance of a source / drain portion by forming the device.

[0002]

2. Description of the Related Art There are two methods for reducing the resistance of a source / drain portion by forming a metal film / metal silicide film or a laminated film thereof on the source / drain of a MOS transistor. Can be

One is, for example, C.I. K. Lau et.
al. IEDM. Tech. Dig. , 1982. p7
This is the so-called salicide method found in 14th grade.

The other is, for example, R. S. Blewer
et. al. Proc. 1st IEEE VLSI
Multilevel Interconnection
onConf. 1984. This is selective growth of a metal film and a metal silicide film on the source / drain, which are observed in p153 and the like.

[0005]

According to the former method (salicide method) described in the former section, the method described in J.I. P. Gambino e
t. al. Abstract of ECS fall
meeting. 1991. As reported in P312, when the line width becomes fine, the problem of the so-called fine line effect occurs, in particular, the sheet resistance of the N-channel increases. In addition, since the method essentially uses the reaction between the silicon substrate and the metal, if the diffusion layer becomes shallower with miniaturization, there is a trade-off relationship between low resistance and junction leakage, and the process margin is reduced. It decreases significantly.

On the other hand, the latter selective growth method has a problem that when there is a particle or the like which serves as a nucleus for crystal growth, so-called selective breaking occurs and the yield is not stable.

[0007]

In order to solve the above problems, in the manufacturing method of the present invention, a metal film, a metal silicide film, or a laminated film thereof is adhered to the entire surface after forming a high concentration diffusion layer. Thereafter, the metal film / metal silicide film other than the high-concentration diffusion layer portion or the laminated film thereof is removed by a chemical mechanical polishing method to form a structure in which the source / drain portions have low resistance.

Further, according to the manufacturing method of the present invention, after removing a metal film / metal silicide film or a laminated film thereof deposited in advance only in a portion where the resistance of the diffusion layer does not need to be lowered by using photolithography, Polishing is performed.

Further, in the manufacturing method of the present invention, when polishing is performed by a chemical mechanical polishing method, after removing a metal film, a metal silicide film or a laminated film of a high step portion in advance using photolithography, the polishing is performed. It is characterized by performing mechanical polishing.

Further, the manufacturing method of the present invention is characterized in that a sidewall spacer is formed so as to leave an insulating film on the gate electrode.

Further, in the manufacturing method of the present invention, polishing is performed so that an insulating film is left on the gate electrode during chemical mechanical polishing and a metal film, a metal silicide film, or a laminated film thereof is left only in a necessary portion. It is characterized by the following.

Further, the manufacturing method of the present invention is characterized in that the metal film
The silicide film or the laminated film thereof is a refractory metal film or a silicide film thereof.

Further, according to the manufacturing method of the present invention, a metal silicide film is formed in a contact portion with a silicon substrate by depositing a metal film and performing a heat treatment, and a stacked film of the metal film and the metal silicide film is formed as a high concentration diffusion layer. It is characterized by being formed above.

Further, in the semiconductor device of the present invention, in a semiconductor device having a MOS transistor as a constituent element, a low concentration diffusion layer is provided below a sidewall spacer, and a metal film / metal silicide film or a laminated film thereof is provided outside the low concentration diffusion layer. And a high-concentration diffusion layer.

Further, the semiconductor device according to the present invention is characterized in that the area of the polished metal film / metal silicide film or the laminated film thereof is larger than the area of the high concentration diffusion layer.

[0016]

Since the present invention uses a structure in which a metal film, a metal silicide film, or a laminated film thereof is stacked on a source / drain, a problem of a fine wire effect and a problem of a junction leak caused by a reaction between a metal and a silicon substrate occur. do not do.

At the same time, the present invention does not use the selective growth method, so that the problem of so-called selective breaking cannot occur.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, an embodiment of a structure of the present invention, in which a metal film, a metal silicide film, or a laminated film thereof is stacked on a source / drain portion of a MOS transistor by a chemical mechanical polishing method. explain.

First, an embodiment of the structure shown in the means 1 and the manufacturing method shown in the means 2 will be described with reference to FIG.
WELL in which impurities are deeply diffused in a silicon substrate 101
102, a silicon oxide film 103 for element isolation is formed. Thereafter, through gate oxidation, film deposition for gate electrode, gate processing, insulating film deposition, anisotropic etching, various ion implantation processes, etc., the gate oxide film 104 and the gate electrode 1
FIG. 1A shows the formation of the sidewall spacers 106 and the source / drain 107. Subsequently, when a metal film, a metal silicide film, or a laminated film 108 thereof is deposited on the entire surface, the result is shown in FIG. The metal film used for this laminated film is preferably titanium (Ti), cobalt (Co), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten ( High melting point metals such as W)
More preferably, titanium (Ti), tungsten (W), molybdenum (Mo), and cobalt (Co) are used. The metal silicide film is preferably a high melting point metal silicide film, more preferably TiSi ₂ , WSi ₂ ,
MoSi ₂ and CoSi ₂ . Although the thickness of the laminated film is not particularly limited, it is 1000 ° to 2500 °, more preferably 1700 ° to 2200 °. It is better to be thicker in consideration of lowering the resistance, but thinner is more desirable in view of miniaturization. In short, this laminated film can sufficiently cope with a temperature of 1000 ° or less as long as a short circuit between the gate and the source / drain can be prevented. Next, in a chemical solution adjusted to around pH 4 with an organic acid or the like, a polishing liquid in which abrasive grains made of, for example, alumina are dispersed, and a polishing cloth made of foamed polyurethane, for example, are used. By rotating the deposited metal film or metal silicide film or their laminated film 108 by rotating the deposited metal film or metal silicide film or their laminated film 108 while the gate electrode 105 is not lost and the deposited metal film or metal silicide film Alternatively, FIG. 1C shows the result of performing the chemical mechanical polishing in such a range that the laminated film 108 remains only on the source / drain 107. As an indication of the end of the chemical mechanical polishing, it is conceivable to analyze the components after the polishing. For example, in the case of a gate electrode formed of polysilicon or the like, if polysilicon can be detected, polishing can be performed without erasing the gate electrode. If SiO ₂ can be detected, polishing can be performed without losing the silicon oxide film. As is clear from FIG. 1C, the silicon oxide film 103 for element isolation, the gate electrode 105, the sidewall spacer 1
06 and the metal film or the metal silicide film or their laminated film 108 have substantially the same height, and have a structure in which the gate electrode 105 and the metal film or the metal silicide film or their laminated film 108 are separated by the sidewall spacer 106. Become. The resistance of the source / drain 107 can be reduced by the metal film, the metal silicide film, or the laminated film 108 thereof. Further, as shown in FIG. 1D, an oxide film, a nitride film, TEOS, BP
An interlayer insulating film 109 of SG, PSG or the like is deposited, and an aluminum wiring 110 is deposited and processed after forming a connection hole. A semiconductor device having a structure in which stacked films are stacked is completed.

Next, a structure represented by the means 4 and an embodiment of a manufacturing method thereof will be described with reference to FIG. WELL 202 in which impurities are deeply diffused in a silicon substrate 201,
A silicon oxide film 203 for element isolation is formed. After that, gate oxidation, film deposition for gate electrode, gate processing,
The gate oxide film 204, the gate electrode 205, the sidewall spacers 206, the source / drain 207 are formed through insulating film deposition, anisotropic etching, various ion implantation processes, and the like.
Is formed in FIG. 2A. Subsequently, a metal film, a metal silicide film, or a stacked film 20 thereof is formed.
When 8 is deposited on the entire surface, the result is shown in FIG. Here, chemical mechanical polishing is performed so that the deposited metal film or metal silicide film or their laminated film 208 remains only on the source / drain 207 without losing the gate electrode 205 located at a high step. FIG. 2C shows that the photoresist 209 is exposed and etched so as to remain only on the metal film or the metal silicide film or the laminated film 208 where the photoresist 209 is to be left. After that, the gate electrode 2 in the high step portion
The resistance of the source / drain 207 is reduced by performing chemical mechanical polishing so that 05 does not disappear and the deposited metal film or metal silicide film or their laminated film 208 remains only on the source / drain 207. FIG. 2 (d) shows the result. Although not shown in the figure, even in this case, as in the embodiment described later, an insulating film is left on the gate electrode, and the gate electrode can be protected even if impurities such as dust adhere. That is, if a nitride film, amorphous silicon, or the like is used for the insulating film on the gate electrode,
By analyzing the above-mentioned polished components that can be distinguished from the silicon oxide film, a structure in which an insulating film is left on the gate electrode can be formed. Further, as shown in FIG.
By depositing an interlayer insulating film 210 and depositing and processing an aluminum wiring 211 after forming a connection hole, a metal film, a metal silicide film, or a laminated film thereof is stacked on a source / drain portion according to an embodiment of the present invention. A semiconductor device having a structure is completed.

Next, a structure represented by the means 5 and an embodiment of a manufacturing method thereof will be described with reference to FIG. WELL 302 in which impurities are deeply diffused in a silicon substrate 301,
A silicon oxide film 303 for element isolation is formed. After that, gate oxidation, film deposition for gate electrode, gate processing,
Through deposition of an insulating film, anisotropic etching, various ion implantation processes, etc., a gate oxide film 304, a gate electrode 305, a sidewall spacer 306 processed so as to leave an insulating film on the gate electrode, and a source / drain 307 are formed. This is shown in FIG. Subsequently, when a metal film, a metal silicide film, or a laminated film 308 thereof is deposited on the entire surface, the structure shown in FIG. 3B is obtained. Here, the gate electrode 3
FIG. 3C shows that chemical mechanical polishing is performed so that the metal film 05 does not disappear and the deposited metal film or metal silicide film or their laminated film 308 remains only on the source / drain 307. Since the sidewall spacer is processed so as to leave the insulating film on the gate electrode, a margin for disappearance of the gate electrode 305 during chemical mechanical polishing is improved. Further, as shown in FIG. 3D, an interlayer insulating film 309 is deposited, and after forming the connection holes, the aluminum wiring 31 is formed.
By depositing and processing 0, a semiconductor device having a structure in which a metal film, a metal silicide film, or a laminated film thereof is stacked on a source / drain portion according to an embodiment of the present invention is completed.

Next, a structure represented by the means 6 and an embodiment of a manufacturing method thereof will be described with reference to FIG. WELL 402 in which impurities are deeply diffused in a silicon substrate 401;
A silicon oxide film 403 for element isolation is formed. After that, gate oxidation, film deposition for gate electrode, gate processing,
Through deposition of an insulating film, anisotropic etching, various ion implantation steps, etc., a gate oxide film 404, a gate electrode 405, a sidewall spacer 406 processed so as to leave an insulating film on the gate electrode, and a source / drain 407 are formed. I do. Subsequently, a metal film, a metal silicide film, or a laminated film 408 thereof is deposited on the entire surface, an insulating film is left on the gate electrode, and the metal film / metal silicide film or the laminated film 408 thereof is left only in necessary portions. FIG. 4A shows the result of chemical mechanical polishing. As an indication of the end of the chemical mechanical polishing, for example, it is conceivable to analyze components after polishing. In this case, in order to easily distinguish the silicon oxide film from the insulating film on the gate electrode, it is preferable to prepare films having different components. For example, when a nitride film, amorphous silicon, or the like is used for an insulating film on a gate electrode, the insulating film can be distinguished from a silicon oxide film. Thereafter, an interlayer insulating film 409 is deposited, and an aluminum wiring 410 is deposited and processed after forming a connection hole, thereby completing a semiconductor device having a structure according to one embodiment of the present invention as shown in FIG. 4B. By leaving the insulating film on the gate electrode, the polished metal film or metal silicide film or their laminated film 408 and the gate electrode 405 are not short-circuited, and the metal film or the polished metal film is smaller than the area of the high concentration diffusion layer.
The area of the metal silicide film or a stacked film thereof can be increased. Therefore, the source / drain 40
7, the allowance for the connection hole of the aluminum wiring 410 to be increased.

Next, a structure represented by the means 8 and an embodiment of a manufacturing method thereof will be described with reference to FIG. WELL 502 in which impurities are diffused deeply in a silicon substrate 501;
A silicon oxide film 503 for element isolation is formed. After that, gate oxidation, film deposition for gate electrode, gate processing,
The gate oxide film 504, the gate electrode 505, the sidewall spacer 506, the source / drain 507 are formed through insulating film deposition, anisotropic etching, various ion implantation processes, and the like.
Is formed in FIG. 5A. Subsequently, when a metal film 508 is deposited on the entire surface, the result is as shown in FIG. Here, chemical mechanical polishing is performed so that the gate electrode 505 does not disappear and the deposited metal film 508 remains only on the source / drain 507. After that, heat treatment is performed to form the metal film 50.
8 react with the silicon substrate to form a metal silicide film 509.
To form At this time, FIG. 1C shows that a stacked film of the metal film 508 and the metal silicide film 509 was formed without reacting all the metal films remaining after the polishing. By forming the metal silicide film 509, the contact resistance with the high concentration diffusion layer is reduced. On the other hand, depending on the size of the diffusion layer, the sheet resistance of the metal silicide film 509 may increase due to the thin line effect described above. However, since it has a laminated structure with the metal film 508, the overall sheet resistance can be kept low. Therefore, unlike the salicide described above, it is not necessary to form the metal silicide film thickly to lower the resistance. Therefore, there is a sufficient margin for junction leakage caused by disappearance of the high concentration diffusion layer due to silicidation as compared with salicide. Further, as shown in FIG. 5D, a semiconductor device having a structure according to an embodiment of the present invention is completed by depositing an interlayer insulating film 510 and then depositing and processing an aluminum wiring 511 after forming a connection hole. .

The embodiments of the semiconductor device of the present invention and the method of manufacturing the same have been specifically described above with reference to FIGS. 1, 2, and 3. Needless to say, the present invention is not limited to the above-described embodiment, and it is needless to say that various changes can be made without departing from the gist thereof, for example, when the transistor structure is more complicated in the method of manufacturing a semiconductor device. is there.

[0025]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

1. By removing the metal film, metal silicide film or their lamination film deposited on the entire surface of the wafer from parts other than the high concentration diffusion layer by chemical mechanical polishing, the resistance rise in a remarkable fine pattern in the so-called salicide structure The resistance of the source / drain can be reduced without causing the problem of the junction and the problem of the junction leak and without causing the problem of the selection breaking in the selective growth.

2. The metal film, metal silicide film, or their laminated film attached to the entire surface of the wafer is scraped off from parts other than the high concentration diffusion layer by chemical mechanical polishing.
In addition, by making the area of the polished metal film, metal silicide film, or their laminated film larger than the area of the high concentration diffusion layer, it is possible to reduce the margin for aligning the aluminum wiring connection hole with the source / drain. Become.

3. The metal film attached to the entire surface of the wafer
The so-called salicide structure is formed by shaving off parts other than on the high concentration diffusion layer by chemical mechanical polishing and converting a part of the remaining metal film into a very small amount of silicide by heat treatment to form a laminated film of metal film and metal silicide film. In this case, the resistance of the source / drain can be reduced without causing the problem of remarkable increase in resistance in a fine pattern or the problem of junction leakage, and without causing the problem of selection breakage in selective growth.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a structural example and a manufacturing flow of a semiconductor device represented by means 1 and means 2 in an embodiment of the present invention.

FIG. 2 is a diagram illustrating a structural example and a manufacturing flow of a semiconductor device represented by a means 4 according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating a structural example and a manufacturing flow of a semiconductor device represented by a means 5 according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating a structural example and a manufacturing flow of a semiconductor device represented by a means 6 according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating a structural example and a manufacturing flow of a semiconductor device represented by a means 8 in the embodiment of the present invention.

[Explanation of symbols]

101, 201, 301, 401, 501 ... silicon substrate 102, 202, 302, 402, 502 ... WEL
L 103, 203, 303, 403, 503: Silicon oxide film for element isolation 104, 204, 304, 404, 504: Gate oxide film 105, 205, 305, 405, 505: Gate electrode 106, 206, 506... Sidewall spacers 306, 406... Sidewall spacers 107, 207, 307, 407, 507... Source / drain 108, 208, 308, 408. ..Metal films, metal silicide films or their laminated films 109, 210, 309, 409, 510: interlayer insulating films 110, 211, 310, 410, 511: aluminum wiring 209: photoresist 508 ..Metal film 509 ... Metal silicide film

Claims (10)

[Claims] In a method of manufacturing a semiconductor device including a MOS transistor as a constituent element, a low concentration diffusion layer is formed below a sidewall spacer and a high concentration diffusion layer is formed outside the low concentration diffusion layer. A method for manufacturing a semiconductor device, comprising: attaching a stacked film to the entire surface; and removing a metal film, a metal silicide film, or a stacked film thereof other than the high-concentration diffusion layer portion by a chemical mechanical polishing method. 2. A method for manufacturing a semiconductor device according to claim 1, wherein only a portion of the diffusion layer which does not need to have a reduced resistance is removed by a photolithography method. A method for manufacturing a semiconductor device, comprising: performing chemical mechanical polishing after the etching. 3. The method of manufacturing a semiconductor device according to claim 1, wherein when polishing is performed by a chemical mechanical polishing method, a metal film, a metal silicide film, or a laminated film of a high step portion is previously formed. A method for manufacturing a semiconductor device, comprising performing chemical mechanical polishing after removing using photolithography. 4. The method for manufacturing a semiconductor device according to claim 1, wherein a sidewall spacer is formed so as to leave an insulating film on the gate electrode. 5. A semiconductor device according to claim 4, wherein an insulating film is left on the gate electrode during chemical mechanical polishing, and a metal film, a metal silicide film, or a laminated film thereof is left only in a necessary portion. A method of manufacturing a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 1, wherein said metal film / silicide film or said laminated film is a refractory metal film or a silicide film thereof. Semiconductor device manufacturing method. 7. A method of manufacturing a semiconductor device according to claim 1, wherein a metal silicide film is formed at a contact portion with a silicon substrate by applying a metal film and performing a heat treatment. A method for manufacturing a semiconductor device, wherein a stacked film of films is formed on a high concentration diffusion layer. 8. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 1. 9. A semiconductor device comprising a MOS transistor as a constituent element, comprising a low-concentration diffusion layer below a sidewall spacer and a high-concentration diffusion layer having a metal film, a metal silicide film, or a laminated film thereof outside thereof. A semiconductor device, comprising: 10. The semiconductor device according to claim 9, wherein the area of the polished metal film / metal silicide film or the laminated film thereof is larger than the area of the high concentration diffusion layer.