JPH10199241A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To assure reliability of gate insulation film of an access transistor of a DRAM(Dynamic Random Access Memory) of the word line non-voltage boosting/word line negative voltage system and a word line driver section transistor. SOLUTION: An intermediate voltage for precharging is generated using an array voltage which is lower than the power supply voltage and an array voltage is transmitted as a sense amplifier drive signal to a sense amplifier(SA). A high level potential of bit lines (BL, /BL) for reading high level data is an array voltage level which is lower than the power supply voltage and a voltage difference between the non-selected word line after a negative voltage (-VS) is applied to the non-selected word line and the bit line from which the high level data is read is equal to the power supply voltage level which prevents application of excessive voltage to the gate insulation film of the access transistor. Moreover, a high level data of the gate of word driver transistors (4ac, 4bc) is equal to an array voltage level to prevent application of the voltage higher than the power supply voltage to the gate insulation film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a dynamic semiconductor memory device, and more particularly, to a dynamic random access memory (DRA) integrated with logic on the same chip.
M).

[0002]

2. Description of the Related Art Logic such as a microprocessor has been increasingly operated at a higher speed.
AM also has a large storage capacity and a high operating speed. However, the DRAM has a limit in improving the operation speed due to dynamic operation and address multiplexing. For this reason, the operation speed of the DRAM cannot follow the operation speed of the logic, and the performance of the processing system is determined by the operation speed of the DRAM. This is one bottleneck for improving the performance of the processing system.

In order to bridge the gap between the operation speeds of the logic and the DRAM, recently, the logic and the DRAM are integrated on the same chip. By interconnecting the logic and the DRAM via a bus having a wide bit width, a large amount of data can be transferred collectively without being affected by the number of data input / output pin terminals of the DRAM. In addition, the internal wiring has a smaller load and can transfer data at a higher speed than the wiring on the board on the printed circuit board.

In such an LSI (Large Scale Integrated Circuit) in which DRAM and logic are mixed, it is necessary to make DRAM and logic manufacturing processes as common as possible in order not to sacrifice performance and cost. is there. From this point of view, logic and DRAM
The thickness of the gate insulating film of the insulated gate field effect transistor (hereinafter, referred to as MOS transistor), which is a component of the above, is made equal. For example, in a DRAM and a logic manufactured under the same manufacturing standard (the same integration degree), the thickness of the gate insulating film of the MOS transistor of the DRAM is 110 °, while the thickness of the gate insulating film of the MOS transistor of the logic is Is set to 70 °. DR
When AM and logic are mixed on the same chip,
The thickness of the gate film of the MOS transistor of the DRAM is set to 70 ° similarly to the case of the logic, so that the manufacturing process of the DRAM and the logic is shared. As a result, cost can be reduced while maintaining performance.

FIG. 20 shows a DRAM mixed with logic.
FIG. 3 is a diagram showing an example of a configuration of a main part of FIG. In FIG.
2 schematically shows a configuration of a memory cell array unit. In this memory cell array, memory cells MC are arranged in a matrix of rows and columns, and word lines WL correspond to each row.
Are arranged, and bit line pairs are arranged corresponding to the respective columns. A memory cell in a corresponding row is connected to word line WL, and a memory cell in a corresponding column is connected to a bit line pair. In FIG. 20, four word lines WL0 to WL
3 and a pair of bit lines BL and / BL are representatively shown.

Word lines WL1 and WL2 and bit line B
Memory cells MC1 and MC3 are arranged corresponding to the intersection of L, and word lines WL1 and WL3 and bit line / B
Memory cells MC2 and MC4 are arranged corresponding to the intersections of L, respectively. Each of the memory cells MC1 to MC4 has a capacitor C for storing information and a capacitor C connected to a corresponding bit line BL (or / BL) in response to a signal potential on a corresponding word line. Access transistor Tc for reading stored information to a corresponding bit line is included. Access transistor Tc
Is composed of n-channel MOS transistors.

A precharge / equalize circuit BPQ for precharging bit lines BL and / BL to intermediate potential VBL during standby is provided for bit line pair BL and / BL. Precharge / Equalize circuit B
PQ is an equalizing transistor T1 that electrically shorts bit lines BL and / BL in response to equalizing signal EQ, and conducts in response to equalizing signal EQ to bit lines BL and / BL from intermediate voltage generating circuit MV. It includes precharge transistors T2 and T3 transmitting precharge voltage VBL. These transistors T1 to T
Each of 3 is composed of an n-channel MOS transistor.

Intermediate voltage generating circuit MV receives an operating power supply voltage (array voltage) VCC of the DRAM and a ground voltage GND, and uses an intermediate voltage of 1/2 of these voltages VCC and GND as bit line precharge voltage VBL. Generate. This intermediate voltage generating circuit MV has an intermediate potential VCC.
/ 2 (GND = 0V) is commonly supplied to the cell plate electrodes CP of the capacitors C of the memory cells MC1 to MC4.

A sense amplifier SA activated for bit lines BL and / BL in accordance with sense amplifier drive signals φP and φN to differentially amplify potentials of bit lines BL and / BL is provided. Sense amplifier S
A includes a P-sense amplifier section composed of cross-coupled p-channel MOS transistors and an N-sense amplifier composed of cross-coupled n-channel MOS transistors. Sense amplifier drive signal φP activates the P sense amplifier, and sense drive signal φN activates the N sense amplifier. The P sense amplifier unit applies the high potential bit lines of corresponding bit lines BL and / BL to power supply voltage V
The potential is raised to the CC level, while the N sense amplifier unit discharges the potential of the low potential bit lines of the bit lines BL and / BL to the ground potential level.

A row selection circuit RSC for decoding an address signal (not shown) for word lines WL0 to WL3 and driving the addressed word line to a selected state is provided. Row select circuit RSC transmits a word line drive signal at the operation power supply voltage VCC level to a selected word line, while transmitting negative voltage -VS to a non-selected word line. Next, the operation of the DRAM shown in FIG. 20 will be described with reference to an operation waveform diagram shown in FIG.

In the DRAM, an operation cycle (a standby cycle in a standby state and an active cycle in which a memory selection operation is performed) is determined by a row address strobe signal / RAS shown in FIG. When row address strobe signal / RAS is at a high level, the DRAM is in a standby cycle, and the internal memory cell array is maintained in a precharged state. In this standby cycle, FIG.
Is equal to a high level, the transistor T in the precharge / equalize circuit BPQ
1 to T3 are all in the ON state. Therefore, bit lines BL and / BL are precharged to the voltage level of precharge voltage VBL applied from intermediate voltage generation circuit MV. The word lines WL0 to WL3 are connected as shown in FIG.
As shown in (d), it is in a non-selected state, and is maintained at a voltage -VS level lower than the ground voltage GND. Sense amplifier drive signals φP and φN are at the intermediate potential level as shown in FIG. 21 (e), and sense amplifier SA is inactive. The reason why the word line in the non-selected state is set to the voltage level of the negative voltage −VS lower than the ground voltage will be described later.

When row address strobe signal / RAS falls to a low level, an active cycle starts,
A memory cell selection operation is started. In response to the fall of row address strobe signal / RAS, equalize signal EQ attains a low level, and all transistors T1-T3 of precharge / equalize circuit BPQ are turned off. In this state, bit lines BL and / BL enter a floating gate state at precharge voltage VBL.

Next, a row address signal (not shown) is taken in in response to the fall of row address strobe signal / RAS and decoded by row select circuit RSC.
The word line WL arranged corresponding to the row addressed by the row address signal is selected, and the potential of the selected word line WL rises to the high level of the operation power supply voltage VCC. In FIG. 21C, the word line WL
The case where 0 is driven to the selected state is shown as an example.
When the potential of word line WL0 rises, access transistor Tc of memory cell MC (MC1) connected to selected word line WL0 becomes conductive, and memory cell capacitor C is electrically connected to corresponding bit line BL. You.
Charge transfer occurs between the bit line BL and the capacitor C according to the amount of stored charge (stored information) of the capacitor C of the memory cell MC1, and the potential of the bit line BL changes. FIG.
In (f), a state in which high-level storage information is read out to the bit line BL is shown as an example. Since the memory cell capacitor is not connected to the other bit line / BL, bit line / BL maintains the voltage level of precharge voltage BVL.

Voltage Δ read out by bit line BL
When V is sufficiently large, sense amplifier drive signal φP is at the high level of power supply voltage VCC level, and sense amplifier drive signal φN is at the low level of ground voltage GND level, and sense amplifier SA is activated. This sense amplifier SA
, The potentials of bit lines BL and / BL are differentially amplified, the potential of high-level bit line BL is at the level of operating power supply voltage VCC, and the potential of low-level bit line / BL is at the level of ground voltage GND. Is set to Then, a column address signal (not shown) is applied and decoded, a memory cell in a column designated by the decoded column address signal is selected, and data writing or reading is performed on the memory cell in the selected column.

When the operation of accessing the memory cell is completed, the row address strobe signal / RAS rises to the high level, and the potential of the selected word line WL0 becomes negative voltage -VS.
The selected word line WL
Access transistor Tc of memory cell MC1 connected to 0 is turned off. Then, sense amplifier drive signals .phi.P and .phi.N return to the intermediate voltage level, sense amplifier SA is deactivated, and bit lines BL and / BL
The latch operation of the potential of stops.

Next, equalizing signal EQ rises to a high level, and bit lines BL and / BL are precharged to precharge voltage VBL at intermediate voltage VCC / 2 level by precharge / equalize circuit BPQ.

As is apparent from the operation waveform diagram shown in FIG. 21, the voltages on bit lines BL and / BL change from precharge voltage VBL to operation power supply voltage VCC or ground voltage GND. Therefore, bit lines BL and / or
The voltage amplitude of BL becomes VCC / 2, the time required for bit lines BL and / BL to be set to the high level and the low level in the read memory cell data, respectively, is shortened, and bit lines BL and / BL are set at an earlier timing. The voltage level of BL can be set to a fixed state. As a result, the access timing to the selected memory cell can be accelerated, and high-speed access can be performed.

The cell plate voltage VCP is changed to the intermediate voltage VCC.
The voltage level of / 2 is set for the following reason. D
As the storage capacity of the RAM increases and the degree of integration increases, the area occupied by the memory cells decreases, and accordingly, the area occupied by the memory cell capacitors also decreases. The potential difference (read voltage) ΔV between bit lines BL and / BL shown in FIG. 20 is detected and amplified by sense amplifier SA, and the memory cell data is read. In order for the sense amplifier SA to accurately perform the sensing operation, it is desirable that the value of the read voltage ΔV be as large as possible. The magnitude of the read voltage ΔV is substantially proportional to the ratio of the capacitance Cb of the bit line BL (or / BL) to the capacitance Cs of the memory cell capacitor C, Cs / Cb. Therefore, the capacitance value Cs of the capacitor C needs to be as large as possible.

The capacitance value of the memory cell capacitor is determined by the facing area between storage node SN and the cell plate and the distance between cell plate CP and storage node SN. In order to realize a sufficiently large capacity value of the memory cell capacitor, this memory cell capacitor C
The thickness of the insulating film is made as thin as possible. In order to guarantee the withstand voltage characteristic of the memory cell capacitor C having such a thinned capacitor insulating film, the cell plate voltage V
A voltage of the intermediate voltage VCC / 2 is applied as CP, and the voltage applied between the storage node SN of the memory cell capacitor C and the cell plate CP is changed to the intermediate voltage VCC / 2.
At the voltage level.

Next, a negative voltage -V is applied to the unselected word line.
The reason for applying S will be described.

Generally, a MOS transistor is turned off when the potentials of its gate and source are equal. However, in this state, current does not flow at all through the MOS transistor, but a current called "tail current (subthreshold current)" flows. Generally, the threshold voltage Vth is defined as a gate-source voltage when a MOS transistor having a predetermined gate width flows a drain current having a constant current value.

FIG. 22 is a diagram showing the tail current characteristics of the n-channel MOS transistor. The vertical axis shows the drain current IDS flowing through the MOS transistor, and the horizontal axis shows the gate-source voltage VGS. As shown by the curve I1, in the case of the threshold voltage VTHL, the drain current IDS0 having a significant value flows even when the gate-source voltage VGS becomes 0V. In order to reduce the current IDS0 to an almost negligible level, it is necessary to increase the threshold voltage to the value of VTHH. When the gate-source voltage VGS becomes higher than the threshold voltages VTHL and VTHH,
A large drain current IDS flows rapidly. Therefore, in order to make the MOS transistor conductive at high speed, it is preferable to use a MOS transistor having a threshold voltage as low as possible. The tail current characteristic of the p-channel MOS transistor is represented by a curve symmetrical to curves I1 and I2 with respect to the vertical axis shown in FIG. For high-speed operation, it is preferable to use a MOS transistor having a threshold voltage as low as possible (threshold voltage with a small absolute value). However, in the case of a semiconductor memory device, the following problem occurs when such a low threshold voltage MOS transistor is used as an access transistor of a memory cell.

Now, consider two memory cells MCa and MCb in the same column as shown in FIG. Memory cell M
Ca is arranged corresponding to the intersection of word line WLa and bit line BL, and memory cell MCb is arranged corresponding to the intersection of word line WLb and bit line BL. Each of these memory cells MCa and MCb has a capacitor C
And an access transistor Tc.

Now, consider the operation of writing "0" (low level) data to memory cell MCb in a state where "1" (high level) data is stored in memory cell MCa. In this case, the potential of the word line WLa is at the low level of the ground voltage GND level, and the potential on the word line WLb is at the high level.

When writing data "0" to memory cell MCb, the potential of bit line BL is set to the level of ground voltage GND. In this state, access transistor Tc of memory cell MCa has a gate (word line WLa).
And the source (bit line BL) have the same potential.
Therefore, as access transistor Tc, M having a tail current characteristic as shown by curve I1 in FIG.
When the OS transistor is used, in the memory cell MCa, a tail current flows from the memory cell capacitor C to the bit line BL, and the amount of charge stored in the capacitor C of the memory cell MCa decreases. Therefore, the charge retention characteristics of the memory cell are degraded, and the reliability of the semiconductor memory device is impaired. Further, a state occurs in which the data of "1" stored in the memory cell MCa changes to the data of "0" due to the outflow of charges due to the tail current, and a semiconductor memory device that stores data accurately is realized. And the reliability of the semiconductor memory device is also impaired. In this writing operation, during normal data reading, the bit line potential is set to the ground voltage GN by the sensing operation of the sense amplifier.
It also occurs when discharged to the D level.

In order to prevent the stored charge from flowing out due to the tail current, a negative voltage -VS lower than the ground voltage GND is applied to the unselected word line as shown in parentheses in FIG. As a result, the gate potential of the access transistor Tc becomes lower than its source, the gate-source voltage VGS becomes a negative voltage level, the gate-source of the access transistor Tc is brought into a deep reverse bias state, and a tail current flows. To prevent

A negative voltage -VS is applied to this unselected word line.
, The voltage level of the selected word line (word line WLb in FIG. 23) changes to the operating power supply voltage VCC.
Level, and even if the voltage level of the high-level data transmitted to the capacitor C is as low as VCC-VTH,
Information can be reliably stored.

[0028]

Now, as shown in FIG. 24, the word line WLa is set to the selected state, and the memory cell MCa
Is read out on bit line BL. The data "1" read to the bit line BL is amplified to the operating power supply voltage VCC level by a sense amplifier (not shown). In this state, negative voltage -VS is transmitted to non-selected word line WLb. The potential difference VBW between the unselected word line WLb and the bit line BL is expressed by the following equation.

VBW = VCC-(-VS) = VCC + V
S> VCC, that is, the potential difference VBW between the unselected word line WLb and the bit line BL is larger than the operation power supply voltage VCC by the absolute value VS of the negative voltage −VS.

FIG. 25 schematically shows a sectional structure of a memory cell. In FIG. 25, the cross-sectional structure of the memory cell is shown in a simplified form, omitting the interlayer insulating film and the like.

Referring to FIG. 25, a memory cell MC has an N-type impurity region 90 formed on the surface of a semiconductor substrate region 900.
1a and 901b. Impurity region 901a includes an N- type impurity region 901aa having a low impurity concentration and a high concentration N-type (N +) impurity region 901ab formed in impurity region 901aa. Similarly, impurity region 901b includes a low impurity concentration N- type impurity region 901ba and a high concentration N + type impurity region 901bb formed in impurity region 901ba.

Memory cell MC further includes a gate electrode 904 formed on a region between impurity regions 901a and 901b on surface of semiconductor substrate region 900 via gate insulating film 902. These impurity regions 901a, 90
1b and the gate electrode 904 constitute an access transistor.

The memory cell MC further includes an impurity region 9
01b (901bb), and a conductive layer 906 formed via a capacitor insulating film to face the upper flat surface of conductive layer 905. This conductive layer 905 has a plug portion 9 connected to impurity region 901b.
05a and an upper flat surface 905b integrally formed with the plug portion 905a. Conductive layer 906 is connected to cell plate node CP, and gate electrode 904 is connected to word line WL.

In the memory cell MC shown in FIG. 25, impurity regions 901a and 901b have LDDs (Lightly Doped).
ped Drain) structure. With this LDD structure, impurity regions 901a and 901b and gate electrode 9 are formed.
The generation of a high electric field at the boundary portion 04 is suppressed. This LD
In the D structure, first, N-type impurity regions 901aa and 901ba having a low impurity concentration are formed in a self-aligned manner with respect to gate electrode 904. Next, a sidewall insulating film (not shown) is formed on the side of the gate electrode 904, and N-type impurity ions are implanted using the sidewall insulating film as a mask to form high-concentration N-type impurity regions 901ab and 901b.
bb is formed. After the ion implantation step, heat treatment is performed to activate the implanted ions. In this heat treatment step, impurity regions 901aa and 901aa
The N-type impurity of ba diffuses in the lateral direction. As a result, impurity regions 901aa and 901ba and gate electrode 904
A region 910 is formed where. In this overlapping region 910, only a thin gate insulating film is formed.

As described above, the word line WL and the bit line B
When the potential difference of L is VCC + VS, the overlapping region 910
Is applied with a voltage higher than the power supply voltage VCC whose breakdown voltage is guaranteed. The application of the voltage equal to or higher than the operation power supply voltage to the overlapping region 910 is performed as follows.
In a normal access operation, when a sense operation is performed, one of bit lines BL and / BL is driven to operating power supply voltage VCC level and the other is driven to ground voltage GND level. Occurs in half of the memory cells connected to the memory cell. Such repeated application of a high voltage causes a problem that the reliability of the insulating film of the access transistor is reduced.

The problem that the high voltage is applied to the gate insulating film also occurs in the MOS transistor of the circuit portion transmitting the negative voltage -VS to the non-selected word line. That is,
This occurs when a control signal at the power supply voltage VCC level is applied to the gate of a word line driving MOS transistor connected between the word line WL and a node supplying the negative voltage -VS.

An object of the present invention is to provide a highly reliable word line non-boosting type semiconductor memory device.

Another object of the present invention is to provide a highly reliable DRAM suitable for being mixed with logic.

Still another object of the present invention is to provide a word line non-boosting DRAM in which the reliability of a gate insulating film of a MOS transistor as a component is guaranteed.

[0040]

According to a first aspect of the present invention, there is provided a semiconductor memory device including a plurality of memory cells arranged in a matrix and each storing binary data. Each of the plurality of memory cells includes a capacitor for storing binary data, and an access transistor having a threshold voltage and reading out the data stored in the capacitor when conductive.

The semiconductor memory device according to the first aspect further includes a plurality of word lines arranged corresponding to each row, each of which is connected to a control electrode node of an access transistor of a memory cell in a corresponding row; And a plurality of column lines connected to one conduction node of an access transistor of a memory cell in a corresponding column, and a selected word line corresponding to an addressed row according to a given address signal. Row selecting means for driving to the selected voltage level and maintaining the remaining unselected word lines at a non-selected voltage level having a polarity different from the selected voltage, and a column line provided corresponding to each column and corresponding to the activated state. Potential setting means for setting the corresponding column line to a potential level corresponding to the data of the memory cell in accordance with the data of the memory cell read out. This potential setting means is provided with two
Means for setting the potential of the corresponding column line to a level lower than the selection voltage by the absolute value of the threshold voltage of the access transistor when data of a high level of the value is read.

According to a second aspect of the present invention, there is provided a semiconductor memory device, wherein the row selecting means of the second aspect is provided corresponding to each word line, and is provided between a non-selection voltage supply node and a corresponding word line. And means for applying a voltage higher in level than the non-selection voltage to the control electrode node of the transistor element when the corresponding word line is not selected in accordance with the address signal, provided corresponding to the transistor element. .

According to a third aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein the memory capacitor has a storage node connected to a corresponding access transistor, and a cell plate electrode node arranged opposite to the storage node. And The semiconductor memory device according to the third aspect further supplies a voltage of a level substantially equal to half the difference between the selection voltage and the absolute value of the threshold voltage of the access transistor to the cell plate electrode node of the capacitor of the memory cell. And an intermediate voltage generating means.

A semiconductor memory device according to a fourth aspect of the present invention is the semiconductor memory device according to the first aspect, further comprising an intermediate voltage for generating a voltage having a level substantially equal to half the difference between the selection voltage and the threshold voltage of the access transistor. Generating means, and a precharge means provided corresponding to each column line, activated during a standby state of the semiconductor memory device, and transmitting the voltage from the intermediate voltage generating means to the corresponding column line.

According to a fifth aspect of the present invention, in the semiconductor memory device, the row selecting means of the first aspect is provided for each word line, and transmits an unselection voltage to the corresponding word line when activated. Type field effect transistor. The absolute value of the threshold voltage of this insulated gate field effect transistor is
It is set larger than the absolute value of the non-selection voltage.

According to a sixth aspect of the present invention, in the semiconductor memory device, the row selecting means of the first aspect is provided corresponding to each word line, and transmits an unselection voltage to the corresponding word line when activated. Type field effect transistor. Claim 6
The semiconductor memory device further includes a bias to a back gate region of each insulated gate type field effect transistor at a level where the absolute value of the threshold voltage of the insulated gate type field effect transistor is larger than the absolute value of the non-selection voltage Means for applying a voltage are further provided.

According to a seventh aspect of the present invention, there is provided a semiconductor memory device according to the first aspect, further comprising a charge pump means for outputting a voltage having the same polarity as the non-selection voltage to an output node according to a charge pump operation, and the charge pump means. And a diode-connected insulated gate field effect transistor for clamping the voltage of the output node to a non-selection voltage level, and stabilizing the voltage of the output node of the charge pump means. And a capacity. The voltage generated at the output node of the charge pump means is applied to the row selection means and transmitted to a non-selected word line as a non-selection voltage.

According to the semiconductor memory device of the present invention, the absolute value of the threshold voltage of the insulated gate field effect transistor of the present invention is set to a value not more than the absolute value of the threshold voltage of the access transistor of the memory cell. Have been.

According to a ninth aspect of the present invention, there is provided a semiconductor memory device according to the third or fourth aspect, wherein the device is connected between a power supply node for supplying a voltage of a level equal to the selection voltage and an output node, and An insulated gate field effect transistor having a threshold voltage of an absolute value equal to or less than the absolute value of the threshold voltage, transmitting a voltage lower than the selection voltage by the threshold voltage to the output node; And a stabilizing capacitor for stabilizing the voltage of the output node. The voltage of this output node is applied to at least the intermediate voltage generating means.

According to a tenth aspect of the present invention, the semiconductor memory device according to the first aspect is further connected between a power supply node for supplying a voltage having a level equal to the selection voltage and an output node,
An insulated gate field effect that has a threshold voltage of an absolute value less than or equal to the absolute value of the threshold voltage of the access transistor and transmits a voltage lower than the selected voltage by the absolute value of the threshold voltage to an output node It further includes a transistor and a stabilizing capacitor connected to the output node for stabilizing the voltage of the output node. The column lines include bit lines arranged in pairs.

According to a tenth aspect of the present invention, the potential setting means is provided corresponding to the bit line pair, and transmits the voltage from the output node to the high potential bit line of the corresponding bit line pair when activated. Includes multiple sense amplifiers.

According to an eleventh aspect of the present invention, in the semiconductor memory device according to the first aspect, the row selection means generates a word line selection signal of a selected voltage level in response to a word line activation timing signal, Means for transmitting a word line selection signal to a word line provided corresponding to the addressed row. The word line selection signal generating means is connected between an output node and a non-selection voltage supply node, and transmits an unselected voltage level to the output node when conducting. Means for applying a voltage substantially equal to the sum of the non-selection voltage and the selection voltage to the gate of the insulated gate field effect transistor when the activation timing signal is inactivated. Output nodes are connected to corresponding word lines.

According to a twelfth aspect of the present invention, in the semiconductor memory device according to the first aspect, the row achieving means generates a word line group designation signal for designating a predetermined number of word lines in accordance with a given first address signal. Means for generating a word line specifying signal for designating one word line of the set of the predetermined number of word lines according to a given second address signal. The word line specifying signal generating means includes a specifying signal generating circuit provided corresponding to each word line of the set. Each of the designation signal generating circuits is provided between an output node coupled to a corresponding word line and a non-selection voltage supply node, and transmits an unselection voltage to this output node when conducting. And provided in correspondence with each of the insulated gate field effect transistors.
A decoding circuit for applying a voltage substantially equal to the level of the sum of the selection voltage and the non-selection voltage to the gate of the insulated gate field effect transistor in accordance with the address signal of A word for transmitting a word line specifying signal to a corresponding word line in accordance with the word line group specifying signal in accordance with the group specifying signal and the word line specifying signal, thereby transmitting a voltage of a selected voltage level to the addressed word line. Includes line drive circuit.

According to a thirteenth aspect of the present invention, in the semiconductor memory device according to the first aspect, the row selection means generates a word line selection signal of a selected voltage level in response to a word line activation timing signal; To the word line corresponding to the addressed row. The word line selection signal generation means is connected between the output node and the non-selection voltage supply node, is turned on in response to activation of the word line selection operation activation timing signal, and supplies a voltage of the selected voltage level to the output node. , And an insulated gate field effect transistor. The absolute value of the threshold voltage of the insulated gate field effect transistor is set larger than that of the access transistor.

According to a fourteenth aspect of the present invention, the row selection means of the first aspect generates a signal for designating a predetermined number of word line sets of a plurality of word lines in accordance with a given first address signal. Word line group designation signal generation means, and means for generating a word line group designation signal designating a set of a predetermined number of word lines according to a given second address signal;
Means for generating a word line specifying signal designating one word line of a predetermined number of word line sets according to a given second address signal. The word line specifying signal generating means includes a specifying signal generating circuit provided corresponding to each word line of a set of a predetermined number of word lines. Each of the designation signal generation circuits is provided corresponding to an output node, an insulated gate field effect transistor that transmits a voltage of a non-selection voltage level to the output node when conducting, and a word line,
A word line drive for transmitting a word line specifying signal to a word line specified by the word line group specifying signal in accordance with the word line group specifying signal and the word line specifying signal to drive the addressed word line to a selected voltage level Including circuits. The absolute value of the threshold voltage of the insulated gate field effect transistor is made larger than that of the access transistor.

In the device according to the first aspect, the voltage of the column line to which the high-level data has been transmitted is driven only to a voltage level equal to the difference between the absolute values of the selection voltage and the non-selection voltage. Therefore, the potential difference between the unselected word line and the column line from which the high-level data has been read becomes the selected voltage level, and only a voltage of a voltage level whose reliability is guaranteed is applied to the access transistor. Reliability is guaranteed.

In the device according to the second aspect, a voltage having a level higher than the non-selection voltage by the selection voltage is applied to the gate of the transistor element for driving the word line to the non-selection state. Therefore, the potential difference between the control electrode node of this transistor and the conduction node receiving the non-selection voltage is at the selection voltage level, and the reliability of the transistor element driving this word line to the non-selection state is guaranteed.

In the device according to the third aspect, a voltage that is half the difference between the selection voltage and the absolute value of the threshold voltage of the access transistor is applied to the cell plate of the memory cell capacitor. Therefore, when the potential of the high-level data stored in the capacitor is the difference between the selection voltage and the absolute value of the threshold voltage of the access transistor, and the low-level data is at the ground voltage level, the cell plate potential is reliably reduced. Can be set at an intermediate potential level between the high level data and the low level data, and the read voltage at the time of high level data read and the low level data read can be made equal (the absolute value of the accumulated charge amount is Equal, just the signs are different).

In the device according to the fourth aspect, the column line is precharged to a voltage level that is half the difference between the selection voltage and the absolute value of the threshold voltage of the access transistor. Therefore, the column line potential can be reliably set at an intermediate voltage level between the high level data and the low level data. Based on this intermediate voltage, the potential changes at the time of reading the high level data and the low level data become equal, The operation can be performed reliably.

In the device according to the fifth aspect, the absolute value of the threshold voltage of the insulated gate field effect transistor for driving the word line to the non-selected state is made larger than the absolute value of the non-selected voltage. When the insulated gate field effect transistor is non-conductive, a leakage current from the selected word line to the non-selected voltage supply node can be reduced.

According to a sixth aspect of the present invention, a bias voltage is applied to a back gate of an insulated gate field effect transistor for driving a word line to a non-selected state, and the absolute value of the threshold voltage is adjusted. By adjusting the bias voltage level, it is possible to effectively reduce the leak current when the insulated gate field effect transistor is not conducting.

In the device according to the seventh aspect, the non-selection voltage level is determined by the diode-connected insulated gate field effect transistor, so that the non-selection voltage can be easily generated. By using the insulated gate field effect transistor of the element, it is possible to easily generate a voltage having a difference between the absolute values of the selection voltage and the non-selection voltage.

In the semiconductor memory device according to the present invention, the absolute value of the threshold voltage of the insulated gate field effect transistor for clamping is substantially equal to or less than the absolute value of the threshold voltage of the access transistor. As a result, the leakage current through the non-conductive transistor in the word line driver can be suppressed.

In the device according to the ninth aspect, the intermediate voltage is generated by lowering the absolute value of the threshold voltage of the insulated gate field effect transistor, so that the intermediate voltage required easily can be generated. can do.

According to a tenth aspect of the present invention, a voltage having a reduced absolute value of the threshold voltage of the insulated gate field effect transistor is transmitted by a sense amplifier to a bit line from which high level data is read. Therefore, the potential of the bit line from which high-level data has been read can be easily set to a predetermined voltage level.

In the device according to the eleventh aspect, when the gate of the insulated gate field effect transistor for driving the word line to the selected state is not selected, a level equal to the sum of the non-selection voltage and the selection voltage is applied. Voltage is applied,
The voltage between the gate of the word line selection transistor and one of the conduction nodes can be set to the selection voltage level, and the reliability of the gate insulating film is guaranteed.

According to a twelfth aspect of the present invention, the gate voltage of the insulated gate field effect transistor of the word line drive signal generator for generating the word line drive signal by the predecode method is equal to the difference between the selection voltage and the non-selection voltage. Since the voltage level is set, it is possible to prevent a voltage higher than the reliability of which is guaranteed from being applied to the gate insulating film of the insulated gate field effect transistor in generating the word line drive signal.

In the device according to the thirteenth aspect, the absolute value of the threshold voltage of the insulated gate field effect transistor transmitting the selection voltage to the word line is made larger than the absolute value of the non-selection voltage. It is possible to reduce a leak current when the insulated gate field effect transistor is off.

According to a fourteenth aspect of the present invention, in the word line drive circuit of the predecode system, the absolute value of the threshold voltage of the insulated gate field effect transistor for driving this word line to the selected state is the non-selection voltage. It is larger than the absolute value, and it is possible to reduce the leakage current when the insulated gate field effect transistor is not conducting.

[0070]

[First Embodiment] FIG. 1 schematically shows a structure of a main part of a DRAM according to a first embodiment of the present invention. FIG. 1 shows only the configuration of a portion operating in association with row address strobe signal / RAS. In order to simplify the drawing, the configuration of a portion related to the column selecting operation is not shown.

In FIG. 1, a DRAM is a memory cell array 1 having a plurality of memory cells arranged in a matrix.
And a row decoder 2 for decoding an internal row address signal provided from an address buffer (not shown), and decoding a predetermined number of bits of the internal address signal when activated,
According to a word line drive signal generating circuit 3 for generating a word line drive signal, a decode signal from the row decoder 2 and a word line drive signal from the word line drive signal generator 3
Word line drive circuit 4 for driving an addressed row of memory cell array 1 to a selected state is included.

The row decoder 2 generates a decode signal for designating a set of a plurality of word lines in the memory cell array 1, as will be described later in detail. Word line drive signal generation circuit 3 receives timing signal φX,
And decodes a predetermined number of bits of the internal address signal,
A word line drive signal φW for selecting one of the plurality of word line sets is generated.

Word line drive circuit 4 transmits word line drive signal φW from word line drive signal generation circuit 3 to a set of a plurality of word lines designated by row decoder 2. This word line drive circuit 4 has a negative voltage −VS as a non-selection voltage applied from negative voltage generation circuit 5.
To the unselected word line of the memory cell array 1. The word line drive signal generating circuit 3 includes an input stage that operates with an operation power supply voltage VCC as a selection voltage and a ground voltage as both operation power supply voltages, a power supply voltage VCC and a negative voltage as a non-selection voltage (hereinafter simply referred to as negative voltage). VS), and an output stage for level conversion that operates using -VS as both operation power supply voltages. Therefore, word line drive signal φW output from word line drive signal generation circuit 3 is not connected to power supply voltage VCC.
And negative voltage -VS.

The DRAM further includes an internal voltage generating circuit 6 for generating an internal voltage (hereinafter, referred to as an array voltage) VCI lower than the power supply voltage from power supply voltage VCC and ground voltage, and internal voltage generating circuit 6 Array voltage V from
Intermediate voltage generating circuit 7 receiving CI and ground voltage to generate intermediate voltages VBLI and VCPI between array voltage VCI and ground voltage GND is included. Intermediate voltage VBLI from intermediate voltage generating circuit 7 is applied to a bit line precharge / equalize circuit included in memory cell array 1, and is used to precharge each bit line to this intermediate voltage level in a standby state. Can be The intermediate voltage VCPI is applied to a cell plate of a capacitor of a memory cell included in the memory cell array 1.

The DRAM is further activated in response to sense amplifier activation signals / φPA and φNA, and outputs a sense amplifier drive signal φP and φN, and a sense amplifier drive circuit 8 and each column of memory cell array 1 (bits). And a sense amplifier circuit 9 for detecting, amplifying and latching memory cell data read into a corresponding column in accordance with sense amplifier drive signals φP and φN. Sense amplifier drive signal φP is set to the level of array voltage VCI when activated. Sense amplifier drive signal φP is applied to a P sense amplifier unit included in sense amplifier circuit 9, and is set at the level of array voltage VCI when activated. Sense amplifier drive signal φN is applied to an N sense amplifier unit included in sense amplifier circuit 9, and is set to the level of ground voltage GND when activated.

The DRAM further operates using power supply voltage VCC and ground voltage GND as both operating power supply voltages, and receives RAS receiving an external row address strobe signal / RAS.
A buffer 10 and a word line which operates using power supply voltage VCC and ground voltage as both operation power supply voltages and drives word line selection operation activation signal φX to an active state at a predetermined timing in accordance with an internal row address strobe signal from RAS buffer 10. The selection activation circuit 11 operates using the power supply voltage VCC and the ground voltage GND as both operation power supply voltages, and responds to activation of an output signal of the word line selection activation circuit 11 at a predetermined timing in response to activation of an output signal. Amplifier activation circuit 1 for driving / φPA and φNA to an active state
2 inclusive.

To the sense amplifier circuit 9, the array voltage VCI
By applying a sense amplifier drive signal φP of a level to perform a sensing operation, in memory cell array 1, the bit line potential rises only to array voltage VCI. This array voltage VCI is at a voltage level lower than power supply voltage VCC. Therefore, it is possible to prevent a voltage higher than the power supply voltage from being applied to the gate insulating film of the access transistor of the memory cell. Also, according to the array voltage VCI, the intermediate voltages VBLI and VCB
By generating PI, it is possible to accurately set the voltage level to exactly the middle of the potential amplitude of the bit line, and to perform an accurate sensing operation. Next, a detailed configuration of each unit will be described.

FIG. 2 is a diagram showing a specific configuration example of the DRAM shown in FIG. In FIG. 2, two word lines W
The structure of a portion related to La and WLb and a pair of bit lines BL and / BL is representatively shown. Word line WL
a corresponding to the intersection of bit line / BL with memory cell MC
a, and a memory cell MCb is arranged corresponding to the intersection of the word line WLb and the bit line BL. Each of memory cells MCa and MCb includes a capacitor C and an access transistor Tc formed of an n-channel MOS transistor. Intermediate voltage VCPI from intermediate voltage generating circuit 7 is applied to cell plate electrode node CP of capacitor C of memory cells MCa and MCb.

A precharge / equalize circuit BPQ for transmitting intermediate voltage VBLI from intermediate voltage generation circuit 7 to bit lines BL and / BL in response to equalize signal EQ is provided for bit line pair BL and / BL. Can be This precharge / equalize circuit BPQ is shown in FIG.
0, includes an equalizing n-channel MOS transistor T1 and precharging n-channel MOS transistors T2 and T3. Sense amplifier SA included in sense amplifier circuit 9 includes p-channel MOS transistors PQ1 and PQ2 whose gates and drains are cross-coupled, and n-channel MOS transistors NQ1 and NQ2 whose gates and drains are cross-coupled. p channel MOS transistor PQ
1 and PQ2 are supplied with a sense amplifier drive signal φP to a connection node (source). Sense amplifier drive signal φN is applied to a connection node (source) of n-channel MOS transistors NQ1 and NQ2. For signal lines transmitting these sense amplifier drive signals φP and φN,
A precharge / equalize circuit having the same configuration as the bit line precharge / equalize circuit BPQ is provided.
It is not shown in FIG.

The sense amplifier drive signals φP and φN
Is activated (low level) when the sense amplifier activation signal / φPA is activated, and transmits the array voltage VCI from the internal voltage generation circuit 6 to activate the sense amplifier drive signal φP. P-channel MOS
Transistor 8a includes an n-channel MOS transistor 8b which conducts when sense amplifier activation signal φNA is activated (high level) and transmits the ground voltage level to drive sense amplifier drive signal φN to the ground voltage level.

Internal voltage generating circuit 6 for generating array voltage VCI has an n-channel diode-connected and connected between power supply voltage supply node VCC (the power supply voltage and its node are denoted by the same reference numerals) and output node NDa. MOS
It includes a transistor 6a and a stabilizing capacitor 6b having a relatively large capacitance value connected between output node NDa and a ground node. From this output node NDa, array voltage VC
I is output. MOS transistor 6a has the same gate insulating film thickness as access transistor Tc, and has a threshold voltage substantially equal to the threshold voltage of access transistor Tc. Therefore, array voltage VCI attains the voltage level of VCC-VTH. Here, VTH indicates a threshold voltage of the MOS transistor 6a (access transistor Tc).

Row decoder 2 has a row decode circuit 2a provided commonly to word lines WLa and WLb.
And an inverter 2b that operates using the power supply voltage VCC and the ground voltage as both operating power supply voltages to invert the output signal of the row decode circuit 2a, and receives the power supply voltage VCC at its gate and transmits the output signal of the inverter 2b to the node 2d. Includes n-channel MOS transistor 2c. When the output signal of inverter 2b is at a high level (power supply voltage VCC level), MOS transistor 2c has its threshold voltage V
The value is reduced by TH and transmitted to output node 2d. This MO
The threshold voltage of S transistor 2c is also substantially equal to the threshold voltage of access transistor Tc. In the following description, unless otherwise specified, in a DRAM mixed with this logic, the thicknesses of the gate insulating films of the MOS transistor of the logic part and the MOS transistor of the DRAM are all equal. Therefore, it is assumed that the threshold voltages of these MOS transistors are all equal.

The word line drive circuit 4 is connected to the word line WL
and a word line driver 4b provided for word line WLb
including. An output signal of row decode circuit 2a is commonly applied to these word line drivers 4a and 4b. Word line driver 4a receives power supply voltage VCC at its gate and transmits an output signal of row decode circuit 2a to n-channel MOS transistor 4aa.
When a signal transmitted via transistor 4aa is at a high level, n channel MOS transistor 4ab transmitting word line drive signal φW1 to word line WLa is provided between negative voltage supply node 4c and word line WLa. Includes n channel MOS transistor 4ac having a gate connected to node 2d.

The word line driver 4b is connected to the power supply voltage VCC.
Is applied to the gate to transmit the output signal of row decode circuit 2a.
When the signal transmitted from the OS transistor 4ba is at a high level, the transistor is turned on, and the word line drive signal φW2 is supplied to the word line WLb.
-Channel MOS transistor 4bb for transmitting the voltage to word line WLb and negative voltage supply node 4c and having its gate connected to node 2d.
Includes S transistor 4bc.

Word line drive signals φW1 and φW2 are
As will be described in detail later, one of them is set to the power supply voltage level in the active state, and the other is set to the negative voltage −VS level in the inactive state. Row decode circuit 2a
Selects a set of two word lines, and one of the two word lines is connected to word line drive signals φW1 and φW2.
Is driven to the selected state. The number of word lines WL simultaneously selected by one row decode circuit 2a is
It is determined by the relationship between the pitch of L and the pitch of the row decode circuit 2a. 4 for one row decode circuit 2a
A configuration in which one or eight word lines are provided may be used. In this case, one of the four word line sets or eight word line sets is driven to the selected state by the word line drive signal.

Negative voltage generating circuit 5 is connected between a capacitor 5a performing a charge pump operation in accordance with a clock signal φ output from, for example, an on-chip ring oscillator not shown, and one electrode node of capacitor 5a and a ground node. An n-channel MOS transistor 5b having its gate connected to one electrode node of capacitor 5a, and an n-channel MOS transistor connected between one electrode node of capacitor 5a and output node NDb and having its gate connected to output node N
N channel MOS transistor 5c connected to Db
And an n-channel MOS connected between output node NDb and the ground node and having its gate connected to the ground node
Transistor 5d and a stabilizing capacitor 5e connected between output node NDb and the ground node and having a relatively large capacitance value for stabilizing the potential of ground node NDb are included. MOS transistors 5b, 5c and 5d operate as diodes.

In the operation of negative voltage generating circuit 5, when clock signal φ rises to a high level, capacitor 5
The potential of one electrode node of c rises, MOS transistor 5b conducts, and clamps the potential of one electrode node of capacitor 5a to its threshold voltage VTH level.
When clock signal .phi. Falls to a low level (ground voltage level), MOS transistor 5b is turned off, and one electrode node of capacitor 5a drops to the VTH-VCC level. As a result, the MOS transistor 5c conducts, and lowers the potential of the output node NDb. MOS
Transistor 5c is turned off when the potential of output node NDb is higher than the potential of one electrode node of capacitor 5a by the threshold voltage of MOS transistor 5c.

Therefore, the potential of output node NDb finally becomes 2 · VTH− by this charge pump operation.
It drops to the VCC level. However, when the potential of the output node NDb drops below the -VTH level,
MOS transistor 5d conducts, and output node ND
The voltage level of b is increased. Therefore, output node N
The voltage level of Db becomes -VTH level (ground voltage is set to 0 V). The negative voltage −VS of this output node NDb
(= −VTH) is stably held by the stabilizing capacitance 5 e and supplied to the negative voltage supply node 4 c of each word line driver of the word line drive circuit 4.

FIG. 3 is a diagram showing an example of the configuration of the word line drive signal generating circuit 3 shown in FIG. In FIG. 3, word line drive signal generation circuit 3 includes a word line drive signal generation circuit 3a for generating word line drive signal φW1 for word line WLa, and a word line drive signal for generating word line drive signal φW2 for word line WLb. Includes generation circuit 3b. Word line drive signal generating circuit 3a includes internal row address signal bit RA0 and word line select operation activating signal φX.
, An n-channel MOS transistor 3ab receiving the power supply voltage VCC at its gate and transmitting the output signal of NAND circuit 3aa, and a NAND gate connected between power supply node VCC and output node Nc and having a gate connected to NAND gate 3aa. P-channel MOS transistor 3ac receiving the output signal of circuit 3aa is connected between output node Nc and negative voltage -VS supply node, and has a gate connected to M gate.
N-channel MOS transistor 3ad receiving an output signal of NAND circuit 3aa via OS transistor 3ab
including. From the output node Nc, the word line drive signal φW1
Is output.

Word line drive signal generation circuit 3b has the same structure as word line drive signal generation circuit 3a except that complementary internal row address signal / RA0 is received. MO
S transistors 3ab and 3bb have a threshold voltage V
TH, and transmits a signal of the level of voltage VCC-VTH. Therefore, when the output signal of NAND circuit 3aa or 3ba is at the high level of power supply voltage VCC, MOS
The voltage V is applied to the gate of the transistor 3ad or 3bd.
CC-VTH is provided. The negative voltage -VS is substantially the voltage level of -VTH as described in FIG. Therefore, MOS transistors 3ad and 3ad
The potential difference between the gate and the source of bd becomes the VCC level, and the reliability of the gate insulating films of these MOS transistors 3ad and 3bd is guaranteed. p-channel MOS
Transistors 3ac and 3bc receive at their gates only a signal of ground voltage GND level or a signal of power supply voltage VC level, and also have a potential difference between the gate and source of MOS transistors 3ac and BC. The power supply voltage goes to the VCC level. Next, the operation of the DRAM shown in FIGS. 1 to 3 will be described with reference to an operation waveform diagram of FIG.

When the row address strobe signal / RAS shown in FIG. 4A is at a high level, the DRAM is in a standby state. In this state, equalizing signal EQ shown in FIG. 4B is at a high level, and transistor T1 of precharge / equalizing circuit BPQ shown in FIG.
T3 are all in a conductive state, and transmit intermediate voltage VBLI from intermediate voltage generating circuit 7 to bit lines BL and / BL. Therefore, bit lines BL and / BL are precharged to half the voltage level of array voltage VCI.

The word line selection operation activating signal φX shown in FIG. 4C is also at the low level, and
The word line drive signals φW1 and φW2 shown in FIG. In this state, the output signal of row decode circuit 2a shown in FIG.
The output signal b is at the power supply voltage VCC level. Therefore, the voltage level of output node 2d of the row decoder of FIG. 2 becomes VCC-VTH, and MOS transistors 4ac and 4b included in word line drivers 4a and 4b, respectively.
c is turned on, and the word lines WLa and WLb are supplied with the negative voltage -V.
Hold at S level. The gate-source voltages of MOS transistors 4ac and 4bc are at the level of power supply voltage VCC, so that the reliability of these gate insulating films is guaranteed. Further, sense amplifier activation signals / φPA and φNA shown in FIGS. 4F and 4G are at high level and low level, respectively, and MOS transistors 8a and 8b of sense amplifier drive circuit 8 are both non-conductive. . In this state, sense amplifier drive signals φP and φN are held at an intermediate voltage level (VCI / 2) by a precharge / equalize circuit (not shown).

When row address strobe signal / RAS falls to a low level, an access cycle starts. In response to the fall of row address strobe signal / RAS, equalize signal EQ attains a low level, and transistors T1 to T3 of bit line precharge / equalize circuit BPQ are turned off.

Then, in response to the fall of row address strobe signal / RAS, word line select operation activation signal φ from word line select activation circuit 11 shown in FIG.
X rises to high level. On the other hand, a row address buffer is activated in response to the fall of row address strobe signal / RAS by a path not shown, takes in an external address signal, generates an internal row address signal, and generates a row decoder shown in FIG. Give to 2. Row decoder 2 decodes internal row address signal bits RA1 to RAn from a row address buffer in response to activation of row address strobe signal / RAS. Now, consider a state where word line WLa shown in FIG. 2 is addressed. In this state, the output signal of row decode circuit 2a rises to a high level. As a result, the word line drivers 4a and 4b
S transistors 4ab and 4bb are conductive, MOS
Transistors 4ac and 4bc are turned off.

In parallel with the decoding operation in row decoder 2, a decoding operation is also performed in word line drive signal generating circuit 3 shown in FIG.
The output signal “a” becomes low level, and the output signal of the NAND circuit 3ba becomes high level of the power supply voltage VCC level. As a result, in the word line drive signal generation circuit 3a, the MO
S transistor 3ac is rendered conductive, and word line drive signal φW1 rises to power supply voltage VCC level (FIG. 4).
(D)). On the other hand, in word line drive signal generating circuit 3b, MOS transistor 3bc is off,
OS transistor 3bd is rendered conductive, and word line drive signal φW2 maintains the non-selected negative voltage level. The voltage of the VCC-VTH level is applied to the gate of MOS transistor 3bd via MOS transistor 3bb. Therefore, MOS transistor 3bd
Is at the power supply voltage VCC level, and the reliability of the gate insulating film of this MOS transistor 3bd is guaranteed.

The word line drive signals φW1 and φW2
Is applied to word line drivers 4a and 4b shown in FIG. In word line drivers 4a and 4b, MOS transistors 4ab and 4bb are conductive. When word line drive signal φW1 at power supply voltage VCC level is applied, MOS transistor 4
Due to the self-bootstrap effect of ab, the gate potential of MOS transistor 4ab rises to the level of power supply voltage VCC or higher, and transmits word line drive signal φW1 at this power supply voltage VCC level to word line WLa. At this time, M
OS transistor 4aa has its gate voltage at the level of power supply voltage VCC, maintains the off state, and prevents a voltage higher than power supply voltage VCC from being supplied to the output node of row decode circuit 2a. On the other hand, the word driver 4b outputs the word line drive signal φ of the negative voltage −VS level.
W2 is transmitted to word line WLb. As a result, FIG.
As shown in (e), the word line WLa is connected to the power supply voltage VC.
C level, while the word line WLb is at a negative voltage −
The non-selected state of the VS level is maintained.

In response to the rise of word line WLa, access transistor Tc of memory cell MCa becomes conductive,
The charge stored in capacitor C is supplied to bit line / BL. FIG. 4I shows an example of a waveform when high-level data is read onto bit line / BL.

When the potential difference between bit lines BL and / BL is sufficiently enlarged, sense amplifier activating signal / φPA from sense amplifier activating circuit 12 shown in FIG. 1 falls to a low level, and the sense amplifier is activated. Signal φNA rises to the high level of power supply voltage VCC level (FIG. 4).
(See (f) and (g)). In response to activation of sense amplifier activation signals / φPA and φNA, MOS transistors 8a and 8b of sense amplifier drive circuit 8 are turned on, and sense amplifier drive signal φP is applied to array voltage VCI.
Level and sense amplifier drive signal φN attain the level of ground voltage GND. As a result, sense amplifier SA is activated, the potential of bit line / BL rises to the level of array voltage VCI, and the voltage of bit line BL rises to ground voltage GND.
Drop to the level. When this sensing operation is completed, writing or reading of data to the selected memory cell is performed. At the time of restoration, the potential of the selected word line is at the power supply voltage VCC level, and the high level potential of the bit line is VCC-VT.
H, which ensures that high-level data is rewritten to the memory cell capacitor.

When the memory cycle is completed, row address strobe signal / RAS rises to the high level, and each signal sequentially returns to the standby state.

When the output signal of row decode circuit 2a is at low level (ground voltage level), word driver 4
In a and 4b, MOS transistors 4ab and 4bb are rendered non-conductive, and word line drive signals φW1 and φW2 are not transmitted to the corresponding word lines. On the other hand, MOS transistors 4ac and 4bc conduct, and word lines WLa and WLb maintain the non-selected state at the level of negative voltage -VES. Sense amplifier drive signal φ
By setting P to a voltage level lower than the power supply voltage VCC by the threshold voltage VTH of the MOS transistor, the high level of the bit lines BL and / BL becomes the array voltage VCI (= VCC-VTH) level, The voltage difference between the selected word line and the bit line from which the high-level data has been read becomes the power supply voltage VCC level. This allows
A voltage higher than the power supply voltage can be prevented from being applied to the gate insulating film of the access transistor, and the reliability of the gate insulating film of the access transistor is secured.

Also in word drivers 4a and 4b, a decoupling transistor 2c is provided in the output section of the row decode circuit to lower the gate voltage of the word line discharging MOS transistor by the threshold voltage VTH. The potential difference between the gate and the source of the MOS transistor for discharging the word line is lower than the power supply voltage level, and the reliability of the gate insulating films of these MOS transistors is guaranteed.

As described above, according to the first embodiment of the present invention, the high level of the bit line is set to the array voltage VCI level lower than the power supply voltage. The potential difference between the read bit line and the read bit line becomes the power supply voltage level, which prevents a voltage higher than the power supply voltage from being applied to the access transistor, and guarantees the reliability of the gate insulating film of the access transistor. be able to.

In the row decode circuit, the high level of the gate potential of the MOS transistor for discharging the word line is reduced by a threshold voltage (same as the absolute value of negative voltage -VS) by using a decoupling transistor. Therefore, the voltage difference between the gate and the source of these MOS transistors can be suppressed to the power supply voltage or less, and the reliability of the gate insulating films of these MOS transistors is guaranteed.

Further, since the voltage level of the negative voltage transmitted to the unselected word line is clamped by the MOS transistor, the difference between the selected voltage (array voltage) and the unselected voltage (negative voltage) can be easily determined. Voltage can be generated.

Since the intermediate voltage is generated from the array voltage, that is, the voltage lowered from the power supply voltage to the threshold voltage of the MOS transistor (threshold voltage of the access transistor), the bit line precharge voltage And the cell plate voltage can be reliably set to a voltage level that is 1/2 of the array voltage, and the absolute values of the high-level data read voltage and the low-level voltage read voltage to the bit line can be equalized. The sense operation can be performed accurately (when the read voltage is different between high-level data read and low-level data read, the sense operation timing is set in accordance with the worst case read voltage) And the sense margin becomes small, making it impossible to accurately perform the sensing operation at high speed).

The high-level potential of the bit line is the high-level potential of the memory cell capacitor, so that unnecessary charge of the bit line is not caused and current consumption is reduced.

[Configuration of Intermediate Voltage Generating Circuit] FIG.
FIG. 3 is a diagram showing an example of a configuration of an intermediate voltage generation circuit 7 shown in FIGS. In FIG. 5, an intermediate voltage generating circuit 7 is connected between an array voltage supply node VCI (the array voltage and the supply node are indicated by the same reference numerals) and a ground node, and outputs a first voltage from the array voltage VCI and the ground voltage GND. A first voltage generator 7a for generating a reference voltage, a second reference connected between array voltage supply node VCI and a ground node, and generating a second reference voltage from array voltage VCI and ground voltage GND Voltage generating unit 7b and intermediate voltage VBLI or VBLI at output node 7z according to the reference voltages from first and second reference voltage generating units 7a and 7b.
An output circuit 7c for generating CPI is included.

First voltage generating section 7a includes p-channel MOS transistors 7aa and 7ab and high resistance element 7ac connected in series between array voltage supply node VCI and internal node 7x, internal node 7x and ground. Includes high-resistance resistor element 7ad connected between nodes.
MOS transistors 7aa and 7ab have their gates and drains interconnected, respectively,
It operates in diode mode due to the small current by ac and 7ad. The high resistance elements 7ac and 7ad have substantially the same resistance. A first reference voltage is output from internal node 7x.

The second reference voltage generator 7b is connected in series with each other between a high resistance element 7ba connected between the array voltage supply node VCI and the internal node 7y, and between the internal node 7y and the ground node. High-resistance element 7bb,
Including n channel MOS transistors 7bc and 7bd. MOS transistors 7bc and 7bd have their gates and drains interconnected to each other, and
The device operates in the diode mode by the small current of ba and 7bb. The high-resistance resistance elements 7ba and 7bb are:
The resistance values are made substantially equal. A second reference voltage is output from internal node 7y.

Output circuit 7c is connected between power supply node VCC and output node 7z, and receives a second output from internal node 7y.
An n-channel MOS transistor 7ca having a gate receiving the reference voltage V.sub.a, and a p-channel MOS transistor 7cb connected between output node 7z and the ground node and having a gate receiving a first reference voltage from internal node 7x. Next, the operation will be described.

The resistance values of the resistance elements 7ac and 7ad are
MOS transistors 7aa and 7ab are sufficiently lower than the channel resistance. Therefore, MOS transistors 7aa and 7ab operate in the diode mode, and cause a voltage drop of absolute value VTP of the threshold voltage. Therefore, the potential of the drain node of MOS transistor 7ab is VCI-2 · VTP.
The resistance values of resistance elements 7ac and 7ad are substantially equal. Therefore, a voltage obtained by dividing the potential of the drain node of 7ab of this MOS transistor by 1: 1 is output to internal node 7x. That is, (VCI-2 · VTP) / 2 = VCI / 2 from the internal node 7x.
A voltage having a voltage level of -VTP is output as a first reference voltage and applied to the gate of MOS transistor 7cb.

On the other hand, in second voltage generating section b, the resistance values of resistance elements 7ba and 7bb have sufficiently large channel resistances (on resistances) of MOS transistors 7bc and 7bb, and MOS transistors 7bc and 7bd
Causes a voltage drop of the threshold voltage VTH. Therefore, the drain potential of MOS transistor 7bc is 2 · VTH. The resistance values of resistance elements 7ba and 70bb are equal,
A voltage obtained by dividing the potential difference between the drain voltage of bc and the voltage VCI of the array voltage supply node VCI by 1: 1 is output from the output node 7y. That is, (VCI + 2 ·
A voltage of a voltage level of (VTH) / 2 = VCI / 2 + VTH is applied as a second reference voltage from internal node 7y to the gate of MOS transistor 7ca.

In output circuit 7c, the voltage applied to the gate of MOS transistor 7ca is equal to power supply voltage VC.
C, the MOS transistor 7ca is
It operates in the source follower mode, and transmits a voltage obtained by subtracting threshold voltage VTH from the gate potential of MOS transistor 7ca to output node 7z. That is, MO
S transistor 7ca is connected to output node 7z by VCI / 2
Of voltage.

On the other hand, MOS transistor 7cb also operates in the source follower mode since its gate potential is higher than ground voltage GND, and applies a voltage higher than the gate potential by absolute value VTP of the threshold voltage to output node 7z. introduce. That is, the MOS transistor 7cb
Transmits the voltage of VCI / 2 to output node 7z.

When the voltage level of output node 7z rises, MOS transistor 7cb conducts, and output node 7cb turns on.
The voltage level of z is reduced. On the other hand, when the voltage level of output node 7z decreases, MOS transistor 7ca conducts, and the voltage level of output node 7z increases. Therefore, in output circuit 7c, when one of MOS transistors 7ca and 7cb is in a conductive state, the other is in a non-conductive state and operates in a push-pull mode.

MOS transistors 7ca and 7ca
Since cb operates near the region where each gate-source voltage is equal to each threshold voltage, that is, since MOS transistors 7ca and 7cb operate at the boundary between the non-conductive state and the conductive state, There is almost no through current from the power supply node VCC to the ground node,
The current consumption is reduced. Further, the voltage generation units 7a and 7
b, the MOS transistors 7aa, 7ab, 7
In order to operate bc and 7bd in the diode mode, only a small current is required, and the resistance element 7a
The resistance values of c, 7ad, 7ba and 7bb are sufficiently large, the current flowing through them is also sufficiently small, and the current consumption is reduced.

By using the intermediate voltage generating circuit shown in FIG. 5, the current consumption can be stably reduced with low current consumption.
/ 2 intermediate voltages VBLI and VCPI can be generated.

[Intermediate Voltage Generating Circuit 2] FIG. 6 shows another structure of intermediate voltage generating circuit 7 shown in FIGS. In FIG. 6, intermediate voltage generating circuit 7 includes a reference voltage generating section 7d for generating first and second reference voltages, and an output circuit 7e for generating an intermediate voltage according to the reference voltage from reference voltage generating section 7d. . Reference voltage generator 7d
Is a high resistance element 7da connected between the array voltage supply node VCI and the internal node 7u;
N-channel MOS transistors 7db and 7dc connected in series between u and 7v, and a high-resistance resistance element 7db connected between internal node 7v and the ground node. MOS transistor 7db has its gate connected to internal node 7u, and
dc has its gate connected to internal node 7v. The resistance value of the high-resistance resistance elements 7da and 7db is the channel resistance (ON resistance) of the MOS transistors 7db and 7bc.
MOS transistor 7d
b and 7dc operate in diode mode.

Output circuit 7e is connected between power supply node VCC and output node 7w, and has its gate connected to internal node 7e.
n channel MOS transistor 7ea connected to u
And a p-channel MO connected between output node 7w and the ground node and having its gate connected to internal node 7v
Includes S transistor 7eb. Next, the operation will be described.

When the resistance values of resistance elements 7da and 7dd are equal to each other and R, and the threshold voltage of MOS transistor 7db is VTH and the absolute value of the threshold voltage of MOS transistor 7dc is VTP, the following equation is obtained. .

2.IRR + VTH + VTP = VCII
R = (VCI-VTH-VTP) / 2 where I indicates a current flowing through the reference voltage generator 7d. Internal node 7u
And 7v, the voltages V (7u) and V (7v) are given by the following equations, respectively.

V (7u) = VCI-IR = VCI / 2
+ (VTH + VTP) / 2V (7v) = V (7u) -V
TH−VTP = VCI / 2− (VTH + VTP) / 2M
Each of the OS transistors 7ea and 7eb operates in the source follower mode, and transmits a voltage obtained by subtracting the absolute value of the threshold voltage from its own gate potential to the drain from the source. Therefore, voltage V (7w) output from output node 7w is given by the following equation.

V (7w) = VCI / 2 + (VTP-VT)
H) / 2 When the voltage V (7w) of the output node 7w rises, the p-channel MOS transistor 7eb is turned on to lower the voltage level of the output node 7w.

On the other hand, when the voltage level of output node 7w decreases, MOS transistor 7ea becomes conductive,
The voltage level of voltage V (7w) from output node 7w is increased. Since threshold voltages VTP and VTN have substantially the same value, voltage V output from output node 7w
The voltage level of (7w) is substantially VCI / 2.

In the structure of the intermediate voltage generating circuit shown in FIG. 6, MOS transistors 7ea and 7eb of output circuit 7e operate in a boundary region between a non-conductive state and a conductive state, and operate in a push-pull mode. Because
Current hardly flows from the power supply node VCC to the ground node, and the current consumption is small. Also in the reference voltage generator 7d, the resistance values of the resistance elements 7da and 7dd are sufficiently large and the flowing current is extremely small, so that the consumption current is extremely small.

[Modification of Row Decode Circuit] FIG. 7 shows a structure of a modification of the row decoder. FIG. 7 shows a row decode circuit portion provided for one word driver 4a. 7, the row decode circuit section includes a row decode circuit 2a for decoding internal address signal bits RA0 to RAn, and an inverter circuit 2e with an amplitude limiting function for inverting the output signal of row decode circuit 2a. The word driver 4a has a configuration similar to the configuration shown in FIG. 2, and corresponding portions are denoted by the same reference numerals and description thereof will be omitted. The output signal of the row decode circuit is also supplied to a word line driver 4b (not shown).

Row decode circuit 2a receives a NAND signal 2AA for receiving row address signal bits RA0 to RAn.
And a CMOS for inverting an output signal of the NAND circuit 2aa
Includes inverter 2ab. The output signal of row decode circuit 2a changes between power supply voltage VCC and ground voltage GND.

Inverter circuit 2e is connected to power supply node VCC.
An n-channel MOS transistor 2ea connected between internal node 2ed and diode-connected and connected between internal node 2ed and output node 2ee and having its gate receiving an output signal of row decode circuit 2a
Channel MOS transistor 2eb and output node 2e
and an n-channel MOS transistor 2ec connected between the ground signal e and a ground node and receiving at its gate the output signal of row decode circuit 2e. The output signal from output node 2ee is applied to the gate of discharge MOS transistor 4ac of word line driver 4a.

In inverter circuit 2e, MO
S transistor 2ea operates in the diode mode, and sets the voltage level of internal node 2ed to the voltage level of VCC-VTH. Therefore, this inverter circuit 2
e, the high level voltage level of the output signal is VCC
It becomes -VTH level. The absolute value VS of the negative voltage −VS is
The voltage level is substantially equal to threshold voltage VTH of MOS transistor 2ea. Therefore, FIG.
By using the inverter circuit 2e having an amplitude limiting function shown in FIG.
The maximum value of the gate voltage of the transistor 4ac is represented by VCC-
The voltage level can be set to VTH + VS = VCC, and similarly, the reliability of the gate insulating film of the discharging MOS transistor can be guaranteed.

FIG. 8 is a diagram showing a configuration of a modification of the inverter circuit 2e with an amplitude limiting function shown in FIG. In FIG. 8, inverter circuit 2e having an amplitude limiting function includes p-channel MOS transistors 2ef and n connected in series between power supply node VCC and output node 2ee.
Channel MOS transistor 2eg and output node 2e
and an n-channel MOS transistor 2eh connected between e and the ground node. The gates of MOS transistors 2ef and 2eh are connected to row decode circuit 2a (FIG. 7).
Output signal from the output signal of the input signal. n-channel MOS
The gate and drain of transistor 2eg are interconnected. MOS transistor 2eg operates in the diode mode, causing a voltage drop of its threshold voltage VTH. Therefore, when p-channel MOS transistor 2ef conducts and transmits power supply voltage VCC to MOS transistor 2eg, output node 2ee is applied to VCC.
The voltage of -VTH is transmitted. Therefore, even if the inverter circuit 2e with the amplitude limiting function shown in FIG. 8 is used, the same effect as the configuration shown in FIG. 7 can be obtained.

[Advantage of array voltage VCI being lower than power supply voltage VCC by threshold voltage VTH of access transistor of memory cell] Intermediate voltage generating circuit is lower than the conventional intermediate voltage level of VCC / 2. , VT
A voltage smaller by H / 2 is generated. Therefore, the voltage applied between the electrodes of the memory cell capacitor C becomes V
TH / 2 becomes smaller. Thereby, the voltage stress of the memory cell capacitor can be made smaller than before,
The reliability of the memory cell capacitor is improved. Also, if the reliability of the memory cell capacitor is maintained at the same level as that of the conventional memory cell, the insulator film thickness of the memory cell capacitor can be reduced and the capacitance value can be increased. A voltage can be generated, and a sense operation margin can be increased.

Similarly, the charge level of the bit line is V
TH / 2 is lowered. Therefore, the charging current at the time of precharging the bit line can be reduced (the low-level bit line is precharged to the intermediate voltage level), and the current consumption during the operation of the intermediate voltage generating circuit can be reduced. The charging current I can be expressed by the following equation.

I = f · Cb · ΔVB where f is the operating frequency, Cb is the bit line capacitance, and ΔVB is the bit line charging voltage. Conventionally, VCC / 2, and in the present invention, (VC
(C-VTH) / 2.

Therefore, as is apparent from the above equation, the charging current I can be reduced by lowering the bit line charging level as in the present invention. Further, at the time of the sensing operation, the bit line amplitude is smaller than the conventional configuration by VTH / 2, so that the charge / discharge current at the time of the sensing operation can be reduced, and the bit line amplitude becomes smaller than that of the conventional configuration. The bit line can be set to a potential level according to the memory cell data at high speed, and the access timing can be made faster. Further, the bit line is charged only up to the charging voltage level of the memory cell capacitor, and unnecessary current consumption is suppressed.

[Second Embodiment] FIG. 9 shows a structure of a main part of a DRAM according to a second embodiment of the present invention.
FIG. 9 shows the configuration of one word line driver 4c for one word line WL. In FIG. 9, word line driver 4c responds to an output signal of row decoder 2, n-channel MOS transistor 4ca transmitting word line drive signal φW to word line WL, and responds to an output signal of row decoder 2. , Negative voltage -VS, and word line W
Including n channel MOS transistor 4cb transmitting to L. MOS transistors 4ca and 4cb have threshold voltage VTN. This threshold voltage VTN is set higher than threshold voltage VTH of access transistor Tc included in memory cell MC. this is,
This is realized by increasing the P-type impurity concentration or lowering the N-type impurity concentration of the channel region by ion implantation. Absolute value VS of negative voltage -VS is a voltage level substantially equal to threshold voltage VTH of access transistor Tc.

In word line driver 4c, when MOS transistor 4cb is off, a signal of the ground voltage level is applied to its gate. In this state, M
The gate-source voltage difference of the OS transistor 4cb is
VS. This voltage difference VS is equal to the MOS transistor 4
cb is smaller than the threshold voltage VTN. Therefore,
The sub-threshold current flowing through MOS transistor 4cb is reduced. MOS transistor 4ca
, When the gate potential is at the low level (ground voltage level) and the word line drive signal φW is at the high level (power supply voltage VCC level), the potential of the word line WL is M
Discharged by the OS transistor 4bc and the negative voltage −VS
Level. In this state, the potential difference between the gate and the source of MOS transistor 4ca is VS, which is smaller than threshold voltage VTN of MOS transistor 4ca, and therefore, the flow of the sub-threshold current through MOS transistor 4ca is suppressed. be able to.

By setting the threshold voltage VTN of the MOS transistors 4ca and 4cb of the word line driver 4c higher than the threshold voltage VTH of the access transistor Tc, it is provided for an unselected word line. The sub-threshold current in the word line driver can be suppressed, and the current consumption of the word line driver provided for many unselected word lines can be suppressed.

[Third Embodiment] FIG. 10 shows a structure of a negative voltage generating circuit according to a third embodiment of the present invention. In negative voltage generating circuit 5 shown in FIG. 10, n channel MOS transistor 5f for clamping voltage -VS at output node NDb has its substrate region connected to the ground node. The other points are the same as those of the configuration of the negative voltage generating circuit shown in FIG. 2, and corresponding portions are denoted by the same reference numerals and detailed description thereof will not be repeated.

Negative voltage -VS from negative voltage generating circuit 5
Is supplied to a word line driver 4d provided for the word line WL. In FIG. 10, word line driver 4d includes an n-channel MOS transistor 4da for transmitting word line drive signal φW to word line WL, and an n-channel MOS transistor for transmitting negative voltage −VS to word line WL.
OS transistor 4db is included. These MOS transistors 4da and 4db have the same threshold voltage VTH as the threshold voltage of an access transistor of a memory cell (not shown) or the same threshold voltage VTN as in FIG.
Having.

In the negative voltage generating circuit 5, the clamp M
The substrate region of OS transistor 5f is connected to a ground node (drain). When the substrate region of this MOS transistor 5f is connected to the source (output node NDb), M
OS transistor 5f has threshold voltage VTH (this connection is indicated by a broken line). This MOS transistor 5
When the substrate region of transistor f is connected to the ground node, the bias voltage of the substrate region of MOS transistor 5f is at the ground voltage level, and its threshold voltage is lower than when biased to the negative voltage level of output node NDb. Become smaller. That is, when the substrate region of MOS transistor 5f is connected to the ground node, MOS transistor 5f
Is the MOS transistor 4 included in the word line driver
It has threshold voltage VTN1 smaller than threshold voltages VTH or VTN of da and 4db (and access transistors of memory cells). Therefore, negative voltage -VS has the voltage level of -VTN1. Therefore, MOS transistor 4db of word line driver 4d
When a ground voltage is applied to the gate of
The potential difference between the gate and the source of the transistor 4db becomes smaller than the threshold voltage VTH, and the sub-threshold current of the MOS transistor 4db can be suppressed. This negative voltage -VS is also applied to the word line drive signal generation circuit. Therefore, the low level of this word line drive signal φW also becomes the voltage level of -VTN1. Therefore, even when a signal at the ground voltage level is applied to the gate of MOS transistor 4da, the potential difference between the gate and source of MOS transistor 4da remains at threshold voltage VTH or VTN.
And the sub-threshold current of the MOS transistor 4da can be suppressed.

FIG. 11 is a diagram schematically showing a sectional structure of MOS transistor 5f shown in FIG. In FIG. 11, an N-type impurity region (well) 31 is formed on the surface of a semiconductor substrate region 30. On the surface of the N well 31, a P type well 32 is further formed. This P-type well 32
Inside, a MOS transistor 5f is formed. In other words, MOS transistor 5f has high-concentration N-type (N +) impurity regions 33 and 34 formed on the surface of P-type well 32 at intervals, and a gate on the region between these impurity regions 33 and 34. It includes a gate electrode 35 formed via an insulating film (not shown). The impurity region 33
Connected to the ground node, and has an impurity region 34 having a negative voltage −V
It is connected to the node NDb that outputs S. The P well 32 has a high concentration P type (P +) formed on its surface.
Connected to the ground node via impurity region 36. N well 31 is coupled to receive power supply voltage VCC via a high concentration N type impurity region 37 formed outside P well 32.

Even if impurity region 34 attains a negative voltage -VS level and impurity region 34 and P-type well 32 are biased in the forward direction, N-well 31 and P-type well 32 are biased in the reverse direction. The current in the P-type well 32 can be suppressed from flowing to another region. Thus, even if the substrate region (P-type well 32) is connected to the drain (impurity region 33) having a higher voltage level than the source (impurity region 34), this can be surely performed without adversely affecting other circuit portions. MOS transistor 5f can be operated as a diode.

[Modification] FIG. 12 shows a structure of a modification of the clamping MOS transistor of the negative voltage generating circuit. FIG. 12 shows only this clamp MOS transistor. In FIG.
OS transistor 5g is connected between negative voltage output node NDb and the ground node, and is formed of a p-channel MOS transistor whose gate and substrate region are connected to output node NDb. Even if this p-channel MOS transistor is used as the clamping MOS transistor 5g, its substrate region is used as the drain region (output node NDb).
, The absolute value of the threshold voltage can be reduced and the voltage level of negative voltage −VS can be increased as compared with the case where the substrate region is connected to the source (ground node). it can.

As described above, according to the third embodiment of the present invention, the absolute value of the threshold voltage of the MOS transistor for negative voltage clamping of the negative voltage generating circuit is determined by using the MOS transistor included in the word line driver and Since the threshold voltage of the access transistor is configured to be smaller than the absolute value, a sub-threshold current in a word line driver connected to an unselected word line can be suppressed, and a DRAM with low current consumption can be realized. it can.

[Fourth Embodiment] FIG. 13 shows a structure of a word line drive signal generating circuit 3 according to a fourth embodiment of the present invention. FIG. 13 shows a configuration of a word line drive signal generator for one word line drive signal φW.
In FIG. 13, word line drive signal generating circuit 3c includes a NAND circuit 3ca receiving word line selection operation activating signal φX and internal row address signal bit RA, an inverter 3cb inverting an output signal of NAND circuit 3ca, and a power supply voltage. N-channel MOS transistor 3cd receiving VCC at its gate and transmitting the output signal of inverter 3cb
And a p-channel MOS transistor 3ce connected between the power supply node VCC and the output node Ne and receiving the output signal of the NAND circuit 3ca at its gate, and connected between the output node Ne and the negative voltage supply node. Includes n-channel MOS transistor 3cf receiving an output signal of inverter 3cb applied via MOS transistor 3cd. Threshold voltage VTN of MOS transistor 3cf is set higher than threshold voltage VTH of the access transistor of the memory cell. The threshold voltage of MOS transistor 3cd is the same VTH as that of the access transistor.

In the structure of the word line drive signal generating circuit shown in FIG. 13, when MOS transistor 3cf is non-conductive, a signal of the ground voltage level is applied to the gate via inverter 3cb. At this time, the potential difference between the gate and the source of MOS transistor 3cf is VTH, and threshold voltage V of MOS transistor 3cf is
MOS transistor 3cf
Can be suppressed. When the MOS transistor 3cf is turned on, its gate
The potential difference between the sources is at the power supply voltage level, and the withstand voltage characteristics are guaranteed.

In p channel MOS transistor 3ce, a high level signal of power supply voltage VCC level is applied to its gate when not conducting. In this state, the potential difference between the gate and the source of MOS transistor 3ce is 0 V, and the subthreshold current can be reliably suppressed without particularly increasing the absolute value of the threshold voltage.

As described above, according to the fourth embodiment of the present invention, the threshold voltage of the MOS transistor for holding the word line drive signal in the inactive state in the word line drive signal generation portion is set to the value of the memory cell. Since the threshold voltage is higher than the threshold voltage of the access transistor, a sub-threshold leakage current in the word line drive signal generation circuit can be suppressed.

[Embodiment 5] The threshold voltage of a MOS transistor depends on the voltage VBS between the back gate (substrate region) and the source. In the configuration of the back gate of the access transistor Tc of the memory cell, since this access transistor Tc is a transfer transistor for transmitting a signal, the source / drain region and the back gate are always separated as shown in FIG. Is done.
That is, in the case of an n-channel MOS transistor, the source is a low potential node and the access transistor T
In c, the source changes depending on the signal to be transferred. In this case, a constant bias voltage V is applied to the back gate Tcg of the access transistor Tc.
BB is applied. The bias voltage VBB applied to the back gate is determined in consideration of factors such as noise (substrate current) to the memory cell and reduction of the junction capacitance.
Set to a constant value. When an n-channel MOS transistor is used as access transistor Tc, bias voltage VBB is at a negative voltage level.

The voltage at the source of access transistor Tc depends on the data written in the memory cell. The back gate-source voltage VBS of the access transistor Tc becomes the largest when writing high level data as shown in FIG. 14B (VBS = V
H-VBB: VH is the voltage of high-level data), and the threshold voltage is the largest at this time. The threshold voltage of the MOS transistor in consideration of the back gate bias is expressed by the following equation.

[0151]

(Equation 1)

Here, Vth0 indicates a threshold voltage when the back gate bias voltage VBB is 0 V, and φF
Represents the Fermi level of the substrate region, and K represents a constant.

FIG. 15 shows the relationship between the threshold voltage VTH of this MOS transistor and the back gate-source voltage VBS. The vertical axis indicates the threshold voltage, and the horizontal axis indicates the back gate-source voltage. In FIG. 15, the threshold voltage Vth1 has a source voltage of | VBB |
It shows the threshold voltage at −Vs, that is, the threshold voltage when a negative voltage −VS is applied to the source. The threshold voltage Vth2 is a threshold voltage when the source voltage is 0V. The threshold voltage Vth3 is such that the source voltage is V
H indicates a threshold voltage when high-level data is written. The threshold voltage Vthr indicates a threshold voltage when the back gate-source voltage VBS becomes equal to the threshold voltage.

In Embodiments 1 to 3 described above,
Although it is described that the threshold voltages of the MOS transistors are equal and VTH, the threshold voltages of these MOS transistors can be used properly according to the purpose of use. An example of this application will be described.

[First Application Example] FIG. 16 shows a structure of a first application example of the fifth embodiment of the present invention. FIG. 16 shows the configuration of the internal voltage generation circuit. Referring to FIG. 16, internal voltage generating circuit 6 includes an n-channel MOS transistor 6a connected between power supply node VCC and output node NDa, and a stabilizing capacitor 6b for stabilizing the voltage of output node NDa. The same negative bias voltage VBB as the bias voltage of the back gate of access transistor Tc for stabilizing memory cell output node 6a is applied to the back gate of MOS transistor 6a. in this case,
Since the node NDa rises to a high level, the threshold voltage of the MOS transistor 6a becomes Vth3. Therefore, the array voltage VCI becomes VCC-Vth3. Array voltage VCI is the same as the voltage level transmitted to storage node SN in writing high-level data to the memory cell (the threshold voltage of the memory cell transistor is Vth3 when writing high-level data).
This array voltage VCI is transmitted to a bit line via a sense amplifier. Therefore, it is possible to generate an array voltage having the same voltage level as the high-level data to be written to the storage node SN of the selected memory cell, and it is not necessary to consume more current than necessary, thereby realizing low current consumption. The array voltage VCI is the same as the voltage level of the high-level data written to the storage node SN, so that the required high-level data can be accurately written.

[First Modification] FIG. 17A shows a structure of a first modification of the internal voltage generating circuit. This FIG.
In the configuration shown in (a), the back gate of MOS transistor 6a is connected to output node NDa. Therefore, back gate-source voltage VBS of MOS transistor 6a is 0 V, and the threshold voltage of MOS transistor 6a is Vth0. Therefore, array voltage VCI becomes VCC-Vth0, which is higher than the voltage value of high-level data written to the memory cell. As a result, high-level data of a voltage level of VCC-Vth3 can be accurately written into a memory cell with a margin for writing high-level data.

[Modification 2] FIG. 17B shows a structure of a modification 2 of the internal voltage generating circuit. FIG.
In (b), the back gate of the MOS transistor 6a is connected to the power supply node VCC. That is, the back gate of the MOS transistor 6a is connected to the drain, and the back gate-source voltage VBS becomes equal to the threshold voltage Vthr of the MOS transistor. Therefore, array voltage VCI is equal to VCC-Vthr
The array voltage VCI can be further increased, and high-level data can be written into the memory cells with a margin. By adjusting the threshold voltage of the MOS transistor through adjustment of the back gate potential of the MOS transistor, it is possible to adjust the generated voltage level.

FIG. 18A shows a structure of a word line driver. In FIG. 18A, the word line driver 4c outputs the word line drive signal φW to the word line W.
N channel MOS transistor 4c for transmitting to L
a and n for transmitting negative voltage -VS to word line WL.
Including channel MOS transistor 4cb. These M
Negative bias voltage VBB is applied to the back gates of OS transistors 4ca and 4cb. By applying the negative bias voltage VBB, the threshold voltages of the MOS transistors 4ca and 4cb can be made higher than the threshold voltage VTH of the access transistor of the memory cell. When negative voltage -VS is the threshold voltage -Vth0 shown in FIG. 15, the threshold voltages of MOS transistors 4ca and 4cb can be set to threshold voltage Vth1, and the sub-threshold leakage current can be reduced. Can be reduced.

FIG. 18B shows the connection of the clamp transistor of negative voltage generating circuit 5. Clamp transistor 5h is formed of an n-channel MOS transistor, its substrate region is connected to output node NDb, and its gate and drain are connected to a ground node.
Negative voltage is supplied to output node NDb from charge pump circuit 5g. This negative voltage −VS is equal to the stabilization capacity 5
stabilized by e.

In the case of connection of the back gate of MOS transistor 5b, the back gate and the source have the same potential, and the threshold voltage is Vth0 from the relationship shown in FIG.
, And the negative voltage −VS becomes −Vth0. This threshold voltage Vth0 is equal to the bias voltage VB applied to the back gate.
B becomes lower than the threshold voltage of the access transistor of the memory cell receiving B and the MOS transistors 4ca and 4cb of the word line driver shown in FIG. Therefore, if this negative voltage is used, the sub-threshold leakage current in the word line driver can be sufficiently suppressed.

FIG. 19 is a diagram showing a list of combinations of back gate connections for reducing the sub-threshold current in the word line driver section. In FIG.
Three cases I, II, and III are shown.

In case I, the word line drive transistor has a negative bias voltage VBB on its back gate.
Receive. In this state, the threshold voltage of the word line drive transistor is V
th1. In the case of an N-type transistor, the substrate region of the negative voltage clamp transistor is connected to the output node, and in the case of using a P-type transistor, the back gate is connected to the ground node. In each case,
This back gate is connected to the source. Therefore, the back gate-source voltage is 0 V, and these MO
The threshold voltages of the S transistors are Vth0 (N) and Vth0 (P). Therefore, the negative voltage −VS is
-Vth0 (N) or -Vth0 (P), which is the shallowest negative voltage.

In case II, the back gate of the word line drive transistor is connected to the negative voltage supply node or source. In this connection, the back gate and the source of the word line drive transistor have the same potential, and the threshold voltage of the word line drive transistor is Vth0.

In the negative voltage clamp transistor,
In the case of an N-type transistor, its back gate is connected to a ground node, and in the case of a P-type transistor, its back gate is connected to an output node. In each case, the back gate is connected to the drain, and therefore the absolute values of the threshold voltages of these N-type and P-type transistors are Vthr (N) and Vtr
hr (P). Also in this case, since threshold voltage Vth0 is higher than absolute values Vthr (N) and Vthr (P) of the threshold voltage, the subthreshold current in the word line driver is suppressed.

In case III, the word line drive transistor receives negative bias voltage VBB at the back gate, and its threshold voltage becomes Vth1. On the other hand, in the clamp transistor, the back gate is connected to the drain in both the N-type transistor and the P-type transistor. Therefore, the absolute values of these threshold voltages are Vthr (N) and Vthr (P). Also in this case, threshold voltage Vth1 is equal to absolute values of threshold voltage Vthr (N) and Vthr
(P) and therefore the threshold voltage Vt
h1 is higher than the absolute value VS of the negative voltage −VS, and the subthreshold current in the word line driver is suppressed.

Of the combinations of cases I to III, the combination that can minimize the sub-threshold current is the combination in which the difference between the negative voltage -VS and the threshold voltage of the drive transistor is the largest. III corresponds. On the other hand, in order to reduce the sub-threshold current of the access transistor of the memory cell, it is preferable that the absolute value of the negative voltage -VS is as large as possible. As the negative voltage clamp transistor, it is best to apply the negative voltage bias voltage VBB to its back gate (threshold voltage Vth1). Therefore, the connection of the back gate of the word line drive transistor and the back gate of the negative voltage clamp transistor is appropriately determined in accordance with the actual purpose of use.

Further, from the viewpoint of alleviating the voltage stress of the gate insulating film of the access transistor of the memory cell, the MOS transistor 6a generating the array voltage (FIG. 17)
(See (A) or (B)), the negative voltage V
By applying BB to lower the array voltage VCI (maximizing the threshold voltage of the voltage dropping transistor), it is preferable to use a combination of back gate connections II or III in the case shown in FIG. The selection of the back gate connection in this case is also appropriately selected according to the purpose of practical use.

In the above configuration, the access transistor of the memory cell is formed of an n-channel MOS transistor. However, instead, p
A configuration in which a channel MOS transistor is used as an access transistor may be used. In this case, the word line has a negative voltage in the selected state, and the word line potential has a positive voltage level in the non-selected state.

[0169]

As described above, according to the present invention, since the bit line amplitude is limited to the selected voltage level lower than the ground voltage and the power supply voltage, the voltage higher than the power supply voltage is applied to the access transistor of the memory cell. Voltage can be prevented from being applied, and a voltage higher than the power supply voltage can be prevented from being applied to the gate insulating film of the access transistor, whereby dielectric breakdown can be prevented, and a highly reliable DRAM can be realized. .

Since a voltage of a selection voltage level lower than the power supply voltage is applied to the gates of the MOS transistors transmitting the non-selection voltage, the potential difference between the gate and the source of these MOS transistors is reduced. Can be prevented from exceeding the power supply voltage.
The reliability of the gate insulating film of the S transistor can be guaranteed.

Since the non-selection voltage is generated by clamping the MOS transistor, the sub-threshold current can be easily reduced in another circuit by using the MOS transistor. In addition, by employing a configuration in which the array voltage is reduced from the power supply voltage by the threshold voltage of the MOS transistor, a selection voltage of a required voltage level can be easily generated. Also,
An array voltage having the same voltage level as high-level data written to a memory cell can be easily generated, and there is no need to unnecessarily charge a bit line potential, thereby reducing current consumption.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an entire configuration of a DRAM of the present invention.

FIG. 2 is a diagram specifically showing a configuration of a main part of the DRAM shown in FIG. 1;

FIG. 3 is a diagram specifically showing a configuration of a word line drive signal generation circuit shown in FIG.

FIG. 4 is a signal waveform diagram representing an operation of the DRAM shown in FIGS. 1 to 3;

FIG. 5 is a diagram illustrating an example of a configuration of an intermediate voltage generation circuit illustrated in FIG. 1;

FIG. 6 is a diagram showing another configuration of the intermediate voltage generation circuit shown in FIG.

FIG. 7 is a diagram showing a configuration of a modification of the row decoder shown in FIG. 2;

8 is a diagram showing a configuration of a modification of the inverter shown in FIG. 7;

FIG. 9 is a diagram showing a configuration of a modified example of a word line driver.

FIG. 10 is a diagram showing a configuration of a modification of the negative voltage generation circuit shown in FIG. 2;

11 is a diagram schematically showing a cross-sectional structure of the MOS transistor for negative voltage clamp shown in FIG. 10;

FIG. 12 is a diagram showing a configuration of a modified example of the negative voltage clamp transistor shown in FIG. 1;

13 is a diagram showing another configuration of the word line drive signal generation circuit shown in FIG.

FIGS. 14A and 14B are diagrams respectively showing a source potential when a threshold voltage of a back gate bias voltage of a memory cell access transistor is highest.

FIG. 15 is a diagram showing a relationship between a threshold voltage of a MOS transistor and a voltage between a back gate and a source.

FIG. 16 is a diagram showing a configuration of a modification of the internal voltage generation circuit shown in FIG. 2;

17 is a diagram showing another modification of the internal voltage generation circuit shown in FIG.

FIG. 18A is a diagram illustrating a configuration of a modification of the word line driver, and FIG. 18B is a diagram illustrating another modification of the clamp transistor of the negative voltage generation circuit.

FIG. 19 is a diagram showing a list of combinations of back gate connections of MOS transistors and negative voltage clamping MOS transistors included in a word line driver.

FIG. 20 is a diagram schematically showing a configuration of an array unit of a conventional DRAM.

21 is a signal waveform diagram representing an operation of the DRAM shown in FIG.

FIG. 22 is a diagram showing a sub-threshold current characteristic of a MOS transistor.

FIG. 23 is a diagram for explaining the reason for applying a negative voltage to a non-selected word line in a conventional DRAM.

FIG. 24 is a diagram illustrating a problem of a conventional negative voltage word line type DRAM.

FIG. 25 is a drawing schematically showing a cross-sectional structure of a memory cell of a conventional DRAM.

[Explanation of symbols]

1 memory cell array, 2 row decoder, 2a row decode circuit, 2b inverter, 2c voltage drop MO
S transistor, 2e inverter, 4 word line drive circuit, 4a, 4b, 4c word line driver, 4a
a, 4ab, 4ac, 4ba, 4bb, 4bc, 4c
a, 4cb, 4cc MOS transistor, 5 negative voltage generating circuit, 5f, 5g, 5h Negative voltage clamping MOS
Transistor, 6 internal voltage generating circuit, 6a MOS transistor, 6b stabilizing capacitor, 5e stabilizing capacitor, 7
Intermediate voltage generating circuit, 8 sense amplifier driving circuit, 9 sense amplifier circuit, SA sense amplifier, Tc memory cell access transistor, C memory cell capacitor,
3 Word line drive signal generation circuit, 3cd, 3ce, 3c
f MOS transistor.

Claims (14)

[Claims] 1. Each of the capacitors includes a capacitor for storing binary data and an access transistor for reading data stored in said capacitor when selected, and is arranged in a matrix. A plurality of memory cells, a plurality of word lines arranged corresponding to each of the rows, a plurality of word lines to which control electrode nodes of access transistors of the memory cells of the corresponding rows are connected, and a plurality of word lines arranged corresponding to each of the columns; A plurality of column lines connected to one conduction node of an access transistor of a memory cell in a corresponding column, a selected word line corresponding to an addressed row is driven to a selected voltage level according to a given address signal, and Row selection means for maintaining the non-selected word lines at a non-selection voltage level having a polarity different from the selection voltage, provided for each of the columns, Potential setting means for setting a corresponding column line to a potential level corresponding to the memory cell data according to the memory cell data read to the column line, wherein the potential setting means sets the corresponding column line to a high level of the two values. Means for setting a potential of the corresponding column line to a level substantially lower than the selection voltage by an absolute value of a threshold voltage of an access transistor of the memory cell when data of a level is read.
Semiconductor storage device. 2. The semiconductor device according to claim 1, wherein the row selection unit is provided corresponding to each of the word lines, and includes a transistor element provided between the non-selection voltage supply node and a corresponding word line; Means for applying a voltage substantially higher than the non-selection voltage level to the control electrode node of the transistor element when the corresponding word line is not selected according to the address signal. The semiconductor memory device according to claim 1. 3. The capacitor of the memory cell has a storage node connected to a corresponding access transistor, and a cell plate electrode node arranged opposite to the storage node. 2. The semiconductor according to claim 1, further comprising: an intermediate voltage generating means for applying a voltage of a level substantially equal to half of a difference between the selection voltage and an absolute value of a threshold voltage of the access transistor to a cell plate electrode node. Storage device. 4. An intermediate voltage generating means for generating a voltage of a level substantially equal to half of the difference between the selection voltage and the absolute value of the threshold voltage of the access transistor, provided corresponding to each of the column lines. 2. The semiconductor memory device according to claim 1, further comprising a precharge means activated during a standby state of said semiconductor memory device and transmitting a voltage from said intermediate voltage generating means to said corresponding column line. 5. The row selecting means includes an insulated gate field effect transistor provided corresponding to each of the word lines and transmitting the non-selection voltage to a corresponding word line when activated. 2. The semiconductor memory device according to claim 1, wherein an absolute value of a threshold voltage of the gate type field effect transistor is larger than an absolute value of the non-selection voltage. 6. The row selection means includes an insulated gate field effect transistor provided corresponding to each of the word lines and transmitting the non-selection voltage to a corresponding word line when activated. The semiconductor device further includes means for applying a bias voltage to the back gate region of the insulated gate field effect transistor to a level at which the absolute value of the threshold voltage of the insulated gate field effect transistor is greater than the absolute value of the non-selection voltage. The semiconductor memory device according to claim 1. 7. A charge pump means for generating a voltage having the same polarity as the non-selection voltage by a charge pump operation, provided at an output node of the charge pump means, and clamping the voltage of the output node to the non-selection voltage level. Further comprising a diode-connected insulated gate field effect transistor, and a stabilizing capacitor for stabilizing the voltage of the output node of the charge pump means, wherein the voltage of the output node of the charge pump means is 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is supplied to a row selection means and transmitted as a non-selection voltage to a non-selection word line. 8. The semiconductor memory device according to claim 7, wherein an absolute value of a threshold voltage of said insulated gate field effect transistor is equal to or less than an absolute value of a threshold voltage of an access transistor of said memory cell. 9. A memory device connected between a power supply node for supplying a voltage having a level equal to the selection voltage and an output node and having a threshold voltage substantially equal to or lower than an access transistor of the memory cell. An insulated gate field effect transistor that transmits a voltage lower than the selection voltage by the threshold voltage to the output node; and a stabilization device connected to the output node for stabilizing the voltage of the output node. 5. The semiconductor memory device according to claim 3, further comprising: a storage capacitor; and wherein a voltage of said output node is supplied to at least said intermediate voltage generating means. 10. An access transistor connected between a power supply node for supplying a voltage having a level equal to the selection voltage and an output node, having a threshold voltage having an absolute value equal to or less than an absolute value of a threshold voltage of the access transistor. An insulated gate field effect transistor for transmitting a voltage lower than the selection voltage by the threshold voltage to the output node; and a stabilizing device connected to the output node for stabilizing the voltage of the output node. Each of the column lines includes a bit line arranged in pairs, and the potential setting means is provided corresponding to each of the bit line pairs, and when activated, the potential setting means is provided from the output node. 2. The semiconductor memory device according to claim 1, further comprising a plurality of sense amplifiers for transmitting a voltage to a high potential bit line of a corresponding bit line pair. 11. A row selection means for generating a word line selection signal of the selection voltage level in response to a word line activation timing signal, and a word line selection signal corresponding to an addressed row. Means for transmitting to a word line disposed in the memory cell, the word line selection signal generating means is connected between an output node and a node for supplying the non-selection voltage, and the non-selection is made to the output node when conducting. An insulated gate field effect transistor that transmits a voltage at a voltage level; and at least when the word line activation timing signal is inactivated, the non-selection voltage and the selection voltage are applied to the gate electrode of the insulated gate field effect transistor. Means for applying a voltage at a level substantially equal to the sum.
13. The semiconductor memory device according to claim 1. 12. The row selecting means includes: a word line group designating signal generating means for generating a signal for designating a plurality of sets of the predetermined number of word lines in accordance with a given first address signal; Word line specifying signal generating means for generating a signal designating one word line of the predetermined number of word line sets in accordance with an address signal, the word line specifying signal generating means comprising: A designation signal generation circuit provided corresponding to each of the designation signal generation circuits, wherein each of the designation signal generation circuits is provided between an output node and the non-selection voltage supply node, and supplies the non-selection voltage to the output node when conducting. Gate-type field-effect transistor for transmitting the signal, and the insulated-gate-type field-effect transistor provided corresponding to each of the insulated-gate field-effect transistors according to the second address signal A decode circuit for applying a voltage substantially equal to the sum of the non-selection voltage and the selection voltage to the gate electrode node of the transistor, further provided for each of the word lines; When the word line group designating signal is activated, the word line designating signal is transmitted onto the corresponding word line according to the word signal and the word line designating signal, and the word is driven to the selected word line to the selected voltage level. 2. The semiconductor memory device according to claim 1, comprising a line drive circuit. 13. A row selecting means for generating a word line selection signal at the selected voltage level in response to a word line activation timing signal, wherein the word line selection signal corresponds to an addressed row. Means for transmitting the selected voltage to a word line disposed between the output node and a node for supplying the selected voltage. 2. The semiconductor memory device according to claim 1, further comprising an insulated gate type field effect transistor transmitting a level voltage and having an absolute value of a threshold voltage larger than an absolute value of a threshold voltage of an access transistor of said memory cell. . 14. A word line group designation circuit for generating a word line group designation signal for designating a set of a predetermined number of word lines of the plurality of word lines according to a given first address signal. Signal generating means, and word line specifying signal generating means for generating a word line specifying signal for specifying one word line of the set of the predetermined number of word lines according to a given second address signal, The word line specifying signal generating means has a specifying signal generating circuit provided corresponding to each of the word lines in the set,
Each of the designation signal generating circuits is provided between an output node and a node for supplying the selection voltage, and is an insulated gate field effect transistor that transmits the selection voltage to the output node when conducting; A decoding circuit provided corresponding to each of the field effect transistors, for applying the selection voltage or the non-selection voltage level to the gate of the insulated gate type field effect transistor in accordance with the second address signal; The absolute value of the threshold voltage of the field-effect transistor is larger than that of the access transistor of the memory cell, and further provided corresponding to each word line, wherein the word line group designation signal and the word line identification signal A word line drive circuit for transmitting the word line specifying signal onto a corresponding word line in accordance with 1 semiconductor memory device according.