JPH10173183A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

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Publication number
JPH10173183A
JPH10173183A JP33530096A JP33530096A JPH10173183A JP H10173183 A JPH10173183 A JP H10173183A JP 33530096 A JP33530096 A JP 33530096A JP 33530096 A JP33530096 A JP 33530096A JP H10173183 A JPH10173183 A JP H10173183A
Authority
JP
Japan
Prior art keywords
gate electrode
step
semiconductor substrate
forming
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33530096A
Other languages
Japanese (ja)
Inventor
Makoto Nakamura
誠 中村
Original Assignee
Sony Corp
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, ソニー株式会社 filed Critical Sony Corp
Priority to JP33530096A priority Critical patent/JPH10173183A/en
Publication of JPH10173183A publication Critical patent/JPH10173183A/en
Pending legal-status Critical Current

Links

Abstract

[PROBLEMS] To provide a method of manufacturing a semiconductor device having uniform transistor characteristics and suppressing a short channel effect even when a contact is formed by a self-alignment process. The method is for manufacturing a semiconductor device having an impurity region formed by oblique ion implantation and a self-aligned contact. The method includes a first step of forming a gate electrode pattern 22 on a semiconductor substrate, and oblique ion implantation into the semiconductor substrate from a direction inclined at a predetermined angle with respect to a normal direction of the semiconductor substrate using the gate electrode pattern as a mask. A second step of performing, a third step of forming an insulating film forming an offset oxide film of the gate electrode over the entire surface of the semiconductor substrate, and a third step of forming an offset oxide film 28 on the gate electrode pattern by patterning the insulating film. 4 steps. By performing oblique ion implantation before forming the offset oxide film, it is possible to perform ion implantation with low density dependence (pattern dependence).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a self-aligned contact with impurity regions and source / drain regions formed by oblique ion implantation. Even when having an offset oxide film on the gate electrode to form a self-aligned contact using
The present invention relates to a method for manufacturing a highly-integrated semiconductor device having a pocket region in which the short-channel effect of a transistor is suppressed by reducing the density dependence (pattern dependence) of oblique ion implantation.

[0002]

2. Description of the Related Art In a field effect transistor (FET), it is important to reduce a line width of a gate electrode to shorten a channel length in accordance with a reduction in design rules of a semiconductor device in order to achieve a high-speed operation. Has become. by the way,
With the shortening of the channel length, the short channel effect accompanied by the punch-through phenomenon and the like becomes remarkable. In order to suppress this effect, several methods have been conventionally proposed. One of them is a layer structure in which a pocket region is formed under a gate electrode by pocket ion implantation.

A pocket ion implantation method will be described by taking an NMOS transistor as an example. First, a gate electrode is formed on a p-type Si substrate. Thereafter, using the gate electrode as a mask, ion implantation of B (boron) for forming ap + -type pocket region and As (arsenic) for forming an n-type source / drain region are performed.
Are sequentially ion-implanted. After that, by performing an annealing process, p
Form a + type pocket region. Thus, the region where the impurity concentration increases in the channel region is limited to the source / drain ends, so that phenomena such as bunch-through are suppressed. An oblique ion implantation method is known as a method for implanting an impurity for forming a pocket region, by which an impurity having a sufficient concentration can be introduced into a Si substrate near an edge of a gate electrode.

[0004] In the semiconductor process, photolithography cannot keep up with the reduction of design rules, which is a major obstacle to miniaturization and high density of semiconductor devices. As a solution to this problem, a self-alignment process that can eliminate a design margin for alignment on a photomask is often used. As a typical example of the self-alignment process, for example, there is an example in which a source / drain region is formed by ion implantation using a gate electrode pattern as a mask, and a design margin for mutual alignment is not required. Regarding the formation of wiring, a method of forming a self-aligned contact conducting to a source / drain region using a self-alignment process has been proposed.
From the 3 μm generation onwards, it is considered an essential technology. Although there are several methods for forming a self-aligned contact, a typical example is a process using a silicon nitride (SiN) film as an etching stop film. To apply this self-aligned contact formation process, it is necessary to provide a relatively thick offset oxide film on the electrode layer of the gate electrode in order to maintain electrical insulation between the gate electrode and the upper wiring. Has become essential.

From the above description, in order to manufacture a highly integrated MOSFET which satisfies the fine design rule and suppresses the short channel effect, oblique ion implantation is performed to form a pocket region under the gate electrode. In addition, it is necessary to form a self-aligned contact with the source / drain region. Here, a conventional method for manufacturing an nMOSFET having a pocket region and a self-aligned contact will be described. First, as shown in FIG.
The gate oxide film 14 is formed on the surface of the substrate 2. Next, on the gate oxide film 14, the polysilicon film 16 and Wsi
The tungsten (W) -polycide film 20 is formed by laminating the film 18. Then, the tungsten (W) -polycide film 20 having a laminated structure is resist-patterned into a predetermined gate electrode pattern by anisotropic dry etching to form a gate electrode 22. Next, FIG.
As shown in FIG. 3, an SiOx film 28 constituting an offset insulating film is formed on the entire surface of the substrate, and the SiOx film 28 is further subjected to resist patterning by anisotropic dry etching, so that the offset insulating film 28 is formed on the gate electrode 22. Form. Next, as shown in FIG. 4C, oblique ion implantation is performed to form a p-type impurity pocket region using the pattern of the gate electrode 22 as a mask, and a p + -type pocket region is formed in the Si substrate 12. 24 are formed.

[0006]

However, MOSFETs
In the above-described conventional manufacturing method, as the distance between the gate electrodes is reduced, the ion incidence is affected by the shadowing effect of the gate electrode when the pocket region is formed, and the impurity reaches below the edge of the gate electrode. And it becomes difficult to form a pocket region below the gate electrode. In particular, when an offset oxide film is provided on a conductive layer of a gate electrode in order to apply a self-aligned contact forming method using a silicon nitride (SiN) film as an etching stop film, as shown in FIG. This problem was remarkable.

Accordingly, an object of the present invention is to provide a case where an offset oxide film is indispensable on an electrode layer of a gate electrode in order to apply a self-aligned contact forming method using a silicon nitride (SiN) film as an etching stop film. Even if at all, an object of the present invention is to provide a method of manufacturing a semiconductor device having a pocket region that effectively suppresses a short channel effect.

[0008]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an impurity region formed by oblique ion implantation and a self-aligned contact. A first step of forming a gate electrode pattern on the transistor formation region of the semiconductor substrate, and oblique ion implantation into the semiconductor substrate from a direction inclined at a predetermined angle with respect to a normal direction of the semiconductor substrate using the gate electrode pattern as a mask. A second step of forming an offset oxide film on the gate electrode pattern, a third step of forming an insulating film constituting an offset oxide film of the gate electrode over the entire surface of the semiconductor substrate, and a third step of patterning the insulating film to form an offset oxide film on the gate electrode pattern. It is characterized by having four steps.

Preferably, in the second step, a pocket region is formed in the semiconductor substrate by oblique ion implantation of impurities of the same conductivity type as the semiconductor substrate. In the case where an LDD sidewall is formed on the side wall surface of the gate electrode and the semiconductor device has an LDD structure, a fifth step of forming an LDD sidewall on the side wall surface of the gate electrode pattern is performed following the fourth step. Provide. In this case, in the second step, an impurity of the same conductivity type as that of the semiconductor substrate is obliquely ion-implanted to form a pocket region in the semiconductor substrate, and an impurity of the conductivity type opposite to that of the semiconductor substrate is ion-implanted to form an LDD. An impurity region is formed.

According to the method of the present invention, an impurity region is formed under a gate electrode by oblique ion implantation. An offset oxide film is provided on the gate electrode, and a source / drain region is formed by using a silicon nitride film as an etching stop layer. And a method of forming a self-aligned contact. As a result,
A highly integrated semiconductor device having a pocket region for suppressing a channel effect and a self-aligned contact with a source / drain region can be manufactured.

The offset insulating film plays an important role in securing a dielectric strength between the gate electrode and the upper wiring, and is formed in a common pattern with the gate electrode. A gate electrode provided with an offset oxide film has a shadowing effect of preventing introduction of impurities into a transistor formation region by oblique ion implantation, and is particularly remarkable when a distance between gate electrodes is small. If the distance between the gate electrode patterns is the same, the lower the pattern height, the less the shadowing effect, so in the present invention, the gate electrode pattern is used as a mask at the stage where the offset oxide film is not formed, Oblique ion implantation is performed in the transistor region. As a result, the efficiency of introducing impurities into the transistor region can be increased. Therefore, even when an offset oxide film is formed on the gate electrode to form a self-aligned contact, impurities can reach the transistor region as prescribed during oblique ion implantation. If the method of the present invention is applied, the dielectric breakdown voltage between the gate electrode and the upper wiring is ensured in the same manner as before by the offset insulating film on the gate electrode, and a good pocket region is formed by oblique ion implantation, thereby shortening the short channel effect. The semiconductor device which suppresses the above can be manufactured. In addition, since the dependency of oblique ion implantation on density is low (pattern dependency), variations in transistor characteristics can be reduced.

[0012]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the film forming method and film forming conditions, etching method and etching conditions, annealing conditions, and the like described in the following examples are merely examples for understanding the method of the present invention.
It is not limited to this. Embodiment This embodiment is an example in which the method of the present invention is applied to the fabrication of an n-type MOSFET having a pocket region that suppresses a short channel effect and a self-aligned contact that conducts to a source / drain region. First, as shown in FIG.
A gate oxide film 14 having a thickness of about 10 nm was formed on the surface of the p-type Si substrate 12 by pyrogenic oxidation. Then, a polysilicon film 16 of about 10 nm containing impurities and a Wsi film 18 of about 100 nm in thickness are sequentially stacked on the gate oxide film 14 by, for example, LP-CVD to form tungsten (W) -polycide. The film 20 was formed. Then, the tungsten (W) -polycide film 20 having the laminated structure was subjected to resist patterning into a predetermined gate electrode pattern by anisotropic dry etching to form a gate electrode 22. In the transistor formation region of this embodiment, the width of the gate electrode 22 is about 0.35 μm, and the distance between the gate electrodes, which is the self-aligned contact formation region, is about 0.35 μm.
μm. As described above, the gate electrode 22 shown in FIG. 1A having a laminated structure of polysilicon / WSix is formed in the n-type MOSFET region on the Si substrate 12.

Next, as shown in FIG. 1B, oblique ion implantation was performed using the pattern of the gate electrode 22 as a mask to form a p-type impurity pocket region. The ion implantation conditions at this time were as follows: the ion species was BF 2 + , the energy was 200 keV, the dose was 1.0 × 13 cm −2 , and the ion implantation angle was 45 degrees. Next, LDD of n-type impurity
Ion implantation was performed. The ion implantation conditions at this time are as follows : the ON species is As + , the energy is 25 keV, and the dose is 2.0
Xx 13 cm -2 and the ion implantation angle was 7 degrees. By the above ion implantation, a p + type pocket region 24 and an n type LDD impurity region 26 are formed in the Si substrate 12. According to the present invention, since the offset oxide film which causes an increase in the aspect ratio of the pattern is formed after the ion implantation, a sufficient impurity is introduced even immediately below the gate electrode, regardless of the thickness of the offset oxide film, so that the predetermined pocket region is formed. Can be formed. Therefore, the short channel effect can be sufficiently suppressed.

Next, as shown in FIG. 1C, an SiOx film 28 constituting an offset insulating film was formed on the entire surface of the substrate by a plasma CVD method. Then, the SiOx film 28
The resist was patterned by anisotropic dry etching to form an offset insulating film 28 on the gate electrode 22.

Next, as shown in FIG. 2D, an SiOx film 30 for covering the entire surface of the substrate conformally is formed by a CVD method and is etched back anisotropically.
An LDD sidewall 30 was formed on the sidewall surface of the pattern of the gate electrode 22. In this state, high-concentration ion implantation is performed to form an n + source / drain region 3 having an LDD structure.
2 was formed on the Si substrate 12. The ion conditions are such that the ion species is As + , the energy is 30 keV, and the dose is 3.0 ×.
It was 10 15 cm -2 . Then, at a temperature of 1050 ° C., 10
RTA (rapid thermal annealing) was performed for seconds to activate the ion-implanted impurities.

Next, as shown in FIG. 2E, a SiN etching stop film 34 having a thickness of about 20 nm for conformally covering the entire surface of the substrate was formed by a plasma CVD method. Subsequently, an interlayer insulating film 36 having a thickness of about 500 nm was formed on the entire surface of the substrate, and the substrate was flattened. In this embodiment, O 3
A BPSG film was formed by doping boron and phosphorus into a SiOx film by -TEOS normal pressure CVD method, and then reflowed to form an interlayer insulating film 36. Then
A resist film was formed, and a resist pattern 40 having a contact opening 38 was formed by photolithography.

Next, the interlayer insulating film 36 exposed in the opening 38 is removed by dry etching with a mixed gas of CHF 3 / CH 2 F 2 , and as shown in FIG. A contact fall 42 was formed in the contact formation region up to the SiN etching stop film 34. Note that this etching was performed under the condition that a high selectivity with respect to SiN can be secured by utilizing the deposition of a fluorocarbon-based polymer.

[0018] Subsequently, as shown in FIG. 3 (g), a SiN etch stop layer 34 exposed on the substrate CHF 3 / O
Etched with 2 mixed gas, the source / drain regions 3
A contact hole 44 exposing 2 was formed. Then, the upper layer wiring 46 was formed so as to fill the contact hole 44 back. The upper layer wiring 46 is formed, for example, by a Ti adhesion tank / W embedded in the contact hole 44.
A plug 48 having a layered structure of a film and a TiN barrier metal / Al-Si /
And an upper wiring pattern 50 made of a TiN antireflection film.

In this embodiment, even if the SiN film 34 is used as an etching stop film to form a self-aligned contact and the offset oxide film 28 is formed on the conductive layer 22 of the gate electrode, the offset oxide film 28 Before forming the gate, oblique ion implantation is performed.
The pocket region that can suppress the channel effect can be formed as predetermined.

[0020]

According to the structure of the method of the present invention, even if an etching stop film and an offset oxide film are provided to form a self-aligned contact in a transistor region on a semiconductor substrate, the gate electrode is formed on the gate electrode. By performing pocket ion implantation before the offset insulating film is formed, ion implantation with low dependency on density (pattern dependency) can be performed, and a pocket region capable of suppressing a short channel effect can be formed as predetermined. Can be. By applying the method of the present invention, the transistor performance is uniform,
A semiconductor device in which the short channel effect is suppressed and which has a self-aligned contact can be manufactured. Therefore, the method of the present invention can reduce the size and integration of a semiconductor device,
This greatly contributes to higher performance.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views of a substrate showing a layer structure in each step when a method of manufacturing a semiconductor device according to the present invention is performed.

FIGS. 2 (d) and (e) respectively show FIG.
FIG. 4C is a cross-sectional view of the substrate, showing a layer structure in each step when the method of manufacturing a semiconductor device according to the present invention is performed, following FIG.

FIGS. 3 (f) and (g) are FIGS.
FIG. 5E is a cross-sectional view of the substrate, showing a layer structure in each step when the method of manufacturing a semiconductor device according to the present invention is performed, following FIG.

FIGS. 4 (a) to 4 (c) are cross-sectional views of a substrate showing a layer structure in each step when a conventional oblique ion implantation method is performed.

[Explanation of symbols]

12 ... p-type Si substrate, 14 ... gate oxide film, 16 ...
... Polysilicon film, 18 ... Wsi film, 20 ... Tungsten (W) -polycide film, 22 ... Gate electrode, 2
4 ... p + type pocket region, 26 ... n - type LDD region, 28 ... offset insulating film, 30 ... LDD sidewall, 32 ... source / drain region having LDD structure, 34 ... SiN etching Stop film, 36 ... Interlayer insulating film, 38 ... Contact opening, 40 ... Resist pattern, 42 ... Contact fall, 44 ...
Contact holes, 46: upper wiring, 48: plug, 50: upper wiring pattern.

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 19, 1997

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

[Fig. 1]

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

[Fig. 4]

Claims (5)

[Claims]
1. A method of manufacturing a semiconductor device having a self-aligned contact with impurity regions and source / drain regions formed by oblique ion implantation, comprising: forming a gate electrode pattern on a transistor formation region of a semiconductor substrate; A first step, a second step of obliquely implanting ions into the semiconductor substrate from a direction inclined at a predetermined angle with respect to a normal direction of the semiconductor substrate using the gate electrode pattern as a mask, and an insulating layer forming an offset oxide film of the gate electrode A method of manufacturing a semiconductor device, comprising: a third step of forming a film over the entire surface of a semiconductor substrate; and a fourth step of forming an offset oxide film on a gate electrode pattern by patterning an insulating film.
2. The method according to claim 1, wherein, in the second step, a pocket region is formed in the semiconductor substrate by oblique ion implantation of an impurity having the same conductivity type as that of the semiconductor substrate.
3. In a second step, an impurity of the same conductivity type as that of the semiconductor substrate is obliquely ion-implanted to form a pocket region in the semiconductor substrate, and an impurity of a conductivity type opposite to that of the semiconductor substrate is ion-implanted to form an LDD. 2. The method according to claim 1, wherein an impurity region is formed.
4. The method according to claim 3, further comprising, after the fourth step, a fifth step of forming an LDD sidewall on the side wall surface of the gate electrode pattern.
5. The method according to claim 4, further comprising, after the fifth step, a step of forming a silicon nitride film as an etching stopper film on the substrate.
JP33530096A 1996-12-16 1996-12-16 Manufacturing method of semiconductor device Pending JPH10173183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33530096A JPH10173183A (en) 1996-12-16 1996-12-16 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33530096A JPH10173183A (en) 1996-12-16 1996-12-16 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH10173183A true JPH10173183A (en) 1998-06-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH10173183A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009218580A (en) * 2008-03-06 2009-09-24 Toshiba Corp Bidirectional halo injection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009218580A (en) * 2008-03-06 2009-09-24 Toshiba Corp Bidirectional halo injection

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