JPH10163357A - Method for assembling electronic parts - Google Patents
Method for assembling electronic partsInfo
- Publication number
- JPH10163357A JPH10163357A JP31735596A JP31735596A JPH10163357A JP H10163357 A JPH10163357 A JP H10163357A JP 31735596 A JP31735596 A JP 31735596A JP 31735596 A JP31735596 A JP 31735596A JP H10163357 A JPH10163357 A JP H10163357A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- pad
- film
- copper
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子部品の組立て
方法に関するものである。The present invention relates to a method for assembling an electronic component.
【０００２】[0002]
【従来の技術】電子部品の組立て構造として、基板の表
面のパッド上に、基板とチップを接続するためのワイヤ
をボンディングするとともに、他のパッド上に突出電極
であるバンプを形成するものが知られている。このよう
な電子部品としては、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａ
ｒｒａｙ）パッケージがある。ワイヤとしては金ワイヤ
が多用されており、またバンプとしては半田バンプが多
用されている。2. Description of the Related Art As an assembly structure of an electronic component, there is known a structure in which a wire for connecting a substrate and a chip is bonded on a pad on a surface of a substrate, and a bump which is a protruding electrode is formed on another pad. Have been. Such electronic components include BGA (Ball Grid A).
(ray) package. Gold wires are frequently used as the wires, and solder bumps are frequently used as the bumps.
【０００３】図５は、従来の基板の断面図である。図
中、１はガラエポ基板などの基板であり、その上側と下
側の表面には回路パターンの銅パッド２，３が形成され
ている。また銅パッド２，３上にはニッケル膜４，５が
形成されており、ニッケル膜４，５上には金膜６，７が
形成されている。そして上面側の銅パッド２と下面側の
銅パッド３は内部配線８で接続されている。ニッケル膜
４，５や金膜６，７は、一般に、メッキ法により形成さ
れる。FIG. 5 is a sectional view of a conventional substrate. In the figure, reference numeral 1 denotes a substrate such as a glass epoxy substrate, and copper pads 2 and 3 of a circuit pattern are formed on the upper and lower surfaces thereof. Further, nickel films 4 and 5 are formed on the copper pads 2 and 3, and gold films 6 and 7 are formed on the nickel films 4 and 5. The copper pad 2 on the upper surface and the copper pad 3 on the lower surface are connected by an internal wiring 8. The nickel films 4, 5 and the gold films 6, 7 are generally formed by a plating method.
【０００４】ニッケル膜４，５は、銅パッド２，３の素
材である銅が金膜６，７中へ拡散して表面に到達し、空
気に触れて銅の酸化膜を生じるのを防止するためのバリ
ヤとして形成されている。なお金膜６，７の表面に銅の
酸化膜が生じれば、金ワイヤのボンディングが不良にな
る。また金膜６，７は、金ワイヤやハンダバンプのボン
ディング性を向上させるために形成されている。なお、
ニッケル膜４，５は、特にバンプの素材であるハンダの
接着性が悪いものである。The nickel films 4 and 5 prevent the copper, which is the material of the copper pads 2 and 3, from diffusing into the gold films 6 and 7 and reaching the surface and contacting air to form a copper oxide film. Is formed as a barrier. If a copper oxide film is formed on the surfaces of the gold films 6 and 7, the bonding of the gold wire becomes defective. The gold films 6 and 7 are formed in order to improve the bonding property of gold wires and solder bumps. In addition,
The nickel films 4 and 5 have poor adhesion to solder, which is a material for the bumps.
【０００５】図６は、図５に示す従来の基板を用いた電
子部品の組立構造図である。一方の銅パッド２の金膜６
上に、基板１に搭載されたチップ（図外）と電気的に接
続するための金ワイヤ９をボンディングし、他方の銅パ
ッド３の金膜７上にハンダバンプ１０を形成して電子部
品を組立てる。FIG. 6 is an assembly structure diagram of an electronic component using the conventional substrate shown in FIG. Gold film 6 on one copper pad 2
A gold wire 9 for electrically connecting to a chip (not shown) mounted on the substrate 1 is bonded thereon, and a solder bump 10 is formed on the gold film 7 of the other copper pad 3 to assemble an electronic component. .
【０００６】[0006]
【発明が解決しようとする課題】しかしながら上記従来
方法は、基板１のパッド構造は、銅パッド２，３、ニッ
ケル膜４，５、金膜６，７の三層構造であったため、単
に製造工程が面倒であるだけでなく、次のような重大な
問題点があった。However, according to the above-mentioned conventional method, the pad structure of the substrate 1 is a three-layer structure of copper pads 2, 3, nickel films 4, 5, and gold films 6, 7, so that the manufacturing process is simply performed. Not only is it troublesome, but also has the following serious problems.
【０００７】すなわち、図６に示すようにハンダバンプ
１０を金膜７上に形成すると、ハンダバンプ１０の形成
時の高温加熱のために金膜７の素材である金はハンダバ
ンプ１０の内部に溶け込んで金膜７は消滅し、その結
果、図６に示すようにハンダバンプ１０はニッケル膜５
に直接ボンディングされることとなる。ところが、上述
したようにハンダバンプ１０とニッケル膜５の接着性は
銅とハンダの密着性よりも悪いため、ハンダバンプ１０
はニッケル膜５から剥げ落ちしやすいという問題点があ
った。またこのような問題点を軽減するために、きわめ
て高価な金膜７をかなり厚く形成する必要があり、この
ため相当のコストアップとなるものであった。なお、従
来の金膜６，７の厚さは、１ミクロン程度である。That is, when the solder bumps 10 are formed on the gold film 7 as shown in FIG. 6, gold as a material of the gold film 7 melts into the solder bumps 10 due to high-temperature heating when the solder bumps 10 are formed. The film 7 has disappeared, and as a result, as shown in FIG.
Will be directly bonded. However, as described above, the adhesion between the solder bump 10 and the nickel film 5 is worse than the adhesion between the copper and the solder.
Has a problem that it is easily peeled off from the nickel film 5. Further, in order to reduce such a problem, it is necessary to form the extremely expensive gold film 7 in a considerably large thickness, which considerably increases the cost. The thickness of the conventional gold films 6 and 7 is about 1 micron.
【０００８】ところで、ハンダバンプが形成されるパッ
ドのみを形成し、金ワイヤをボンディングしないタイプ
の基板には、上述した問題は生じない。何故ならば、ハ
ンダバンプのみを形成する場合は、銅パッド上にニッケ
ル膜を形成しないで金膜を直接形成した二層構造でもよ
いからである。すなわちこの場合、上述したように銅パ
ッドの素材である銅は金膜中に拡散し、外部の空気に触
れることにより、ハンダバンプの接着性を阻害する酸化
膜が生じるが、ハンダバンプを形成する際にはフラック
スが用いられるので、このフラックスにより酸化膜は還
元除去されてしまうからである。このように、上記問題
点は、基板の銅パッド上に金ワイヤをボンディングし、
他の銅パッド上にハンダバンプを形成して電子部品を組
立てる場合に特有の問題である。The above-mentioned problem does not occur in a substrate of a type in which only pads on which solder bumps are formed and no gold wires are bonded. This is because, when only solder bumps are formed, a two-layer structure in which a gold film is directly formed without forming a nickel film on a copper pad may be used. That is, in this case, as described above, copper, which is a material of the copper pad, diffuses into the gold film, and when exposed to outside air, an oxide film that inhibits the adhesiveness of the solder bump is generated, but when forming the solder bump, Is because a flux is used, and the oxide film is reduced and removed by the flux. Thus, the above problem is caused by bonding a gold wire on a copper pad of a substrate,
This is a particular problem when assembling electronic components by forming solder bumps on other copper pads.
【０００９】したがって本発明は、基板の銅パッド上
に、金ワイヤを良好にボンディングできるとともに、ハ
ンダバンプを良好に形成できる電子部品の組立て方法を
提供することを目的とする。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method of assembling an electronic component capable of favorably bonding a gold wire on a copper pad of a substrate and forming a good solder bump.
【００１０】[0010]
【課題を解決するための手段】本発明は、基板の表面に
金ワイヤをボンディングするための銅パッドおよびハン
ダバンプを形成するための銅パッドを形成し、かつこれ
らの銅パッド上に金膜を形成し、銅パッドの素材である
銅が金膜の表面に拡散して空気に触れることにより生じ
た酸化膜をプラズマエッチングにより除去した後、この
銅パッドの金膜上に金ワイヤをボンディングし、ハンダ
バンプが形成される銅パッドにハンダバンプを形成す
る。According to the present invention, a copper pad for bonding a gold wire and a copper pad for forming a solder bump are formed on the surface of a substrate, and a gold film is formed on these copper pads. After the copper film, which is the material of the copper pad, diffuses to the surface of the gold film and removes the oxide film generated by contact with air by plasma etching, a gold wire is bonded on the gold film of the copper pad to form a solder bump. A solder bump is formed on a copper pad on which is formed.
【００１１】また、前記プラズマエッチングによる前記
酸化膜の除去を金ワイヤがボンディングされる銅パッド
についてのみ行い、ハンダバンプを形成するための銅パ
ッドについては行わない。The removal of the oxide film by the plasma etching is performed only on the copper pad to which the gold wire is bonded, but not on the copper pad for forming the solder bump.
【００１２】[0012]
【発明の実施の形態】上記構成の本発明によれば、銅パ
ッド上のニッケル膜を不要にし、かつ金膜を従来方法よ
りもきわめて薄くして、金ワイヤをボンディングすると
ともに、他の銅パッドにハンダバンプを形成することが
できる。According to the present invention having the above structure, the nickel film on the copper pad is unnecessary, the gold film is made extremely thinner than the conventional method, the gold wire is bonded, and other copper pads are formed. Solder bumps can be formed on the substrate.
【００１３】以下、本発明の一実施の形態を図面を参照
して説明する。図１は、本発明の一実施の形態の電子部
品の組立構造図、図２は同基板の断面図、図３は同基板
のプラズマエッチング中の断面図、図４は同電子部品の
組立構造図である。An embodiment of the present invention will be described below with reference to the drawings. 1 is an assembly structure diagram of an electronic component according to an embodiment of the present invention, FIG. 2 is a sectional view of the same substrate, FIG. 3 is a sectional view of the same substrate during plasma etching, and FIG. 4 is an assembly structure of the same electronic component. FIG.
【００１４】まず、電子部品Ａの構造について説明す
る。電子部品ＡはＢＧＡタイプのパッケージである。図
１において、１１は基板であり、基板１１の上面にはチ
ップ１２が搭載されている。チップ１２の表面のパッド
１３と基板１１の上面の第１のパッド１４は金ワイヤ１
５で接続されている。１５’は、パッド１３にボンディ
ングされる金ワイヤ１５の先端の金ボールである。First, the structure of the electronic component A will be described. The electronic component A is a BGA type package. In FIG. 1, reference numeral 11 denotes a substrate, on which a chip 12 is mounted. The pad 13 on the surface of the chip 12 and the first pad 14 on the upper surface of the substrate 11
5 is connected. Reference numeral 15 ′ denotes a gold ball at the tip of the gold wire 15 to be bonded to the pad 13.
【００１５】基板１１の下面には第２のパッド１６が形
成されている。第２のパッド１６上にハンダバンプ１７
が形成されている。第１のパッド１４と第２のパッド１
６は内部配線１８で接続されている。基板１１の上面に
はチップ１２やワイヤ１５を封止するための樹脂モール
ド１９が形成されている。３１はチップ１２をボンディ
ングするためのボンドである。On the lower surface of the substrate 11, a second pad 16 is formed. Solder bump 17 on second pad 16
Are formed. First pad 14 and second pad 1
6 are connected by an internal wiring 18. A resin mold 19 for sealing the chip 12 and the wires 15 is formed on the upper surface of the substrate 11. Reference numeral 31 denotes a bond for bonding the chip 12.
【００１６】次に、図２および図３を参照して、図１に
示す電子部品の組立て方法を説明する。図２は、基板１
１の断面を示している。第１のパッド１４は、銅パッド
２１上に金膜２２を薄くコーティングして形成されてい
る。また第２のパッド１６も、銅パッド２３に金膜２４
を薄くコーティングして形成されている。金膜２２，２
４は、同一工程メッキ法により同時に形成されている。
第１のパッド１４の銅パッド２１上の金膜２２は、金ワ
イヤ１５のボンディング力を確保するために形成されて
いる。次に基板１１の上面にボンド３１を介してチップ
１２を搭載し、基板１１を加熱してボンド３１を硬化さ
せてチップ１２を基板１１上にボンディングする。Next, a method of assembling the electronic component shown in FIG. 1 will be described with reference to FIGS. FIG.
1 shows a cross section. The first pad 14 is formed by thinly coating a gold film 22 on a copper pad 21. The second pad 16 also has a gold film 24 on the copper pad 23.
Is formed by thin coating. Gold film 22, 2
No. 4 is formed simultaneously by the same process plating method.
The gold film 22 on the copper pad 21 of the first pad 14 is formed to secure the bonding force of the gold wire 15. Next, the chip 12 is mounted on the upper surface of the substrate 11 via the bond 31 and the substrate 11 is heated to cure the bond 31 and bond the chip 12 to the substrate 11.
【００１７】図２に示す銅パッド２１，２３の素材であ
る銅は、ボンド３１を硬化させるときなどの加熱によっ
て徐々に金膜２２，２４中に拡散し、金膜２２，２４の
表面にあらわれて、図３に示すように酸化膜２５，２６
が生じる。上述したように、第１のパッド１４側の酸化
膜２５は金ワイヤ１５のボンディング性を阻害する。一
方、第２のパッド１６側の酸化膜２６は、後工程で塗布
されるフラックスで還元されて除去されるので、ハンダ
バンプ１７の接着性に実質的に悪影響を与えない。Copper, which is a material of the copper pads 21 and 23 shown in FIG. 2, gradually diffuses into the gold films 22 and 24 by heating such as when the bond 31 is cured, and appears on the surfaces of the gold films 22 and 24. Then, as shown in FIG.
Occurs. As described above, the oxide film 25 on the first pad 14 side inhibits the bonding property of the gold wire 15. On the other hand, the oxide film 26 on the second pad 16 side is reduced and removed by the flux applied in a later step, and thus does not substantially affect the adhesiveness of the solder bump 17.
【００１８】そこで、図３に示すように、第１のパッド
１４側の酸化膜２５は、プラズマエッチングを行って除
去する。破線矢印は、酸化膜２５に衝突せられるプラズ
マ分子やプラズマイオンを示している。プラズマエッチ
ングは、例えば特開平４−３１１０４４号公報に示され
るようなプラズマクリーニング装置を用いて行われる。
なお第２のパッド１６側の酸化膜２６は、上述した理由
により除去する必要はないが、この酸化膜２６も酸化膜
２５と同様にプラズマエッチングによって除去してもよ
い。Therefore, as shown in FIG. 3, the oxide film 25 on the first pad 14 side is removed by performing plasma etching. Dashed arrows indicate plasma molecules and plasma ions that collide with the oxide film 25. The plasma etching is performed using a plasma cleaning apparatus as disclosed in, for example, Japanese Patent Application Laid-Open No. 4-311044.
The oxide film 26 on the second pad 16 side does not need to be removed for the above-described reason. However, this oxide film 26 may be removed by plasma etching similarly to the oxide film 25.
【００１９】このようにして第１のパッド１４側の酸化
膜２５を除去したならば、図４に示すようにワイヤボン
ディングにより金ワイヤ１５を金膜２２上にボンディン
グする。その後、チップ１２、ワイヤ１５、第１のパッ
ド１４を覆う樹脂モールド１９を形成する。次にパッド
１６側の金膜２６上にフラックスを介してハンダボール
を搭載し、このハンダボールをリフローして溶融・固化
させてハンダバンプ１７を形成する。なおこの金膜２４
は、図４に示すようにハンダバンプ１７の形成時にハン
ダバンプ１７中に拡散して消滅する。またハンダバンプ
１７の形成時には、フラックスが用いられるので、酸化
膜２６はフラックスに還元除去されて消滅する。After the oxide film 25 on the first pad 14 side is removed in this manner, the gold wire 15 is bonded onto the gold film 22 by wire bonding as shown in FIG. After that, a resin mold 19 that covers the chip 12, the wires 15, and the first pads 14 is formed. Next, a solder ball is mounted on the gold film 26 on the pad 16 side via a flux, and the solder ball is reflowed and melted and solidified to form a solder bump 17. The gold film 24
Are diffused into the solder bumps 17 and disappear when the solder bumps 17 are formed, as shown in FIG. Since flux is used when the solder bump 17 is formed, the oxide film 26 is reduced and removed by the flux and disappears.
【００２０】実験結果によれば、金膜２２，２４の厚さ
を０．０３〜０．０５ミクロン程度に薄くしても、金ワ
イヤ１５やハンダバンプ１７の十分なボンディング力を
得ることができた。因みに、図５および図６に示す従来
例では、上述したように金膜６，７の厚さは１ミクロン
程度であり、本方法によれば、高価の金の使用量を大巾
に削減できる。なお上記実施の形態では、金ワイヤ１５
をボンディングする第１のパッド１４とハンダバンプ１
７を形成する第２のパッド１６は、基板１１の上面と下
面に形成されているが、第１のパッド１４と第２のパッ
ド１６は基板１１の同じ上面または下面に形成してもよ
いものである。According to the experimental results, a sufficient bonding force of the gold wire 15 and the solder bump 17 could be obtained even if the thickness of the gold films 22 and 24 was reduced to about 0.03 to 0.05 μm. . Incidentally, in the conventional example shown in FIGS. 5 and 6, the thickness of the gold films 6 and 7 is about 1 micron as described above, and according to this method, the amount of expensive gold used can be greatly reduced. . In the above embodiment, the gold wire 15
Pad 14 and solder bump 1 for bonding
7 are formed on the upper surface and the lower surface of the substrate 11, but the first pad 14 and the second pad 16 may be formed on the same upper surface or the lower surface of the substrate 11. It is.
【００２１】[0021]
【発明の効果】本発明によれば、銅パッド上のニッケル
膜を不要にし、かつ金膜を従来方法よりもきわめて薄く
して、金ワイヤの先端部の金ボールをボンディングする
とともに、ハンダバンプを形成することができる。According to the present invention, the nickel film on the copper pad is made unnecessary, the gold film is made extremely thinner than the conventional method, the gold ball at the tip of the gold wire is bonded, and the solder bump is formed. can do.
【図１】本発明の一実施の形態の電子部品の組立構造図FIG. 1 is an assembly structure diagram of an electronic component according to an embodiment of the present invention.
【図２】本発明の一実施の形態の基板の断面図FIG. 2 is a sectional view of a substrate according to an embodiment of the present invention.
【図３】本発明の一実施の形態の基板のプラズマエッチ
ング中の断面図FIG. 3 is a cross-sectional view of the substrate according to the embodiment of the present invention during plasma etching.
【図４】本発明の一実施の形態の電子部品の組立構造図FIG. 4 is an assembly structure diagram of an electronic component according to an embodiment of the present invention.
【図５】従来の基板の断面図FIG. 5 is a sectional view of a conventional substrate.
【図６】従来の電子部品の組立構造図FIG. 6 is an assembly structure diagram of a conventional electronic component.
１１ 基板 １２ チップ １４ 第１のパッド １５ ワイヤ １６ 第２のパッド １７ ハンダバンプ ２１，２３ 銅パッド ２２，２４ 金膜 ２５，２６ 酸化膜 Reference Signs List 11 substrate 12 chip 14 first pad 15 wire 16 second pad 17 solder bump 21, 23 copper pad 22, 24 gold film 25, 26 oxide film
Claims (2)
ための銅パッドおよびハンダバンプを形成するための銅
パッドを形成し、かつこれらの銅パッド上に金膜を形成
し、銅パッドの素材である銅が金膜の表面に拡散して空
気に触れることにより生じた酸化膜をプラズマエッチン
グにより除去した後、この銅パッドの金膜上に金ワイヤ
をボンディングし、ハンダバンプが形成される銅パッド
にハンダバンプを形成することを特徴とする電子部品の
組立て方法。A copper pad for bonding a gold wire and a copper pad for forming a solder bump on a surface of a substrate, and a gold film is formed on the copper pad to form a copper pad material. After the oxide film generated by the copper diffusing on the surface of the gold film and coming into contact with air is removed by plasma etching, a gold wire is bonded on the gold film of the copper pad, and the solder bump is formed on the copper pad where the solder bump is formed. Forming an electronic component.
の除去を金ワイヤがボンディングされる銅パッドについ
てのみ行い、ハンダバンプを形成するための銅パッドに
ついては行わないことを特徴とする請求項１記載の電子
部品の組立て方法。2. The electronic device according to claim 1, wherein the removal of the oxide film by the plasma etching is performed only on a copper pad to which a gold wire is bonded, but not on a copper pad for forming a solder bump. How to assemble parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31735596A JP3277830B2 (en) | 1996-11-28 | 1996-11-28 | How to assemble electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31735596A JP3277830B2 (en) | 1996-11-28 | 1996-11-28 | How to assemble electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10163357A true JPH10163357A (en) | 1998-06-19 |
| JP3277830B2 JP3277830B2 (en) | 2002-04-22 |
Family
ID=18087315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31735596A Expired - Fee Related JP3277830B2 (en) | 1996-11-28 | 1996-11-28 | How to assemble electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3277830B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1432293A4 (en) * | 2001-09-28 | 2005-12-07 | Ibiden Co Ltd | Printed wiring board and production method for printed wiring board |
-
1996
- 1996-11-28 JP JP31735596A patent/JP3277830B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1432293A4 (en) * | 2001-09-28 | 2005-12-07 | Ibiden Co Ltd | Printed wiring board and production method for printed wiring board |
| US7129158B2 (en) | 2001-09-28 | 2006-10-31 | Ibiden Co., Ltd. | Printed wiring board and production method for printed wiring board |
| US7449781B2 (en) | 2001-09-28 | 2008-11-11 | Ibiden Co., Ltd. | Printed wiring board |
| US8013256B2 (en) | 2001-09-28 | 2011-09-06 | Ibiden Co., Ltd. | Printed wiring board |
| US8878078B2 (en) | 2001-09-28 | 2014-11-04 | Ibiden Co., Ltd. | Printed wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3277830B2 (en) | 2002-04-22 |
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