JPH10150187A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce masking processes and other processes attendant on them in under by a method wherein a source electrode is patterned by the use of a photomask the diffusion of impurities is carried out for the formation of a channel and a source region using the source electrode as a mask, and a trench is formed using the source electrode as a mask. SOLUTION: A photoresist left on an electrode 13 is removed after a source electrode 13 is formed, and P<+> -type impurities are injected into the exposed surface of an epitaxial layer 11 using the electrode 13 as a mask for the formation of a channel impurity diffusion region 21A. Then, P-type impurities are injected to form a source impurity diffusion region 15A using a patterned oxide film 14 and the electrode 13 as masks. Then a silicon oxide film 16 is formed on all the surface, and the oxide film 16 is removed from the regions 21A and 15A to make the surface of the region 15A exposed. In succession, a trench is cut in the regions 21A and 15A respectively using the oxide film 16 formed 16 formed on the electrode 13 as a mask to isolate the regions 21A and 15A form each other, and a channel region and a source region area formed ion the opposed side faces. Therefore, masking process are lessened in number.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for manufacturing a vertical power semiconductor device of a trench type.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described below with reference to FIG. FIG. 8 is a cross-sectional view showing the structure of a power MOSFET having a so-called trench structure. In this power MOSFET, as shown in FIG. 8, an N- type common drain layer 1 is formed on the surface of an N + type semiconductor substrate 8 by an epitaxial growth method, and a P + type The channel layer 2 is formed by diffusing the impurities. A source region 5 is formed in a part of the surface layer of the channel layer 2 by diffusing N + -type impurities, and a groove (trench) is provided to penetrate the source region 5. A gate insulating film 3 is formed on a surface layer of the trench, and a polysilicon gate 4 is formed on the gate insulating film 3 so as to fill the trench.

An interlayer insulating film 6 is formed on the polysilicon gate 4 so as to cover the same. Source area 5
A contact hole is formed in the interlayer insulating film 6 in the region where the source region 5 is formed.
Are formed.

[0004]

In order to form a power MOSFET having such a structure, a conventional manufacturing method is used.
(1) a step of forming a guard ring, (2) a step of element isolation, (3) a step of forming a channel layer in an element region,
(4) a step of forming a body region, (5) an impurity diffusion step in forming a source region, (6) a step of forming a trench,
(7) a gate electrode forming step, (8) a step of forming a contact hole with a source region in an interlayer insulating film, and (9) a photomask essential for a photolithography step for patterning is required in each of the wiring layer patterning steps. Thus, a total of nine photomasks were required.

[0005] For this reason, the number of masking steps and steps accompanying the masking steps becomes very large, and the manufacturing steps become complicated, resulting in a problem that the manufacturing cost is increased. The present invention has been made in view of the above circumstances, and provides a method of manufacturing a power semiconductor device having a trench structure in which the number of masks is significantly reduced.

[0006]

In order to solve the above-mentioned problems, the present invention employs the following manufacturing method. That is, in the method for manufacturing a semiconductor device of the present invention, a step of forming a drain region layer serving as a common drain region on a surface layer of a semiconductor substrate of one conductivity type, and a step of forming a first conductive layer serving as a source electrode on the drain region layer Forming a body layer, forming a photoresist film via a first insulating film formed on the surface of the first conductor layer,
After exposing and developing the photoresist film into a predetermined pattern, removing the first conductor layer exposed by the resist film and forming a source electrode, the drain exposed using the source electrode as a mask A step of implanting a reverse conductivity type impurity into a region to be a channel region in the region layer; and a step of implanting the one conductivity type impurity into the exposed region implanted with the reverse conductivity type impurity using the source electrode as a mask. Implanting and diffusing, forming a second insulating film covering the side walls and the upper surface of the source electrode, and using the second insulating film as a mask in a region other than the source electrode formation region. Forming a groove reaching the drain region layer and forming a third insulating film on the surface of the groove; and a gate electrode filled in the groove and covered with the second insulating film. It is characterized by a step of forming a second conductive layer over the entire surface that.

Here, the impurity diffusion of the opposite conductivity type implanted into the region to be the channel region is performed in the same thermal diffusion step as the impurity diffusion of one conductivity type implanted into the region to be the source region. And As mentioned above,
By using a source electrode pattern as a mask, an impurity to be a channel and a source region is implanted, and a groove for forming a trench structure is formed, whereby a channel region and a source region can be formed with one mask. it can.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a vertical power semiconductor device having a trench structure according to an embodiment of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1, an N- type epitaxial layer serving as a drain region 11 is formed on a surface layer of an N + type semiconductor substrate 10 by an epitaxial growth method. C on the epitaxial layer 11
A polysilicon layer 12, which is a first conductor serving as a source electrode, is formed to a thickness of about 5000 ° by a VD method or the like. Then, a film thickness of about 500 is formed on the surface of the polysilicon layer 12.
A first oxide film 14 of about 0 ° is formed by a CVD method or the like.

Next, as shown in FIG. 2, a photoresist PR is applied on the oxide film 14 to a thickness of about 1 μm, and a photomask PM is used to cover a region other than a region where a source electrode is to be formed later. The photoresist PR is selectively exposed. After developing the photoresist PR and removing the exposed region, the oxide film 14 and the polysilicon layer 12 are sequentially etched and removed by using the photoresist PR remaining in a region where a source electrode is to be formed later as a mask. Is formed (see FIG. 3).

Next, as shown in FIG.
Is formed, the photoresist PR remaining on the source electrode 13 is removed, and using the source electrode 13 as a mask, a P + -type impurity serving as a channel impurity diffusion region is implanted into the exposed surface of the epitaxial layer 11. As a P + type impurity, for example, B (boron) is dosed at 5.times.10@13 c.
The injection is performed under the condition of about m-2. Such P + -type impurities may be diffused by thermal diffusion after implantation, but in the present embodiment, they are diffused in the same step as the later-described diffusion of the source region.

Next, as shown in FIG. 5, the re-patterned oxide film 14 and source electrode 13 are used as masks.
Impurity diffusion region 21A for channel implanted with P-type impurity
Is implanted into a region to be a source region. As an N-type impurity, for example, AS (arsenic) is implanted under the condition of a dose of 1.times.10@16 cm @ -2 and thermally diffused to form a channel impurity diffusion region 21A and a source impurity diffusion region 15A.

Next, as shown in FIG. 6, after forming a silicon oxide film 16 having a thickness of about 8000 ° to be a second oxide film on the entire surface by a CVD method or the like, the silicon oxide film 16 is sandwiched between the source electrodes 13 by dry etching. The silicon oxide film 16 on the regions 21A and 15A where the impurities serving as the channel and source regions are diffused is etched and removed to expose the surface of the impurity diffusion region 15A serving as the source region. Thus, the side wall and the upper surface of the source electrode 13 are covered and protected by the silicon oxide film 16 of the second oxide film.

Next, as shown in FIG.
Using the insulating film 16 formed on the mask 3 as a mask, trenches (grooves) 17 are formed in the impurity diffusion regions 21A and 15A serving as channel and source regions, and the regions 21A and 15A in which the impurities are diffused are separated. A P-type channel region 21 and an N-type source region 15 are formed on the side surfaces, respectively. The depth of the trench 17 is determined by the thickness of the epitaxial layer 11, and can be arbitrarily determined unless the trench 17 penetrates. In this embodiment, the trench 17 having a depth of about 3 μm is formed.

After the trench 17 is formed, its surface is thermally oxidized to form a gate insulating film 18 having a thickness of about 500.degree. Serving as a third oxide film. The value of 500 ° is, for example, a value in the case of a 30V power MOSFET, and it is needless to say that this film thickness is arbitrarily determined by the withstand voltage of the power MOSFET.
After the gate insulating film 18 is formed, a polysilicon layer is laminated on the entire surface by a CVD method or the like, and a gate electrode 19 filling the trench 17 and covering the entire surface of the insulating film 16 is formed.

Next, a wiring layer 20 made of aluminum having a thickness of about 1 μm is laminated on the surface by sputtering or the like, and a photoresist is coated on the wiring layer (not shown) to form a second photo-resist. The photoresist is patterned by a photolithography method using a mask, and the wiring layer 20 and the gate electrode 19 are etched and removed by using the patterned resist as a mask to perform patterning as shown in FIG. The power MOSFET is completed.

As described above, according to the present invention, after the source electrode 13 is formed using the photoresist PR patterned using one photomask PM as a mask, the channel region is formed using the source electrode as a mask. , A source region forming step, a trench 17 forming step, and the like.
Most steps can be performed in a self-aligned manner. Therefore, even if a photomask used for the patterning step of the wiring layer 20 is included, only two photomasks are required, so that a mask process is required as compared with a conventional manufacturing method using as many as nine photomasks. In addition, it is possible to drastically reduce the number of processes associated therewith, thereby enabling labor saving of the manufacturing process and greatly reducing the manufacturing cost.

In this embodiment, the steps relating to element isolation are not described at all. However, after manufacturing in the above steps, each element is cut out and separated by dicing. Not required at all. In the above-described embodiment, the NchMOSFET has been described. However, the present invention can be used for a vertical power semiconductor device, and a PchMOSFET and an IGBT can be used.
Needless to say, the present invention can also be applied to (insulated gate bipolar transistor).

In this embodiment, the source electrode 13 and the gate electrode 19 are formed of polysilicon. However, the present invention is not limited to this, and for example, polycide or metal may be used.

[0019]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, the source electrode patterned using one photomask is used as a mask, and the impurities to be the channel region and the source region are formed. Spread, and even,
A trench (groove) can be formed, and in the subsequent steps, a photomask is not required until a wiring layer patterning step, and most steps can be performed in a self-aligned manner.

As a result, only two photomasks are required even when including the step of patterning the wiring layer.
Compared to the conventional manufacturing method that used nine photomasks for manufacturing, the number of mask steps and associated steps can be greatly reduced, and the manufacturing process can be labor-saving and the manufacturing cost can be significantly reduced. Will be possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating a method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a structure of a conventional trench power MOSFET.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Onda 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Hiroaki Saito 2-chome Keihanhondori, Moriguchi-shi, Osaka No. 5-5 Sanyo Electric Co., Ltd. (72) Inventor Keita Odashima 2-5-5 Keihan Hondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (2)

[Claims] A step of forming a common drain region layer of the same conductivity type on a surface layer of a semiconductor substrate of one conductivity type; forming a first conductor layer serving as a source electrode on the drain region layer; Forming a photoresist film via a first insulating film formed on a surface of the first conductor layer, exposing and developing the photoresist film in a predetermined pattern, and exposing the first conductive film exposed by the resist film; Removing the body layer and forming a source electrode, injecting a reverse conductivity type impurity into a region serving as a channel region in the drain region layer exposed using the source electrode as a mask, Implanting and diffusing one conductivity-type impurity serving as a source region into the exposed region into which the impurity has been implanted, using the source electrode as a mask; and forming a second insulating film covering side walls and an upper surface of the source electrode. Forming a groove in a region other than the formation region of the source electrode using the second insulating film as a mask, and forming a third insulating film on the surface of the groove; Forming a second conductive layer that is to be a gate electrode to be filled and covered with the second insulating film over the entire surface. 2. The method according to claim 2, wherein the impurity diffusion of the opposite conductivity type implanted into the region to be the channel region is performed in the same thermal diffusion step as the impurity diffusion of one conductivity type implanted into the region to be the source region. The method for manufacturing a semiconductor device according to claim 1.