JPH10145242A - Viterbi decoding method and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the scale of a comparator circuit of a maximum likelihood deciding part and also to increase the speed of maximum likelihood decision for path metric normalization. SOLUTION: A Viterbi decoding device 1 is provided with a BMU(branch metric arithmetic circuit) 5, which calculates a branch metric based on a decoding symbol, a normalizing circuit 7 which subtracts a maximum likelihood path metric from a branch metric and normalizes it, an ACSU(addition comparative selecting unit) 9 which adds a normalized branch metric to a immediately preceding path metric, compares each other and selects a path metric based on comparison result, a level-converting circuit 19 which performs level conversion of the path metric, a deciding circuit 21 which calculates the minimum value from a path metric after level conversion, a maximum likelihood deciding part 11 which calculates maximum likelihood path information of the path metric and a path memory circuit 13, which stores selection information of the ACSU and also outputs a maximum likelihood decoding system in accordance with maximum likelihood information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding method and apparatus for decoding a convolutional code, and more particularly to a Viterbi decoding method and apparatus capable of reducing the circuit scale of a maximum likelihood determination unit in the apparatus. Things.

[0002]

2. Description of the Related Art Block codes and convolutional codes are known as error correction codes in digital transmission. Comparing the block code and the convolutional code, it is considered that the convolutional code has a higher error correction capability than the block code if the complexity of the decoding device is almost the same. For this reason, the use of convolutional codes is expanding from the conventional communication field to the consumer field.

As a decoding method of the convolutional code, a Viterbi decoding method (GD Forney, Jr., "The V
iterbi Algorithm "Proceedi
ngs of IEEE, Vol. 61, pp 268
-278, Mar. 1973). This Viterbi decoding method is an algorithm that efficiently implements maximum likelihood decoding (decoding into the most likely code).

Hereinafter, this Viterbi decoding method will be described. First, on the transmitting side, encoding is performed using a convolutional encoder as shown in FIG. The encoder in the example of FIG. 6 includes a 2-bit shift register and two exclusive OR circuits, and the internal state {a, b} of the encoder can take four states. Then, 2-bit coded output signals y (0) and y (1) are obtained per 1-bit input signal u (coding rate R = １ ／), and the change of one bit of the input is a continuous output 3 Affects bits (constraint length L = 3). The convolutional code encoded by such an encoder is transmitted to the receiving side through a binary symmetric channel. That is, it is assumed that a code error from 0 to 1 or 1 to 0 occurs in a communication path error, and an undecidable received code is not defined.

On the receiving side, a received code sequence containing an error is extracted, and decoding (error correction) is performed based on the trellis expression shown in FIG. Referring to FIG. 7, each bold line indicates each state {a, b} = decoding when decoding is advanced until time k = 4.
Surviving paths (decoding sequence candidates) V (0), V (1), V (2) selected and survived in {0,0}, {0,1}, {1,0}, and {1,1}, respectively. ) And V
This represents (3). The surviving path is selected based on the hamming distance difference between the received code sequence and the transmission code sequence (hereinafter, the hamming distance difference is simply referred to as the distance difference). A path metric corresponding to the distance difference when decoding is advanced to each time is indicated by a solid square in FIG. The dotted square is the path metric of the discarded path.

As is apparent from FIG. 7, surviving paths V (0),..., V when decoding is advanced until time: k = 4
The path metrics of (3) are 1, 1, 2, and 2, respectively. In general, the past sequence of each surviving path has a higher probability of being combined into one, so the memory length of the surviving path is truncated to an appropriate length (for example, 4 to 6 times the constraint length) and the oldest symbol is Output as decoded symbol.

Although the oldest bit of each surviving path may not match depending on the error pattern, it goes without saying that the one with the smallest path metric corresponds to the most probable decoded sequence.

In the implementation of the Viterbi decoding apparatus, the calculation of the path metric can be realized in units of a set of state transitions shown in FIG. The surviving path metrics selected at time (k-1) are denoted by -1k-1 and Γ'k-1, respectively, and the branch metrics corresponding to the distance difference from the current received code are λk,
λ'k. There are two surviving path candidates at the current time k in each state, and the path metric of each candidate is Γk−1, Γ′k−1, λk, λ′k (Γk−
1 + λk), (Γ'k-1 + λ'k), (Γk-1 + λ'k
), (Γ'k-1 + λk). In each state, a path corresponding to the smaller one of the path metrics is selected.

As described above, the calculation of the path metric includes addition (Add), comparison (Compare), and selection (Sel).
ect), such a path metric calculator is called an ACS unit (ACSU).

FIG. 9 is a block diagram showing an example of the configuration of the entire Viterbi decoder. ACSU (804a and 804 in FIG. 9)
b), the number of possible states is Ns = 2L-1 (L:
(Constraint length), each corresponds to two states, and is (Ns / 2). Therefore, in this conventional example, Ns / 2 = 2 because L = 3.

The three comparison / selection circuits 821a, 821b,
The maximum likelihood determining unit 805 configured with 821c determines the most probable surviving path (the maximum likelihood path)
The purpose is to detect the minimum path metric. As shown in FIG. 9, the comparison / selection circuits 821a and 821a
1b and 821c are configured in a tree shape to form a maximum likelihood determination unit 805
Requires (Ns-1) comparison / selection circuits.

The path memory update circuit 807 aims to update the paths left in each state. That is, each state {0,0} = (0), {0,1} = (1),
{0,1} = (2), {1,1} = (3), path selection signals β (0), β (1), β indicating the remaining paths selected
(2), β (3), V (0),.
The decoded symbol candidates σ (0),..., Σ (3) corresponding to the oldest symbol of (3) are output.

A Viterbi decoding selector 808 selects a decoded symbol corresponding to the maximum likelihood path from these decoded symbol candidates σ (0) to σ (3) and outputs the selected symbol as a Viterbi decoded symbol. For this selection, the identification signal Pm (m
= 0 or 1 or 2 or 3).

By the way, the values of the path metrics Γ (0),..., Γ (3) shown in FIG. In actual implementation of the apparatus, the size of the path metric registers 803a,..., 803d holding the path metric is finite, so that overflow occurs over time.

In order to prevent this overflow, normalization may be performed using the minimum path metric. That is, each path metric is subtracted by the minimum path metric Γmin, k−1 one unit time ago stored in the maximum likelihood path metric register 806 before being stored in the path metric register. This is obtained by subtracting the minimum path metric Γmin, k-1 from the branch metrics λ00, λ01, λ10, λ11 previously calculated by the branch metric unit (BMU) 801 by the normalization circuit 802 as shown in FIG. Same thing. By doing so, the path metrics Γ (0),..., Γ (3) left in each state fall within a certain range, and the path metric register 8
If the sizes of 03a and 803d are sufficiently large, the decoding performance is not affected.

In FIG. 7, the Hamming distance is used as the branch metric. However, in order to improve the correction capability, a soft decision of the received symbol is introduced, and the Euclidean distance or the square of the Euclidean distance is used as the branch metric. There is. In this case, if the branch metric is expressed by 3 bits, the register of each path metric needs 6 to 8 bits in order not to degrade the decoding performance.

As the convolutional code actually used, as the constraint length is larger, the correction capability is larger, and therefore, a code of about L = 7 is often used. Coding rate R = 1/2, constraint length L = 7
FIG. 10 shows an overall configuration diagram of the Viterbi decoding device in the case of (1).
Since the number of states of the convolutional encoder is Ns = 2 ^L−1 = 64, the number of comparison inputs of the maximum likelihood determination unit is also 64.

[0018]

However, when the Viterbi decoding device which has been conventionally developed has a constraint length of 7, a maximum likelihood path metric is selected by the maximum likelihood decision section in order to select a maximum likelihood path metric. Since it needs to go through the selection circuit,
There is a problem that the delay time increases and the circuit scale further increases due to the effect.

For example, in order to perform a high-speed operation with a processing capacity of about 30 Mbps, it is difficult to derive the maximum likelihood determination value with one clock, and several clocks are required. Therefore, the path metric that should be used for maximum likelihood value determination for addition, comparison, selection, and normalization in one clock is:
A delay in the maximum likelihood value determination causes a time lag until normalization, which requires extra computational accuracy in the path memory and a limiter in the normalization operation unit to prevent underflow. Various problems occur.

The present invention has been made in view of the above problems, and in particular, in realizing a Viterbi decoding device, shortens the maximum likelihood determination time for normalization, which is a critical path, and speeds up the Viterbi decoder. It is another object of the present invention to provide a Viterbi decoder whose circuit scale is reduced.

[0021]

In order to achieve the above object, the present invention has the following arrangement. That is, the invention according to claim 1 includes a branch metric calculation step of calculating a branch metric based on a demodulated symbol, an addition step of adding the branch metric and the immediately preceding path metric to obtain a path metric, and Comparing a path metric with each other and selecting a path metric based on the comparison result; a level converting step of level-converting the path metric; a determining step of obtaining a minimum value from the level-converted path metric; A Viterbi decoding method comprising: a normalization step of normalizing a path metric using a minimum value; and an output step of outputting a maximum likelihood signal sequence from a path memory storing the result of the comparison. .

According to a second aspect of the present invention, in the Viterbi decoding method according to the first aspect, the level conversion step includes:
The point is to limit the path metric value to a certain value or less by a limiter.

According to a third aspect of the present invention, in the Viterbi decoding method according to the first aspect, the level conversion step includes:
The gist of the present invention is to use the result of the magnitude comparison between the path metric value and the predetermined value.

According to a fourth aspect of the present invention, in the Viterbi decoding method according to the first aspect, the level conversion step comprises:
The gist is to use 0 detection of the path metric value.

According to a fifth aspect of the present invention, in the Viterbi decoding method according to the first aspect, the determining step logically ANDs signals obtained by converting the respective path metric values into binary.

According to a sixth aspect of the present invention, there is provided a branch metric operation circuit for calculating a branch metric based on a demodulated symbol, and an addition for adding the branch metric and the immediately preceding path metric to generate an updated path metric. A circuit, a comparison / selection circuit that compares the updated path metric with each other and selects a path metric based on the comparison result, a level conversion circuit that converts the level of the path metric, and a minimum value from the path metric after the level conversion. Determination circuit, a normalization circuit that normalizes a path metric using the minimum value, a path memory that stores the result of the comparison, and an output circuit that outputs a maximum likelihood signal sequence from the path memory. This is a Viterbi decoding device having a gist of the above.

According to a seventh aspect of the present invention, in the Viterbi decoding device according to the sixth aspect, the level conversion circuit comprises:
The gist is any one of a limiter, a comparator for comparing a converted value with a predetermined value, and a 0 detection circuit for detecting whether the converted value is 0 or a combination thereof.

According to an eighth aspect of the present invention, in the Viterbi decoding device according to the sixth aspect, the determination circuit is an AND circuit for performing an AND operation on signals obtained by converting the respective path metric values into binary values. Is the gist.

[Operation] In the present invention, attention is paid to the fact that the most correct one of the path metrics has a smaller value than the others, and the other ones have very large values. By compressing the number of bits and determining the minimum value for normalization from the path metric subjected to the level conversion, the maximum likelihood determination for path metric normalization is accelerated and the circuit size of the Viterbi decoding device is reduced. Can be.

[0030]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of a Viterbi decoding device according to the present invention. In the present embodiment, the constraint length L = 7, and the number of possible states of the encoder at each time is Ns = 2 ^L−1 =
64, which does not limit the invention.

In FIG. 1, a Viterbi decoding device 1 includes an input terminal 3 and a branch metric operation circuit (hereinafter referred to as BMU).
5), a normalization circuit 7, an addition / comparison / selection unit (hereinafter abbreviated as ACSU) 9, a maximum likelihood determination circuit 11,
A path memory circuit 13, an output terminal 15, a level conversion circuit 19 for level-converting the path metric, and a determination circuit 21 for selecting and outputting the minimum value from the path metric after the level conversion are configured. .

The BMU 5 calculates a branch metric based on the demodulated symbols input from the input terminal 3,
Output to the normalization circuit 7. The normalization circuit 7 subtracts the maximum likelihood path metric value Γmin selected by the determination circuit 21 described later from the branch metric and outputs the result to the ACSU 9.

The ACSU 9 corresponds to Ns = 64.
s / 2 = 32 subunits, ACSU # 1 to AC
It is composed of SU # 32. The sub-units ACSU # 1 to ACSU # 32 of the ACSU9 add a new path metric by adding the output of the normalization circuit 7 to the value of the path metric in the previous state held by two path metric registers (not shown), respectively. The path metrics of the two state transitions to the new state are compared with each other, the smaller path metric is selected from the two, and the path metric register is updated with the selected path metric value. At the same time, the selection flags β0 to β63, which are information of the selected transitions, are sent to the path memory circuit 13.

The path memory circuit 13 stores the selection flags β0 to β63 output from the ACSU 9 in time series, and stores the selection flags β0 to β63 in the memory circuit based on the maximum likelihood path information output from the maximum likelihood determination circuit 11. The content is selected and output to the output terminal 15 as the maximum likelihood decoding output.

The maximum likelihood determination circuit 11 obtains maximum likelihood path information, which is identification information of the path metric having the minimum value, from the path metric output from the ACSU 9, and outputs this to the path memory circuit 13.

The level conversion circuit 19 is located between the ACSU 9 and the judgment circuit 21 and generates a path metric in which the number of bits is reduced by converting the level of each path metric output from the ACSU 9 to the judgment circuit 21. Output.

The determination circuit 21 obtains the minimum value from the path metric after the number of bits has been reduced by the level conversion circuit 19, and determines the minimum value, the maximum likelihood path metric value Γmin.
Is output to the normalization circuit 7.

The level conversion circuit 19 and the judgment circuit 21
A characteristic component of the present invention, with a relatively simple circuit configuration, reducing the number of bits representing a path metric value,
As a result, the circuit scale for detecting the minimum path metric is reduced, and the delay period of the normalized feedback loop, which is a critical path, is significantly reduced.

FIG. 2A is a detailed circuit diagram showing an example of a conversion table circuit as the first embodiment of the level conversion circuit, and converts a 6-bit input PM5 to PM0 into a 3-bit output PML2 to PML0. FIG. 6 is a circuit diagram showing an example of the operation.
In the figure, reference numerals 101, 103 and 105 denote OR circuits, respectively, and reference numerals 107, 109, 111 and 11
Reference numeral 3 denotes an AND circuit.

The input of the OR circuit 101 is connected to four input signals PM5 to PM2, and PML2, which is the logical sum of these signals, is output and the AND circuits 107, 1
11 are connected to one input. The OR circuit 101 has an inverted output, and supplies a complementary (inverted) logic signal of the PML2 to one input of each of the AND circuits 109 and 113.

The other inputs of the AND circuits 107 and 111 are connected to PM5 and PM4, respectively.
09, 113 are respectively PM1, PM
Connected to 0. The outputs of the AND circuits 107 and 109 are input to the OR circuit 103, and the output of the OR circuit 103 is PML1. Similarly, the outputs of the AND circuits 111 and 113 are input to the OR circuit 105, and the output of the OR circuit 105 is PML0.

With the above circuit configuration, this conversion table circuit outputs PM1 and PM0 to PML1 and PML0 when the input PM is 3 or less, and respectively outputs PML1 and PML0 when the input PM is 4 or more. Level conversion is executed by outputting PM5 and PM4. FIG. 2B is an input / output conversion table of the conversion table circuit.

FIG. 3A is a detailed circuit diagram showing an example of a limiter circuit as a second embodiment of the level conversion circuit. In the figure, reference numerals 121, 123, 125, and 127 indicate OR circuits, respectively. This limiter circuit is a circuit for converting the signal amplitudes of the 6-bit inputs PM5 to PM0 into 3-bit outputs PML2 to PML0 in which the signal amplitudes are limited to "7". When there is an input of "" or more, the output is limited to "7".

The operation of the limiter circuit of FIG. 3A is as follows. First, when the input is "7" or less, the output of the OR circuit 121 is not energized, and the lower three bits PM2-0 of the 6-bit input are output as 3-bit outputs PML2-0. Becomes When the input path metric value is equal to or more than “8”, of the 6-bit input,
The logical sum circuit 121 for outputting the logical sum of the upper three bits PM5 to PM3 is activated, and as a result, the logical sum circuit 12
The outputs 3, 3, 127 are also energized, and the values of the outputs PML2 to PML0 after the amplitude limitation become "7".

FIG. 3B is a detailed circuit diagram showing an example of a limiter circuit as a third embodiment of the level conversion circuit. In the figure, reference numerals 131, 133, 135, and 137 indicate OR circuits, respectively. This limiter circuit sets the signal amplitude of the 5-bit inputs PM4 to PM0 to "1".
This is a circuit that converts the output to a 4-bit output PML3 to PML0 limited to 5 and outputs the input below “15” as it is, but limits the output to “15” when there is an input above “15”. Is what you do.

FIG. 4A is a detailed circuit diagram showing an example of a comparator for performing a magnitude comparison with a predetermined value as a fourth embodiment of the level conversion circuit. In the figure, reference numeral 141 denotes an OR circuit, and among the 6-bit inputs PM5 to PM0,
Three of PM5 to PM3 are input. Other PM
2 to PM0 are not connected. When the input PM value is “8” or more, the output PML is energized,
When the input PM is less than "7", the output PML is not energized. That is, the comparator has 6-bit inputs PM5 to PM
As a result of comparison between 0 and the comparison reference value "8", a comparator in which the output PML becomes "1" when the input is "8" or more and the output PML becomes "0" when the input is "7" or less Will work as

FIG. 4B is a detailed circuit diagram showing an example of a 0 detection circuit as a fifth embodiment of the level conversion circuit.
In the figure, reference numeral 19 denotes an OR circuit, for example,
Inputs PM5 to PM0 indicating a 6-bit path metric value
Are connected to the OR circuit 19. When the value of the input PM is “1” or more, the output PML is energized, and when the input PM is “0”, the output PML is not energized. That is, the output of the OR circuit 19 is
And 1 can be regarded as a comparator, or can be regarded as a 0 detector having a negative logic output.

When each of the level conversion circuits 19 in FIG. 1 is composed of 0 detectors as shown in FIG. 4B, the path metric after level conversion by each level converter is: Since it becomes “0” or “1”,
The determination circuit 21 that selects the minimum value from these path metrics is implemented by a logical product circuit that calculates the logical product of these converted path metrics.

In the actual Viterbi decoding, even if a 3-bit branch metric capacity is provided, the value of the branch metric in a state where there is an error that can be corrected is distributed at most about "1" or "2". It is also known that errors are less likely to continue.

Therefore, even if the number of bits used for normalization of the path metric is limited to one bit, if one normalization (or a small value such as 2) is subtracted by one normalization, an overflow of the path metric occurs. There is little possibility of doing this. If a large error occurs and the normalized value, that is, the minimum path metric value is 1 or more, the normalization value is subtracted by one by a plurality of normalizations, and the minimum path metric value becomes 0.
And can be normalized.

If there is a margin in the bit precision of the path metric, one normalization is not performed one by one, but when the minimum value of the path metric exceeds 8 or 16,
The normalization may be performed by subtracting 8 or 16. The level conversion circuit used at this time is preferably a comparison circuit as shown in FIG. 4A, and an AND circuit can be used as the determination circuit.

FIG. 5 is a characteristic graph of the bit error rate in Viterbi decoding. The bit error rate when the path metric is level-converted and the path metric is compressed to 3 bits, and the bit error rate when the path metric is 5 bits. This is a reference value.

As can be seen from the figure, when the path metric indicated by the thick solid line is level-converted to 3 bits (N
There is almost no difference in the bit error rate between the case of m = 3 and □ display) and the case of a 5-bit path metric to be compared (Rf32, black △ display), proving the effectiveness of the present invention.

Although the preferred embodiment has been described above, this does not limit the present invention. For example,
In the conversion table circuit of the first embodiment, an example in which the input / output characteristics are bent with the input value “4” as a boundary has been described. It can be.

Although the limit level is set to "7" in the second embodiment, another value may be set as the limit level. Furthermore, although the predetermined value to be compared by the comparator in the fifth embodiment is set to “8”, it is apparent that another value may be used.

[0056]

As described above, according to the present invention, A
By converting the level of the path metric sent from the CSU to the maximum likelihood determination unit and compressing the number of bits, the maximum likelihood path metric that is the minimum value is determined from the level converted path metric and used for normalization. Thus, the delay time for normalizing the path metric, which is a critical path, can be reduced, and the clock of the entire Viterbi decoding device can be sped up.

Further, according to the present invention, it is possible to reduce the circuit scale of the maximum likelihood determination unit, and it is not necessary to take measures against underflow in the normalization circuit, and it is possible to reduce the size of the entire circuit of the Viterbi decoding device. It has the effect of being able to.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a Viterbi decoding device according to the present invention.

FIG. 2 is a circuit configuration diagram showing details of a level conversion circuit used in the Viterbi decoding device according to the present invention.

FIG. 3 is a circuit diagram showing details of a limiter circuit used in the Viterbi decoding device according to the present invention.

FIG. 4 is a circuit diagram showing details of a comparison circuit (a) and a 0 detection circuit (b) used in the Viterbi decoding device according to the present invention.

FIG. 5 is a graph showing a bit error rate characteristic of the Viterbi decoding device according to the present invention.

FIG. 6 is a diagram illustrating a configuration of a convolutional encoder.

FIG. 7 is a trellis diagram illustrating the principle of Viterbi decoding.

FIG. 8 is a diagram for explaining a relationship between a set of state transitions and a path metric.

FIG. 9 is a block diagram illustrating a configuration of an entire conventional Viterbi decoding device.

FIG. 10 is a block diagram illustrating a configuration of an entire conventional Viterbi decoding device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Viterbi decoder, 3 ... Input terminal, 5 ... Branch metric calculation circuit (BMU), 7 ... Normalization circuit, 9 ... Addition / comparison / selection circuit (ACSU), 11 ... Maximum likelihood determination circuit, 13
... Path memory circuit, 15 output terminal, 19 level conversion circuit, 21 determination circuit.

Claims (8)

[Claims] A branch metric calculation step of calculating a branch metric based on a demodulated symbol; an addition step of adding the branch metric to the immediately preceding path metric to obtain a path metric; Comparing and selecting a path metric based on the comparison result; a level conversion step of level-converting the path metric; a determination step of obtaining a minimum value from the path metric after the level conversion; and A Viterbi decoding method, comprising: a normalization step of normalizing a path metric; and an output step of outputting a maximum likelihood signal sequence from a path memory storing the result of the comparison. 2. The Viterbi decoding method according to claim 1, wherein said level conversion step limits a path metric value to a certain value or less by a limiter. 3. The Viterbi decoding method according to claim 1, wherein said level conversion step uses a result of magnitude comparison between a path metric value and a predetermined value. 4. The Viterbi decoding method according to claim 1, wherein said level conversion step uses 0 detection of a path metric value. 5. The Viterbi decoding method according to claim 1, wherein in the determining step, signals obtained by binarizing the respective path metric values are logically ANDed with each other. 6. A branch metric calculation circuit for calculating a branch metric based on a demodulated symbol, an addition circuit for adding the branch metric and the immediately preceding path metric to generate an updated path metric, and A comparison / selection circuit that compares metrics with each other and selects a path metric based on the comparison result; a level conversion circuit that performs level conversion of the path metric; a determination circuit that obtains a minimum value from the path metric after the level conversion; A Viterbi decoder, comprising: a normalization circuit that normalizes a path metric using a value; a path memory that stores the result of the comparison; and an output circuit that outputs a maximum likelihood signal sequence from the path memory. apparatus. 7. The level conversion circuit may be a limiter, a comparator that compares a converted value with a predetermined value, and a 0 detection circuit that detects whether the converted value is 0 or a combination thereof. 7. The Viterbi decoding device according to claim 6, wherein 8. The Viterbi decoding device according to claim 6, wherein said determination circuit is an AND circuit for performing an AND operation on signals obtained by binarizing respective path metric values.