JPH1012779A - Semiconductor mounting structure - Google Patents
Semiconductor mounting structureInfo
- Publication number
- JPH1012779A JPH1012779A JP16214696A JP16214696A JPH1012779A JP H1012779 A JPH1012779 A JP H1012779A JP 16214696 A JP16214696 A JP 16214696A JP 16214696 A JP16214696 A JP 16214696A JP H1012779 A JPH1012779 A JP H1012779A
- Authority
- JP
- Japan
- Prior art keywords
- heat transfer
- semiconductor
- semiconductor element
- wiring board
- mounting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はフリップチップ方式
により半導体素子を配線基板に接合した半導体実装構造
に係り、特に半導体素子の発熱を効果的に放散させるこ
とが可能な半導体実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting structure in which a semiconductor element is bonded to a wiring board by a flip chip method, and more particularly to a semiconductor mounting structure capable of effectively dissipating heat generated by the semiconductor element.
【０００２】[0002]
【従来の技術】一般に、大規模集積回路（ＬＳＩ）など
の半導体素子は、プラスチックパッケージ，メタルパッ
ケージ，セラミックスパッケージに搭載され、パッケー
ジ配線基板本体に形成された配線と電気的な接合を施さ
れて使用されている。上記各種パッケージのうち、特に
セラミックスパッケージは、ＬＳＩを気密封止する際の
信頼性が高く、優れた耐湿性や放熱性を兼ね備えている
ため、コンピュータの演算部に用いるＣＭＯＳゲートア
レイやＥＣＬゲートアレイ等のパッケージングに広く使
用されている。2. Description of the Related Art Generally, a semiconductor device such as a large-scale integrated circuit (LSI) is mounted on a plastic package, a metal package, or a ceramic package, and is electrically connected to wiring formed on a package wiring substrate body. It is used. Among the various packages described above, a ceramic package, particularly a ceramic package, is highly reliable when hermetically sealing an LSI, and has both excellent moisture resistance and heat dissipation. Widely used for packaging and the like.
【０００３】上記の半導体素子とパッケージとしての配
線基板との電気的な接続方式としては、ワイヤボンディ
ング方式やフリップチップ方式が採用されている。ワイ
ヤボンディング方式は、半導体素子の表面側の電極と配
線基板の端子部やリードフレームとを金やアルミニウム
などの導電性ワイヤーで接続する方式である。[0003] As an electrical connection method between the semiconductor element and a wiring board as a package, a wire bonding method or a flip chip method is adopted. The wire bonding method is a method in which an electrode on the front side of a semiconductor element is connected to a terminal portion or a lead frame of a wiring board by a conductive wire such as gold or aluminum.
【０００４】一方、フリップチップ方式は、図７および
図８に示すように、半導体素子１の裏面の電極部に形成
した突起電極（半田バンプ）２を介してプリント基板な
どの配線基板３に直接接続する方式である。配線基板３
の表面および内部には配線層４が形成されており、この
配線層４の端部は配線基板３の下面側に接合された入出
力ピン５と電気的に接続されている。On the other hand, in the flip-chip method, as shown in FIGS. 7 and 8, a wiring board 3 such as a printed board is directly provided via a protruding electrode (solder bump) 2 formed on an electrode portion on the back surface of a semiconductor element 1. This is a connection method. Wiring board 3
A wiring layer 4 is formed on the surface and inside of the wiring board 3, and an end of the wiring layer 4 is electrically connected to input / output pins 5 joined to the lower surface of the wiring board 3.
【０００５】上記ワイヤーボンディング方式による半導
体実装構造によれば、半導体素子の下部全面がダイパッ
ドを介して配線基板表面に接合される構造であるため、
半導体素子において発生した熱が半導体素子の下部全面
を経由して配線基板（パッケージ本体）方向に伝達さ
れ、放熱性が良好であるという利点がある。しかしなが
ら、ワイヤーによって電気的な接続を確保しているため
に、配線長さが増大し、信号遅れが発生し易く、大型化
および高速化を指向する半導体素子の実装構造として
は、不十分であった。According to the semiconductor mounting structure by the wire bonding method, the entire lower surface of the semiconductor element is bonded to the surface of the wiring board via the die pad.
The heat generated in the semiconductor element is transmitted to the wiring board (package main body) through the entire lower surface of the semiconductor element, and has an advantage that heat dissipation is good. However, since electrical connection is ensured by wires, the length of wiring increases, signal delays are likely to occur, and the mounting structure of a semiconductor element that is directed to increase in size and speed is insufficient. Was.
【０００６】またワイヤーボンディング方式による実装
構造においては、ボンディング操作に必要な空間距離を
確保するために配線基板の単位面積当りに配設する入出
力ピン数を増加させることが困難であり、高集積化した
半導体素子を実装する構造としては技術上の限界となっ
ていた。In the mounting structure using the wire bonding method, it is difficult to increase the number of input / output pins arranged per unit area of the wiring board in order to secure a space required for the bonding operation. There has been a technical limit to the structure for mounting the semiconductor device.
【０００７】一方、フリップチップ方式の実装構造によ
れば、微少な突起電極（半田バンプ）を介して半導体素
子と配線基板とが直接接続されるために、配線経路長が
短縮され、高速処理を指向する半導体素子の実装構造と
して好適である。また突起電極はボンディングワイヤー
と比較して、その配設密度を大幅に高めることが可能で
あり、配線基板の単位面積当りに配設できる入出力ピン
数も飛躍的に増大化させることができ、半導体素子の高
集積化にも十分に対応可能な実装構造となり得る。On the other hand, according to the flip-chip type mounting structure, the semiconductor element and the wiring board are directly connected via fine projection electrodes (solder bumps), so that the wiring path length is shortened and high-speed processing is achieved. It is suitable as a mounting structure of a semiconductor element to be oriented. In addition, the arrangement density of the protruding electrodes can be greatly increased as compared with the bonding wires, and the number of input / output pins that can be arranged per unit area of the wiring board can be dramatically increased. A mounting structure that can sufficiently cope with high integration of semiconductor elements can be obtained.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上記フ
リップチップ方式による半導体実装構造によれば、伝熱
経路となる突起電極部分の面積が半導体素子の面積と比
較して極めて小さくなり、基板方向への伝熱面積が減少
するため、放熱性が悪化する問題点があった。このた
め、従来のフリップチップ方式による実装構造において
は、半導体素子とその半導体素子を封止するためのリッ
ド（蓋）との間に半田を充填したり、高熱伝導性を有す
る樹脂材料を充填したりすることによって、半導体素子
の電極側と反対方向に熱を放散させる機構を別途設ける
必要があった。However, according to the flip-chip type semiconductor mounting structure, the area of the protruding electrode portion serving as a heat transfer path is extremely small as compared with the area of the semiconductor element, and the area in the direction of the substrate is reduced. Since the heat transfer area is reduced, there is a problem that heat dissipation is deteriorated. For this reason, in a conventional flip-chip mounting structure, solder is filled between a semiconductor element and a lid for sealing the semiconductor element, or a resin material having high thermal conductivity is filled. Therefore, it is necessary to separately provide a mechanism for dissipating heat in a direction opposite to the electrode side of the semiconductor element.
【０００９】しかしながら、上記構造によれば、製造が
困難であり、また封止後においては素子の検査が不可能
になる上に、半導体装置の製造コストが大幅に上昇する
ことに加えて、さらに耐久性や動作信頼性が低下し易く
なるという問題点があった。However, according to the above-described structure, manufacturing is difficult, and after sealing, it becomes impossible to inspect the element, and the manufacturing cost of the semiconductor device is significantly increased. There has been a problem that durability and operation reliability are likely to decrease.
【００１０】本発明は上記問題点を解決するためになさ
れたものであり、フリップチップ方式により半導体素子
と配線基板とを接合する場合において、半導体素子の発
熱を効果的に放散することが可能な半導体実装構造を提
供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can effectively dissipate heat generated by a semiconductor element when a semiconductor element and a wiring board are joined by a flip-chip method. It is an object to provide a semiconductor mounting structure.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するた
め、本発明に係る半導体実装構造は、半導体素子の電極
部に形成した突起電極を介してフリップチップ方式にて
半導体素子と配線基板とを接続する一方、上記半導体素
子の電極部の反対側表面と配線基板表面とを接続する伝
熱板を配設したことを特徴とする。In order to achieve the above object, a semiconductor mounting structure according to the present invention comprises a semiconductor element and a wiring board which are flip-chip bonded to each other through a projecting electrode formed on an electrode portion of the semiconductor element. A heat transfer plate for connecting the surface of the semiconductor element opposite to the electrode portion and the surface of the wiring board is provided.
【００１２】また、伝熱板は銅およびアルミニウムの少
なくとも一方から選択された高熱伝導性材料から構成す
るとよい。さらに、半田層を介して伝熱板と配線基板表
面とを接合するとよい。また半田層を介して伝熱板と半
導体素子表面とを接合してもよい。さらに配線基板表面
に伝熱板を接合するためのメタライズ層を形成するとよ
い。Preferably, the heat transfer plate is made of a high heat conductive material selected from at least one of copper and aluminum. Further, the heat transfer plate and the surface of the wiring board may be joined via a solder layer. Further, the heat transfer plate and the surface of the semiconductor element may be joined via a solder layer. Further, a metallized layer for bonding the heat transfer plate to the surface of the wiring board may be formed.
【００１３】ここで上記配線基板としてはプリント基板
や、表面および内部に配線層を形成した多層セラミック
ス基板が使用される。この配線基板を構成するセラミッ
クスとしては、特に限定されないが、窒化アルミニウム
（ＡｌＮ）、窒化けい素（Ｓｉ3Ｎ4），アルミナ（Ａｌ
2Ｏ3）などの窒化物系セラミックスや酸化物系セラミッ
クスなどが使用できる。なお、特に熱伝導率が１６０Ｗ
／ｍ・Ｋ以上と高い窒化アルミニウム（ＡｌＮ）製の配
線基板を採用することにより半導体パッケージ全体の放
熱特性を向上させることができる。Here, as the wiring substrate, a printed substrate or a multilayer ceramic substrate having a wiring layer formed on the surface and inside is used. The ceramics constituting this wiring board is not particularly limited, but aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), alumina (Al
Nitride ceramics such as 2 O 3 ) and oxide ceramics can be used. In particular, the thermal conductivity is 160 W
By employing a wiring board made of aluminum nitride (AlN) as high as / m · K or more, the heat radiation characteristics of the entire semiconductor package can be improved.
【００１４】また、伝熱板は半導体素子において発生し
た熱を、半導体素子の電極部と反対方向の表面から、封
止用のリッド（蓋）方向ではなく、配線基板方向に伝達
するために設けられる。この伝熱板を構成する材料とし
ては、特に限定されるものではないが、高熱伝導性を有
する銅，アルミニウムなどの金属材料が好ましい。この
伝熱板の熱伝達効果によって、半導体素子と配線基板と
の熱膨張差に起因する基板や素子の破損および素子の動
作信頼性の低下を抑制することも可能になる。また、熱
伝達とともに熱膨張差が重視される場合には、コバール
合金などの金属材料を使用してもよい。The heat transfer plate is provided to transfer heat generated in the semiconductor element from the surface of the semiconductor element in the direction opposite to the electrode to the wiring board, not to the sealing lid. Can be The material constituting the heat transfer plate is not particularly limited, but is preferably a metal material having high thermal conductivity, such as copper or aluminum. Due to the heat transfer effect of the heat transfer plate, it is also possible to suppress damage to the substrate and the device due to the difference in thermal expansion between the semiconductor device and the wiring substrate and to reduce the operational reliability of the device. When importance is attached to the difference in thermal expansion as well as the heat transfer, a metal material such as a Kovar alloy may be used.
【００１５】上記伝熱板と半導体素子との接合および伝
熱板と配線基板との接合は、汎用の樹脂接着剤を使用し
て接合してもよいが、より熱抵抗が小さい半田層を介し
て接合することが望ましい。The heat transfer plate and the semiconductor element and the heat transfer plate and the wiring board may be bonded using a general-purpose resin adhesive, but may be bonded via a solder layer having a lower thermal resistance. It is desirable to join them.
【００１６】なお伝熱板の両端をそれぞれ半田層を介し
て半導体素子および配線基板にそれぞれ接合してもよい
が、半田層を介して伝熱板の一端と配線基板とを接合す
る一方、伝熱板の他端と半導体素子の表面部とは単に伝
熱板の押圧力（ばね力）のみによって接触するように構
成してもいよい。この場合、素子表面部と伝熱板とは摺
動自在に接触しているため、両者の熱膨張差を吸収する
ことが可能である。したがって、繰り返して熱サイクル
を受けた場合においても、熱膨張差に起因する熱応力が
発生することが少なく、耐熱サイクル特性に優れた半導
体パッケージが得られる。Although both ends of the heat transfer plate may be respectively joined to the semiconductor element and the wiring board via the solder layer, one end of the heat transfer plate and the wiring board are joined to each other via the solder layer, while The other end of the hot plate and the surface portion of the semiconductor element may be configured to contact only by the pressing force (spring force) of the heat transfer plate. In this case, since the element surface and the heat transfer plate are slidably in contact with each other, it is possible to absorb a difference in thermal expansion between the two. Therefore, even when repeatedly subjected to a thermal cycle, thermal stress due to a difference in thermal expansion is less likely to occur, and a semiconductor package having excellent heat cycle characteristics can be obtained.
【００１７】また配線基板表面で伝熱板の一端を接合す
る部位に厚さ１０〜２０μｍ程度のメタライズ層を予め
形成することによって配線基板と伝熱板との接合強度を
高めることが可能であり、両者の熱膨張差に起因する剥
離や割れを効果的に防止でき、半導体パッケージの耐久
性および信頼性を高めることができる。さらにメタライ
ズ層表面にニッケル（Ｎｉ）や金（Ａｕ）などから成る
厚さ１〜５μｍ程度のめっき層を形成することにより、
半田に対する濡れ性を向上し、接合強度をさらに高める
ことが可能となる。さらに配線基板表面に予め設けたメ
タライズ層部分に伝熱板を半田によって接合することに
より、接合部の熱抵抗をさらに低減でき、伝熱板による
放熱効果をさらに改善することができる。Further, by forming in advance a metallized layer having a thickness of about 10 to 20 μm at a portion where one end of the heat transfer plate is bonded on the surface of the wiring substrate, it is possible to increase the bonding strength between the wiring substrate and the heat transfer plate. Also, peeling and cracking due to the difference in thermal expansion between the two can be effectively prevented, and the durability and reliability of the semiconductor package can be improved. Further, by forming a plating layer having a thickness of about 1 to 5 μm made of nickel (Ni) or gold (Au) on the surface of the metallized layer,
It is possible to improve the wettability to solder and further increase the bonding strength. Furthermore, by joining the heat transfer plate to the metallized layer portion provided in advance on the surface of the wiring board by soldering, the thermal resistance of the joint can be further reduced, and the heat dissipation effect of the heat transfer plate can be further improved.
【００１８】上記構成に係る半導体実装構造によれば、
半導体素子において発生した熱は、突起電極とともに伝
熱板を経由して配線基板方向に効率的に伝達されるた
め、放熱性が大幅に改善される。特に伝熱板の熱伝達効
果によって半導体素子の放熱が極めて容易になる。さら
に半導体素子と配線基板との熱膨張差に起因する基板や
素子の破損および素子の動作信頼性の低下を効果的に防
止でき、耐久性，放熱性，信頼性に優れた半導体パッケ
ージを実現することができる。According to the semiconductor mounting structure having the above configuration,
The heat generated in the semiconductor element is efficiently transmitted in the direction of the wiring board via the heat transfer plate together with the protruding electrodes, so that the heat dissipation is greatly improved. In particular, the heat transfer effect of the heat transfer plate makes it extremely easy to radiate heat from the semiconductor element. Furthermore, it is possible to effectively prevent breakage of the substrate and the element due to the difference in thermal expansion between the semiconductor element and the wiring board and decrease in the operational reliability of the element, thereby realizing a semiconductor package having excellent durability, heat dissipation, and reliability. be able to.
【００１９】[0019]
【発明の実施の形態】次に本発明の実施形態について、
添付図面を参照して説明する。なお、図７および図８に
示す従来例と同一要素には同一符号を付している。Next, an embodiment of the present invention will be described.
This will be described with reference to the accompanying drawings. The same elements as those in the conventional example shown in FIGS. 7 and 8 are denoted by the same reference numerals.
【００２０】実施例１ 図１および図２は本発明に係る半導体実装構造を半導体
パッケージに適用した実施例を示す平面図および断面図
である。すなわち本実施例に係る半導体パッケージ７
は、半導体素子１の電極部に形成した突起電極（半田バ
ンプ）２を介してフリップチップ方式にて半導体素子１
とＡｌＮ多層配線基板３とを接続する一方、上記半導体
素子１の電極部の反対側表面とＡｌＮ多層配線基板３の
表面とを接続する４個の銅製伝熱板６を配設して構成さ
れる。 Embodiment 1 FIGS. 1 and 2 are a plan view and a sectional view showing an embodiment in which a semiconductor mounting structure according to the present invention is applied to a semiconductor package. That is, the semiconductor package 7 according to the present embodiment
Is a semiconductor element 1 formed by flip-chip bonding via a projecting electrode (solder bump) 2 formed on an electrode portion of the semiconductor element 1.
And the AlN multilayer wiring board 3, while four copper heat transfer plates 6 are provided to connect the opposite surface of the electrode portion of the semiconductor element 1 to the surface of the AlN multilayer wiring board 3. You.
【００２１】また上記ＡｌＮ多層配線基板３の表面およ
び内部には配線層４が形成されており、配線層４の一端
は突起電極２を介して半導体素子の各電極部と接続され
る一方、配線層４の他端は基板３の裏面に接合された入
出力ピン５に接続されている。４個の伝熱板６はそれぞ
れ半導体素子１の４辺の中央部とＡｌＮ多層配線基板３
の表面とを接続するように配置される。さらに各伝熱板
６の下端部は半田層８を介してＡｌＮ多層配線基板３の
表面に接合されている。A wiring layer 4 is formed on the surface and inside of the AlN multilayer wiring board 3. One end of the wiring layer 4 is connected to each electrode portion of the semiconductor element through the protruding electrode 2, while the wiring The other end of the layer 4 is connected to an input / output pin 5 joined to the back surface of the substrate 3. The four heat transfer plates 6 are respectively located at the center of the four sides of the semiconductor element 1 and the AlN multilayer wiring board 3.
It is arranged so as to connect with the surface. Further, the lower end of each heat transfer plate 6 is joined to the surface of the AlN multilayer wiring board 3 via a solder layer 8.
【００２２】本実施例に係る半導体パッケージ７におい
て、半導体素子１で発生した熱は、主として伝熱板６を
経由してＡｌＮ多層配線基板３方向に効率的に伝達され
る。したがって、図７および図８に示す従来の半導体パ
ッケージにおいては突起電極２を経由した少ない熱伝導
量であったため、放熱性が不十分であったが、本実施例
によればＡｌＮ多層配線基板３方向への熱伝導量が飛躍
的に増大化する結果、半導体パッケージの放熱性が大幅
に改善でき、高出力化および高集積化を指向する大規模
集積回路（ＬＳＩ）などの半導体素子を搭載したパッケ
ージとして極めて有効である。In the semiconductor package 7 according to the present embodiment, heat generated in the semiconductor element 1 is efficiently transmitted mainly to the AlN multilayer wiring board 3 via the heat transfer plate 6. Therefore, in the conventional semiconductor package shown in FIGS. 7 and 8, the heat dissipation was insufficient due to the small amount of heat conduction via the bump electrodes 2. As a result, the heat dissipation of the semiconductor package can be greatly improved, and a semiconductor device such as a large-scale integrated circuit (LSI) for high output and high integration is mounted. Very effective as a package.
【００２３】実施例２ 図３および図４はそれぞれ本発明に係る半導体実装構造
を半導体パッケージに適用した他の実施例を示す平面図
および断面図である。すなわち本実施例に係る半導体パ
ッケージ７ａは、実施例１で用いたＬ字形の伝熱板６に
代えて、断面がＵ字形状の伝熱板６ａを用いた点以外は
実施例１と同様な手順で製造されている。 Embodiment 2 FIGS. 3 and 4 are a plan view and a sectional view, respectively, showing another embodiment in which the semiconductor mounting structure according to the present invention is applied to a semiconductor package. That is, the semiconductor package 7a according to the present embodiment is the same as the first embodiment except that a heat transfer plate 6a having a U-shaped cross section is used instead of the L-shaped heat transfer plate 6 used in the first embodiment. Manufactured by procedures.
【００２４】上記半導体パッケージ７ａにおいても、実
施例１と同様に、半導体素子１で発生した熱は伝熱板６
ａを経由してＡｌＮ多層配線基板３方向に効率的に伝達
され、パッケージ全体としての放熱性を、従来構造のも
のより大幅に改善できる。In the semiconductor package 7a, as in the first embodiment, the heat generated in the semiconductor element 1 is transferred to the heat transfer plate 6a.
The heat is efficiently transmitted in the direction of the AlN multilayer wiring board 3 via the line a, and the heat dissipation of the entire package can be greatly improved as compared with the conventional structure.
【００２５】なお図３に示す実施例では１枚の帯状の伝
熱板６ａを半導体素子１の表面側に被着した構造例を示
しているが、帯状の伝熱板６ａを複数枚、平行して配設
することも可能であり、放熱特性の要求水準に応じて伝
熱板６ａの配設枚数を増減してもよい。Although the embodiment shown in FIG. 3 shows an example of a structure in which one band-like heat transfer plate 6a is attached to the front side of the semiconductor element 1, a plurality of band-like heat transfer plates 6a are formed in parallel. The number of the heat transfer plates 6a may be increased or decreased according to the required level of the heat radiation characteristics.
【００２６】実施例３ 図５および図６はそれぞれ本発明に係る半導体実装構造
を半導体パッケージに適用したその他の実施例を示す平
面図および断面図である。すなわち本実施例に係る半導
体パッケージ７ｂは、実施例１において素子１の各辺中
央部とＡｌＮ多層配線基板３の表面とを接続する伝熱板
６に代えて、素子１の各角部表面と基板３の表面とを接
続する伝熱板６ｂを配設した点、および各伝熱板６ｂの
下端部が基板３の表面と接合する部位にＷメタライズ層
９を予め形成した点以外は実施例１と同様な手順で製造
したものである。 Embodiment 3 FIGS. 5 and 6 are a plan view and a sectional view, respectively, showing another embodiment in which the semiconductor mounting structure according to the present invention is applied to a semiconductor package. That is, in the semiconductor package 7b according to the present embodiment, instead of the heat transfer plate 6 connecting the center of each side of the device 1 and the surface of the AlN multilayer wiring board 3 in the first embodiment, the semiconductor package 7b Embodiments are the same as those of the embodiment except that a heat transfer plate 6b for connecting to the surface of the substrate 3 is provided, and a W metallized layer 9 is previously formed at a position where the lower end of each heat transfer plate 6b is joined to the surface of the substrate 3. This was manufactured by the same procedure as in Example 1.
【００２７】上記半導体パッケージ７ｂにおいても、実
施例１と同様に、半導体素子１で発生した熱は伝熱板６
ｂを経由してＡｌＮ多層配線基板３方向に効率的に伝達
され、パッケージ全体としての放熱性を、従来構造のも
のより大幅に改善することができる。In the semiconductor package 7b, as in the first embodiment, the heat generated by the semiconductor element 1
The heat is efficiently transmitted in the direction of the AlN multilayer wiring board 3 via the “b”, and the heat dissipation of the entire package can be significantly improved as compared with the conventional structure.
【００２８】さらに各伝熱板６ｂと下端と接合するＡｌ
Ｎ多層配線基板３の表面部位に予めＷメタライズ層９を
形成し、半田層８を介して各伝熱板６ｂを接合している
ため、伝熱板６ｂと配線基板３との接合強度が高まり、
耐熱サイクル特性を大幅に改善することができる。Further, the heat transfer plate 6b is joined to the lower end by Al.
Since the W metallization layer 9 is formed in advance on the surface of the N multilayer wiring board 3 and the respective heat transfer plates 6b are bonded via the solder layer 8, the bonding strength between the heat transfer plate 6b and the wiring substrate 3 is increased. ,
The heat cycle characteristics can be greatly improved.
【００２９】上記実施例１〜３のような半導体実装構造
を有する半導体パッケージにおいては、半導体素子１の
表面側と配線基板３の表面と接続する伝熱板６，６ａ，
６ｂを配設して素子１で発生した熱を配線基板３側に伝
達する構造であるため、従来のようにリッドと素子との
間を樹脂封止して半導体素子の表面側に熱を放散させる
機構を別途に設ける必要がなく、パッケージ構造が大幅
に簡素化されるという効果も発揮される。In the semiconductor package having the semiconductor mounting structure as in the first to third embodiments, the heat transfer plates 6, 6 a connected to the surface of the semiconductor element 1 and the surface of the wiring board 3 are connected.
6b is arranged to transfer the heat generated in the element 1 to the wiring board 3 side, so that the heat is radiated to the surface side of the semiconductor element by sealing the resin between the lid and the element as in the conventional case. There is no need to provide a separate mechanism for effecting this, and the effect of greatly simplifying the package structure is also exhibited.
【００３０】また突起電極２を介して半導体素子１を配
線基板３の表面に接合する際に、同時に各伝熱板を配線
基板３表面に半田層８を介して接合することが可能であ
り、半導体素子１を搭載する半導体パッケージの組立が
大幅に簡素化される。Further, when the semiconductor element 1 is joined to the surface of the wiring board 3 via the protruding electrodes 2, it is possible to simultaneously join each heat transfer plate to the surface of the wiring board 3 via the solder layer 8. Assembly of a semiconductor package on which the semiconductor element 1 is mounted is greatly simplified.
【００３１】[0031]
【発明の効果】上記構成に係る半導体実装構造によれ
ば、半導体素子において発生した熱は、突起電極ととも
に伝熱板を経由して配線基板方向に効率的に伝達される
ため、放熱性が大幅に改善される。特に伝熱板の熱伝達
効果によって半導体素子の放熱が極めて容易になる。さ
らに半導体素子と配線基板との熱膨張差に起因する基板
や素子の破損および素子の動作信頼性の低下を効果的に
防止でき、耐久性，放熱性，信頼性に優れた半導体パッ
ケージを実現することができる。According to the semiconductor mounting structure having the above structure, the heat generated in the semiconductor element is efficiently transmitted to the wiring board via the heat transfer plate together with the protruding electrodes, so that the heat radiation is greatly improved. To be improved. In particular, the heat transfer effect of the heat transfer plate makes it extremely easy to radiate heat from the semiconductor element. Furthermore, it is possible to effectively prevent breakage of the substrate and the element due to the difference in thermal expansion between the semiconductor element and the wiring board and decrease in the operational reliability of the element, thereby realizing a semiconductor package having excellent durability, heat dissipation, and reliability. be able to.
【図１】本発明に係る半導体実装構造の一実施例を示す
平面図。FIG. 1 is a plan view showing one embodiment of a semiconductor mounting structure according to the present invention.
【図２】図１におけるII−II矢視断面図。FIG. 2 is a sectional view taken along the line II-II in FIG.
【図３】本発明に係る半導体実装構造の他の実施例を示
す平面図。FIG. 3 is a plan view showing another embodiment of the semiconductor mounting structure according to the present invention.
【図４】図３におけるIV−IV矢視断面図。FIG. 4 is a sectional view taken along the line IV-IV in FIG. 3;
【図５】本発明に係る半導体実装構造のその他の実施例
を示す平面図。FIG. 5 is a plan view showing another embodiment of the semiconductor mounting structure according to the present invention.
【図６】図５におけるVI−VI矢視断面図。FIG. 6 is a sectional view taken along the line VI-VI in FIG. 5;
【図７】従来の半導体実装構造の一例を示す平面図。FIG. 7 is a plan view showing an example of a conventional semiconductor mounting structure.
【図８】図７におけるVIII−VIII矢視断面図。8 is a sectional view taken along the line VIII-VIII in FIG. 7;
１ 半導体素子（半導体チップ，ＬＳＩ） ２ 突起電極（半田バンプ） ３ 配線基板（パッケージ本体） ４ 配線層 ５ 入出力ピン ６，６ａ，６ｂ 伝熱板 ７，７ａ，７ｂ 半導体パッケージ ８ 半田層 ９ メタライズ層（Ｗメタライズ層） DESCRIPTION OF SYMBOLS 1 Semiconductor element (semiconductor chip, LSI) 2 Protruding electrode (solder bump) 3 Wiring board (package main body) 4 Wiring layer 5 I / O pin 6, 6a, 6b Heat transfer plate 7, 7a, 7b Semiconductor package 8 Solder layer 9 Metallization Layer (W metallized layer)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小岩 馨 神奈川県横浜市鶴見区末広町２の４ 株式 会社東芝京浜事業所内 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kaoru Koiwa 2-4, Suehirocho, Tsurumi-ku, Yokohama-shi, Kanagawa Inside the Toshiba Keihin Plant
Claims (6)
を介してフリップチップ方式にて半導体素子と配線基板
とを接続する一方、上記半導体素子の電極部の反対側表
面と配線基板表面とを接続する伝熱板を配設したことを
特徴とする半導体実装構造。1. A semiconductor device and a wiring board are connected by a flip-chip method via a protruding electrode formed on an electrode portion of the semiconductor device, and a surface opposite to the electrode portion of the semiconductor device and a surface of the wiring substrate are connected to each other. A semiconductor mounting structure comprising a heat transfer plate to be connected.
とも一方から選択された高熱伝導性材料から成ることを
特徴とする請求項１記載の半導体実装構造。2. The semiconductor mounting structure according to claim 1, wherein the heat transfer plate is made of a high heat conductive material selected from at least one of copper and aluminum.
を接合したことを特徴とする請求項１記載の半導体実装
構造。3. The semiconductor mounting structure according to claim 1, wherein the heat transfer plate and the surface of the wiring board are joined via a solder layer.
とを接合したことを特徴とする請求項１記載の半導体実
装構造。4. The semiconductor mounting structure according to claim 1, wherein the heat transfer plate and the surface of the semiconductor element are joined via a solder layer.
メタライズ層を形成したことを特徴とする請求項１記載
の半導体実装構造。5. The semiconductor mounting structure according to claim 1, wherein a metallized layer for bonding a heat transfer plate is formed on the surface of the wiring board.
ニウム焼結体から成ることを特徴とする請求項１記載の
半導体実装構造。6. The semiconductor mounting structure according to claim 1, wherein the wiring board is made of an aluminum nitride sintered body having a high heat transfer coefficient.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16214696A JPH1012779A (en) | 1996-06-21 | 1996-06-21 | Semiconductor mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16214696A JPH1012779A (en) | 1996-06-21 | 1996-06-21 | Semiconductor mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1012779A true JPH1012779A (en) | 1998-01-16 |
Family
ID=15748920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16214696A Pending JPH1012779A (en) | 1996-06-21 | 1996-06-21 | Semiconductor mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1012779A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006038543A3 (en) * | 2004-10-04 | 2006-05-26 | Toshiba Kk | Light emitting device, lighting equipment or liquid crystal display device using such light emitting device |
| US8053082B2 (en) | 2004-03-23 | 2011-11-08 | Ube Industries, Ltd. | Adhesion-enhanced polyimide film, process for its production, and laminated body |
-
1996
- 1996-06-21 JP JP16214696A patent/JPH1012779A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8053082B2 (en) | 2004-03-23 | 2011-11-08 | Ube Industries, Ltd. | Adhesion-enhanced polyimide film, process for its production, and laminated body |
| WO2006038543A3 (en) * | 2004-10-04 | 2006-05-26 | Toshiba Kk | Light emitting device, lighting equipment or liquid crystal display device using such light emitting device |
| JPWO2006038543A1 (en) * | 2004-10-04 | 2008-05-15 | 株式会社東芝 | Light emitting device and lighting apparatus or liquid crystal display device using the same |
| US7812360B2 (en) | 2004-10-04 | 2010-10-12 | Kabushiki Kaisha Toshiba | Light emitting device, lighting equipment or liquid crystal display device using such light emitting device |
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