JPH10124546A - Device and method for compressing graphic layout - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arrange wiring without moving any via hole or parts terminal when newly adding wring to a pattern after its layout had finished. SOLUTION: A layout correction designating means 5 has an input means such as a mouse, and gives commands to an intra-allowable interval compaction means 6, a wiring compaction means 7, a rewiring means 8 and an allowable interval calculating means 9. The correction designating means 5 prepares vertical order data with respect to wirings decomposed for each terminal, via hole or corner. The allowable interval calculating means 9 prepares vertical and horizontal order data for vertically arranging all the elements in order and further calculates the allowable interval between the parts terminal and the via hole. Based on allowable interval data, the intra-allowable interval compaction means 6 moves the parts terminal and the via hole while compacting them downward and further moves the parts terminal and the via hole to positions having spaces so as to keep the interval of 'interval correcting amount' with the adjacent element if possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic layout compressing apparatus and method, and more particularly to a graphic layout compressing apparatus and method for performing compaction processing on component layout and wiring design of printed wiring boards and integrated circuits.

[0002]

2. Description of the Related Art An automatic layout apparatus is used for designing a layout of a large-scale semiconductor integrated circuit and a layout of a printed wiring board. Various compaction techniques have been conventionally proposed for this type of layout apparatus. That is, as a first prior art, Japanese Patent Laid-Open No. 2-16
Japanese Patent Application Publication No. 5654 discloses a "method of changing the design of a semiconductor integrated circuit". This is because when adding a new wiring to an existing layout, it receives a layout correction command from the operator, specifies the compaction separation line and the area near it, and places the wiring around the compaction separation line as the center. In this case, a space is opened near the compaction separation line, and wiring is inserted and added into the space.

A second prior art is disclosed in Japanese Patent Laid-Open No. 1-2
Japanese Patent No. 79373, entitled "LSI Layout Compressor" is known. The purpose of this is to compress the layout of each cell and wiring on an LSI chip into a smaller area, and search for the longest graphic element in the layout and display the longest path on the display unit. Search means, and layout enlarging means for inserting a space that intersects the longest order into the layout, and the layout modification designating means receives a command from the operator to extract a segment from the order so as to shorten the longest order. It has compaction means for moving and compressing the resulting layout.

Further, as a third prior art, Japanese Patent Laid-Open No.
No. 51855, “Layout compaction device”
It has been known. This is provided with means for setting a compaction prohibited area for a block cell for each wiring layer, and means for compacting a layout pattern based on the prohibited area set by the prohibited area setting means.

[0005]

In the above-mentioned conventional compaction apparatus and compaction method, the wires are compacted by compaction means so that the wires are brought together and arranged in a dense state with a small gap between the wires. . Therefore, when a new wiring is inserted and added, it is necessary to perform a compaction process for opening a space for the added wiring as in the first related art. This has the drawback that a large amount of time is required since a large number of through-holes and a plurality of wirings in the vicinity thereof are moved by compaction processing. Therefore, the problem to be solved by the present invention is to arrange a component terminal or a via hole with a margin as much as possible, so that wiring can be added to an existing layout without requiring a large number of steps. It is.

[0006]

According to the present invention, there is provided a graphic layout compression apparatus for compacting a pattern of one or more layers having wiring, terminals, and via holes. And layout modification designating means (5) for decomposing the wiring, terminals and via holes into segments and creating vertical and horizontal order data of all the segments, and calculating the order of the vertical and horizontal directions of all the segments. (9) for calculating the allowable data between the terminal and the via hole and the adjacent terminals and via holes, and moving and arranging the terminal and the via hole in the lower or upper position and in the left or right position. Then, the compaction means (6) within the allowable interval for re-arranging the terminals and the via holes at a marginal interval, and arranging the wiring in a lower or upper position and a left or right position. Wiring compaction means (7),
Rewiring means (8) for arranging the wiring at a position at least an allowable distance from a neighboring element, layout data storing means (12, 13) for storing layout data, and permission for storing an allowable distance between terminals and via holes. A graphic layout compression device having interval data storage means (11) is provided.

Further, according to the present invention, there is provided a graphic layout compression method for compacting a pattern of one or more layers having wiring, terminals and via holes, wherein the wiring, terminals and via holes in the input layout data are segmented. And the process of creating vertical and horizontal order data of all segments, and the creation of upper and lower and left and right order data of all segments, and the allowable spacing between terminals and via holes and neighboring terminals and via holes And moving and arranging the terminals and via holes to the left or right with left and right justifications at the allowable interval determined in the previous process, and, if possible, adding one extra terminal and via hole The process of rearranging with a margin for the amount of gap correction with the aim of the width of the wiring, and arranging the wiring bottom or top, left or right,
Storing the position as wiring limit position data;
A step of arranging the wiring so as to be the shortest distance in a space between a position at an allowable distance from a segment existing on the opposite side to the wiring packing direction and the wiring position stored as the wiring limit position data; And a graphic layout compression method having the following.

Further, according to the present invention, there is provided a graphic layout compression method for compacting a pattern of one or more layers having wiring, terminals and via holes, wherein the wiring, terminals and via holes in the layout data are decomposed into fragments. A step of storing the terminal and the via-hole segment whose position has been changed or added as the starting segment; a step of creating upper and lower and left and right order data of all the segments based on the updated layout data; Calculating the permissible distance between the via hole and the neighboring terminal and via hole, and moving the starting element and the element that has been moved due to the provision of the starting element between the neighboring terminal and the via hole. If it is possible to have at least the above-mentioned permissible interval, the width is set so that one extra wiring can pass through the above-mentioned permissible interval. A process of moving at an interval obtained by adding the gap correction, graphic layout compression method having the steps, the placing on the wiring was separated from neighboring segments or acceptance interval position, is provided.

[0009]

FIG. 1 is a block diagram showing a schematic configuration of a graphic layout compression apparatus according to the present invention. In FIG. 1, a display means 4 comprises a CRT display or a liquid crystal display, and displays layout data in addition to an initial layout pattern, a layout pattern being changed, and a final layout pattern. The layout modification designating means 5 (hereinafter abbreviated as modification designating means 5 as appropriate) has input means such as a console, a mouse or a touch panel, and issues a command to display the input result and the correction result on the display means 4. This is a means for issuing a command to operate the corresponding predetermined function means. The functional means for instructing the operation of the modification designating means 5 include compaction means 6 within the allowable interval of component terminals and via holes (hereinafter abbreviated as compaction means 6 within the allowable interval as appropriate).
There are a wiring compaction unit 7, a rewiring unit 8, and an allowable interval calculating unit 9 for component terminals and via holes (hereinafter abbreviated as the allowable interval calculating unit 9 as appropriate).

The layout modification designating means 5 decomposes the via holes among the component terminals, via holes, and wirings constituting the layout pattern for each layer surface, and disassembles the wirings for each corner, to obtain the component terminals and the disassembled via holes. ,
Unit data is created using each of the decomposed wires as a unit. Then, upper and lower order data and left and right order data of segments indicating the vertical and horizontal relationships of adjacent segments are created. The allowable interval calculating means 9 receiving the instruction of the correction designating means 5 creates up-down and left-right order data for arranging all the pieces in the up-down and left-right order, and furthermore, makes the connection between the component terminal and the component terminal and the via hole near the via hole. Is calculated, and this is calculated as the allowable interval data 1 for component terminals and via holes.
1 (hereinafter, appropriately abbreviated as allowable interval data 11).

The within-permissible-interval compaction means 6 shifts the positions of the component terminals and via holes to the lower (or upper) and right (or left) positions based on the allowable interval data 11 of the component terminals and via holes. Then, when these segments are moved, the allowable interval calculation means 9 is operated to update the allowable interval data 11. The loop between the permissible interval calculating means 9 and the permissible interval compaction means 6 is repeated a plurality of times. The compaction means 6 within the permissible interval may further include a “gap correction amount” if the component terminal and the via hole except for the component terminal and the via hole whose position is specified can be spaced from the adjacent component terminal or via hole.
Move so that there is enough room. Here, the gap correction amount is set to a width that allows one extra wiring to pass through, that is, an amount obtained by adding a necessary interval to another element to the wiring width. The layout data 13 of the component terminals and via holes created by the compaction unit 6 within the allowable interval is transmitted to the modification designating unit 5, and the layout data 12 is updated via the modification designating unit 5.

After the arrangement of the component terminals and the via holes is determined, the wiring compaction unit 7 performs a compaction operation of compressing the wiring by packing the wiring downward (or above) and left (or right). When the compaction work is performed by the wiring compaction means 7, the rewiring means 8 determines whether the position determined by the limit position data on the packed side is equal to the position spaced from the element on the opposite side by an allowable distance. Rearrange the wiring in the space between them. Further, when the compaction work is not performed by the wiring compaction means 7, the rewiring means 8 arranges the wiring at a position separated from the neighboring element by an allowable distance or more.

[0013]

Next, embodiments of the present invention will be described in detail with reference to the drawings. [First Embodiment] FIG. 1 shows a first embodiment of the present invention.
This will be described with reference to FIG. FIG. 2 is a flowchart of the overall processing procedure of the compaction processing according to the present embodiment. 3 and 4 are plan views showing pictures for explaining the processing operation of the first embodiment. FIG. 3A shows the initial state of a printed wiring board to be processed in this embodiment. 2 shows a layout. FIGS. 4B and 4C are plan views showing layouts in a state where the processing according to the present embodiment has been completed. 3 and 4, reference numeral 1 denotes a component terminal, reference numeral 2 denotes a wiring, and reference numeral 3 denotes a via hole connecting between layers.

The operation of the graphic layout compression apparatus of the present invention for compacting the layout of FIG. 3A will be described below with reference to the flowchart of the processing procedure of FIG. In this embodiment, after the compaction process is completed,
Wiring 2 connecting terminal A and terminal B is inserted. Here, the initial layout of the printed wiring board of FIG. 3A can be applied even when the gap between the adjacent wiring 2, the terminal 1, and the via hole 3 does not adhere to the minimum gap of the design rule. It is. This is because gaps smaller than the minimum dimension of the design rule are corrected in the course of processing according to the present embodiment.

First, the modification designating means 5 recognizes the layout of the layout data 12 as follows (step S11). That is, layout data 1
2 is analyzed, each terminal 1 of the component is defined as one element, the via hole 3 is divided into each layer surface, and each element is defined as one element, and each wiring is divided at a corner and a branch point, and each element is defined as one element. Create segment data. For example, in FIG. 3A, the terminal numbers are assigned to the terminals 1a, 1b,..., The wiring pieces 2a, 2b,. FIG.
FIGS. 5A and 5B are diagrams showing the data structure of the generated piece data 14. FIG. 5A shows the data structure of the piece data 14 of the terminal 1 and the via hole 3, and FIG. FIG. 5B shows the data structure of the segment data 14 of FIG. In the segment data 14, a moving set number 15 is recorded in which all the segments of the terminal related to one component are set to the same moving set, and the segments of all the layer surfaces of one via hole 3 are set to the same moving set.
Also, a wiring 2 connected to the terminal 1 or the via hole 3
In the segment data 14, the moving set number 15 that is the same as the terminal 1 or via hole 3 to which the end of the wiring is connected is recorded corresponding to the end of the wiring. In the segment data 14, a coordinate value is further recorded. The above is Step S11.

Next, for each layer surface, a search is made for a segment that overlaps vertically (here, up and down means up and down on the paper surface of FIG. 3 and the like, but does not mean a direction perpendicular to the paper surface).
In the data structure shown in FIG. 5 (c), unit vertical order data 16 for recording the unit number of the unit overlapping above and the unit number of the unit overlapping below is created (step S12). In FIG. 3, for example, for the terminal element 1a, vertical order data is created between the terminal elements 1b and 1c, and for the wiring element 2a, the terminal element 1a, the wiring elements 2b, 2c, 2d, and 2e are formed. , 2f and the via-hole piece 3a, a vertical order of the pieces is provided. In addition, the lowest boundary line X of the arrangement area of these segments is recorded at the bottom of the segment vertical order data 16. This boundary line X indicates, for example, the edge of the printed wiring board. Similarly, in the left-right direction, the unit left-right order data 1
6 'is created. In the present invention, the same processing as in the up-down direction is performed in the left-right direction. However, for simplicity, the following description will be mainly made in the up-down direction, but it is understood that the same processing is performed in the left-right direction. I want to be.

Next, the allowable interval calculating means 9 calculates
The network structure formed by the segment upper / lower order data 16 is arranged, and the segments from the lower order segment to the upper order segment are shown in FIG.
The upper and lower rank data 17 indicating the data structure is created in (d) (step S13). As shown in FIG. 3A, the order of the upper / lower ranking data 17 is as follows.
... Note that this ranking is not uniquely determined. For example, the numbered terminal pieces may be numbered, and the numbers may be ranked in order from the left to the left. Next, the allowable interval calculating means 9 starts from the terminal 1 or the via hole 3 and traces the network structure formed by the segment vertical order data 16 from the bottom to the top, and searches for the terminal 1 or the via hole 3 existing above. Also, it stores the wiring 2 that passes through it. The width of the wiring 2 passing therethrough, the radii of the upper and lower ends of the pieces, and the sum of the necessary minimum gap therebetween are calculated, and the allowable interval 10 in the vertical direction between the two pieces is obtained. The permissible interval 10 is calculated as the permissible interval 10 on the left and right, the permissible interval 10 on the top and bottom, and the permissible interval 10 in the diagonal direction of 45 degrees. FIG. 6A shows a case in which two wires are interposed between the upper element A and the lower element B, and FIG.
Is indicated by a broken line at a position vertically spaced apart from the lower element B by an allowable distance 10. In FIG. 6 (c), the position where the upper element A is separated from the lower element B by 10 to the left and right at an allowable distance 10 is indicated by a broken line. In the case where the left and right interval between the upper and lower segments is smaller than the allowable left and right interval 10, that is, when the upper and lower segments are in a vertically overlapping relationship, FIG. ), The terminal / via hole vertical order data 18 for recording the upper unit number and the lower unit number is created. Here, the vertical coordinate value of the lower element is subtracted from the vertical coordinate value of the upper element, and a value obtained by subtracting the upper and lower allowable interval 10 is calculated. The relative limit movement amount 19 with respect to the segment is recorded in the terminal / via hole vertical order data 18 (step S14). When the allowable interval 10 is obtained for the segments A and B having the positional relationship of FIG. 6A as shown in FIG. 6B, the relative limit movement amount 19 is as shown in FIG.
The result is as shown in FIG.

Next, the compaction means 6 within the allowable interval between the component and the via hole removes only the terminal 1 and the via hole 3 excluding the wiring 2 from the following steps S15 to S17.
Arrange by the procedure up to. In step S15, first, the position of the boundary line X of the arrangement area of the segment is fixed, and for the component whose position is designated, the moving amount 21 of the moving set of the terminal segment is fixed to the designated value. The moving set of the via hole 3 sets the initial value of the moving amount 21 to infinity. Here, the moving aggregate data 22 whose data structure is shown in FIG. 7B is created. The moving amount is not updated for the moving set number whose position is fixed, but is sequentially updated from the infinity of the initial value to a smaller value for other moving set numbers. The terminal 1 and the via hole 3 are selected in the order from the bottom to the top of the unit upper and lower order data 17 and are arranged as processing units in the following procedure. That is, the terminal / via hole vertical order data 18 including the processing unit as the upper unit is extracted, and the value obtained by adding the relative limit moving amount 19 to the moving amount 21 of the moving set to which the lower unit belongs is calculated as the processing unit. Is the maximum limit movement amount 20 of the moving set. For example, as shown in FIG.
When the moving amount 21 of the moving set to which the lower unit B belongs is given to the unit A as the processing unit as illustrated, the maximum limit moving amount 20 of the moving set to which the unit A belongs is Provided as shown. If the maximum limit movement amount is less than the existing movement amount 21 of the moving set to which the processing element belongs, the existing movement amount 21 is updated by the maximum limit movement amount 20.

After this processing is performed from the bottom up, that is, after step S15 is performed, it is checked whether or not the movement amount 21 has been updated in the cycle (step S16). If the update has been performed, step S15 is repeated again. By repeating steps S15 and S16 in this manner for a plurality of cycles, the terminals and via holes are lowered, and when the movement amount is no longer updated, the movement amounts of all the moving groups are reduced to 21.
Has been updated to the appropriate value. FIG. 3B shows a position where the terminal 1 and the via hole 3 are moved and arranged in the above procedure. In FIG. 3B, only the terminal 1 or the via hole 3 is moved, and the wiring 2 is hidden by the shadow of the allowable interval 10, but the existence of the wiring 2 defining the allowable interval 10 is indicated by a broken line.

Next, except for the component whose position is designated, the terminal 1 and the via hole 3 of the component are rearranged as follows (step S17). Here, parts other than the small parts are
You can also specify the position to fix to the position obtained in 16,
In that case, the other via holes 3 and small parts are rearranged. In step S17, first, the moving amount 21 of the moving set of the segment excluding the one whose position is designated is calculated in step S15.
Set to an initial value equal to or less than the value obtained in. Next, the segments of the terminal 1 and the via hole 3 of the component whose position is not fixed are selected from the top and bottom order data 17 of the segments in order from the top to the bottom to be processed. The terminal / via hole upper / lower order data 18 including the same is extracted for each processing unit, and the data is rearranged with respect to them, satisfying the following priority order conditions.

(Priority 1) In the case where the processing element is the lower element in the terminal / via hole vertical order data 18, the moving amount 21 of the moving set is the relative limit moving amount from the moving amount 21 of the upper element. Increase the value by subtracting 19. (Priority 2) When the processing unit is the upper unit in the terminal / via hole vertical order data 18, the moving amount 21 of the moving set to which the processing unit belongs is set to the maximum limit moving amount 20 or less. That is, the moving amount 21 of the moving set is set to be equal to or less than the initial value of the lower segment or the value obtained by adding the relative limit moving amount 19 to the moving amount 21 determined thereafter. (Priority 3) When the processing unit is the lower unit in the terminal / via hole vertical order data 18, the moving amount 21 of the moving set is obtained by subtracting the relative limit moving amount 19 from the moving unit 21 of the upper unit. Set it to a value equal to or greater than the value obtained by adding the gap correction amount. This gap correction amount is set to the sum of the width of the wiring 2 and the required minimum distance between the wirings. This value is 0.3175 m for a normal printed wiring board.
m or about 0.508 mm. (Priority 4) When the processing unit is the upper unit in the terminal / via hole vertical order data 18, the moving amount 21 of the moving set is relative to the moving amount 21 of the lower unit moving set. 19 is added to make the value equal to or less than the value obtained by subtracting the gap correction amount.

In the above priority order, the higher the order, the higher the priority. (Priority 1) must be satisfied, but other things do not have to be satisfied. When (priority 1) is satisfied but cannot be satisfied after (priority 2), the moving amount 21 of the moving set to which the processing unit belongs is selected so as to be as close as possible to the condition of (priority 2). . Similarly, when (priority 1) and (priority 2) are satisfied but cannot be satisfied after (priority 3), the moving amount 21 of the moving set to which the processing unit belongs
Are selected so as to be as close as possible to the condition of (priority 3). When all the priorities are satisfied, the movement amount 21 is determined to be an arbitrary value within a range that satisfies those conditions. As a result, if any of the conditions of the priority order 2 is not satisfied, step S17 is repeated again until the condition of the priority order 2 is satisfied. Thus, as shown in FIG. 3C, the terminal 1 and the via hole 3 of the component are arranged with a margin for the gap correction amount (step S17).

After the terminals 1 and the via holes 3 of these components are determined at the moving positions, the wiring compaction means 7 arranges the wirings 2 in the order of the unit vertical order data 17 from bottom to top. At this time, the wiring is arranged at the bottom and the position is stored as the wiring lower limit position data 23 (step S1).
8). This wiring lower limit position data 23 is shown in FIG. Next, the re-wiring means 8 selects the segments of the wiring 2 in the reverse order of the vertical order data 17 of the segments from top to bottom and arranges them as processing segments as follows. That is, unit vertical order data 16 having a processing unit as a lower unit is extracted,
The position of the segment on it is read. Further, the wiring lower limit position data 23 is read out, and the wiring 2 is arranged at the shortest distance in a space between a position at an allowable distance from the element above the wiring 2 and the wiring lower limit position data 23 (step S19). FIG. 4B shows the result of this wiring.

If it becomes necessary to add a new wiring 2 for connecting the terminals A and B to the layout shown in FIG. 4B, a broken line is shown in FIG. 4C. Like the wiring 2, the new wiring 2 can be inserted without moving the via hole 3 and the wiring 2. Although the examples shown in FIGS. 3 and 4 are simple patterns, even if the pattern is more complicated, if the layout is formed by the above procedure, there is a margin for the gap correction amount. In this case, the new wiring 2 can be added without moving the terminal 1 or the via hole 3 or by changing the layout only by moving the surrounding wiring 2 only on the layer surface where the new wiring is inserted.

In the above embodiment, the layout which is the processing result of each step can be displayed on the display means 4. However, the initial layout is formed by the automatic arrangement / wiring means, and the contents are not displayed. It is also possible to execute steps S11 to S19 and display only the result.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a flowchart showing the overall processing procedure of the compaction method according to the present embodiment. FIGS. 10 and 11 are plan views showing patterns in the processing example of the second embodiment.
(A) shows the initial layout of the printed wiring board. First,
A command to move the terminal 1 or the via hole 3 or to add the terminal 1, the via hole 3 and the wiring 2 of the component is received from the operator to the layout modification specifying means 5. FIG. 10B shows an example in which a via hole B is added to the initial layout. By this command, the modification designation means 5
Updates or newly creates the segment data 14 of the changed layout. The segment data 14 of the terminal 1 and the via hole 3 are the same as those of the first embodiment.
It is created in the data structure of (a). As for the wiring, the segment data 14 and the sub segment data 14 'having the data structures shown in FIGS. 13A and 13B are created. The sub-segment data 14 'in the second embodiment is the same as the segment data 14 in the first embodiment whose data structure is shown in FIG. 5 (b), and is divided by the bend of the wiring and the branch point. Each is a sub-piece. In contrast, the second
In the embodiment, in the segment data 14 of the interconnect, each interconnect is defined as one connected segment up to a branch point, a via hole, or a connection point with a terminal. For example, in FIG. 10A, the lowermost wiring forms one element, and 2 g,
It is divided into three sub-elements, 2h and 2i. FIG.
As shown in (a), the segment data 14 stores the storage address at the head of the sub-segment group included in the segment and the number of sub-segment data. Further, the same moving set number 15 is recorded in the segment data 14 connected to the changed terminal 1 or via hole 3, and the segments with the same moving set number 15 finally move by the same moving amount. The moving set data 22
The data structure shown in FIG. 13C is stored, and the moving set number 15, the moving amount 21, and the maximum limit moving amount 20 in the vertical and horizontal directions are stored. The segment thus changed or added is stored as the start segment (step S
21). In the illustrated example, the via hole B is a starting element.

Next, similarly to step S12 of the first embodiment, the updated segment data 14
Is searched for a segment overlapping above and below, and the segment vertical order data 16 is searched.
[FIG. 5C] is created (step S22). next,
The permissible interval calculating means 9 moves up and down from the changed or added segment of the net structure created by the segment up-down sequence data 16 to search for terminals 1 or via holes 3 existing above and below. Similarly to the step S14 in the example, the upper and lower allowable intervals 10, the left and right allowable intervals 10, and the allowable intervals 10 in the oblique 45-degree direction between the upper and lower via holes 3 or the pieces of the terminal 1 are calculated. 12 (a) shows, in the allowable interval data 11 showing the data structure, the upper unit number, the lower unit number, each allowable interval 10, and the element of the wiring 2 sandwiched between the both ends. Record the strip number. Here, when a new element of the wiring 2 is newly added, the allowable interval data 11 of the terminal 1 or the via hole 3 sandwiching the wiring 2 is created.

If there is existing allowable interval data 11 for inserting the wiring 2 therebetween, the conventional allowable interval 10 is corrected to a value obtained by adding the width of the new wiring 2 and the necessary gap, and The unit number of the new wiring 2 is added to the unit number list of the wiring 2 sandwiched between the pieces, and the allowable interval data 11 is updated.
In the case where the starting element is an added element, if the approaching element does not satisfy the required minimum gap with an adjacent element and approaches, the starting element and the adjacent terminal 1 or the element of the via hole 3 are not connected. The unit number of the wiring 2 included in the allowable interval data 11 is stored as a changed unit. In the case of a changed segment, the segment data 14 of the wiring is stored with the sub-segment data undecided. When the start segment is a moving segment, the element of the wiring 2 included in the allowable interval data 11 between the start segment and the terminal 1 or the segment of the via hole 3 located in the moving direction of the start segment. The segment number is stored as a changed segment. FIG.
When the via hole B is inserted in (b), the wiring between the terminal E and the terminal F, which is sandwiched between the via holes A and B, and the terminal G
The wiring connecting the terminal H and the two wirings sandwiched between the via holes B and C are changed pieces. In FIG. 10B, the wiring 2 stored as the changed element is indicated by a broken line.
Similarly, when the unit moves in the subsequent processing, the unit number of the wiring 2 recorded in the allowable interval data 11 relating to the unit is stored as a changed unit (step S23).

Next, the compaction means 6 within the allowable interval between the component and the via hole selects a processing element of the terminal 1 or the via hole 3 in the following priority order and performs the following processing (step S24). [First selection] (Priority 1) Terminal 1 or via hole 3 of starting element
If there is, select it as a processing element. After the processing as the processing element is completed, the registration of the start element is released.
When the starting segment is the wiring 2, the terminal 1 or the via hole 3 of the allowable interval data 11 containing the starting segment as an element is selected as the processing segment. (Priority 2) If there is a unit for which processing is reserved, select it. After selecting, cancel the processing reservation. Tolerable interval data 11 in which this processing unit is set to the first unit number or the second unit number is extracted, and the other unit recorded together with this processing unit is selected as a neighboring unit. . If the arrangement position of the processing unit is not apart from the neighboring unit in the vertical and horizontal directions by the allowable interval of 10 or more, the position where the processing unit is separated until the allowable interval 10 is satisfied is calculated. Here, when calculating the position of the processing unit, the position of the processing unit is calculated by giving priority to satisfying the allowable interval 10 with the neighboring unit having a higher priority according to the following priority order.

[Second Selection] (Priority 1) Priority is given to satisfying an allowable interval between a position and a designated neighboring segment. For this reason, when the processing unit moves, the movement set data 22 stores the maximum limit movement amount 20 that does not allow the processing unit to approach the neighboring unit any more. (Priority 2) When the processing segment is the start segment, its original position is prioritized. (Priority 3) Priority is given to satisfying the permissible interval with the recently placed neighboring unit. When the movement amount 21 of the movement set data 22 of the neighboring unit is equal to the maximum limit movement amount 20 in the direction away from the processing unit (that is, when the neighboring unit cannot further move away from the processing unit)
In the moving set data 22 of the processing unit, there is a maximum limit movement amount 20 such that the moving unit cannot approach the neighboring unit any longer.
Is stored. (Priority 4) An interval obtained by adding the gap correction amount to the allowable interval 10 with the neighboring unit is satisfied.

Thus, the processing element is moved. And
When a processing unit is moved, another unit belonging to the same moving set is reserved for processing. In addition, a neighboring unit is extracted for each of the moved units, and if the allowable interval 10 is not satisfied with the neighboring unit, the neighboring unit is also reserved for processing. The above is Step S24. After this process, it is determined whether or not there is a start segment or a segment that has been reserved for processing and has not been processed. If there is, the process returns to the beginning of step S24 to continue the process. If there is no segment for which processing is reserved, and the storage of all start segments has already been released, the process proceeds to step S26.

The processing in steps S24 and S25 will be described more specifically with reference to FIG. FIG.
As shown in (b), when the via hole B is added, this becomes the start segment, and therefore, in step S24, the via hole B is selected as the processing segment in the first selection. In this case, the via holes A and C serve as neighboring segments. here,
It is assumed that none of the via holes A, B, and C is a segment whose position is designated, and the position of the terminal D is designated. It is also assumed that the allowable interval 10 between the via holes A and B is not satisfied, and that the via holes B and C have an interval greater than the allowable interval 10 plus the gap correction amount.

In the second selection, the position of the via hole B is prioritized according to the priority order 2, so that the via hole A, which is a neighboring element, becomes a movement candidate and is reserved for processing. Then, the unit of the via hole A for which processing is reserved in step S25 is detected, and the process returns to step S24, and the processing is continued with the via hole A as the processing unit [FIG. 10 (c)]. However, this time, the position of the processing element A is changed to the neighboring element D whose position is specified.
Is given priority (priority order 1), so that it is installed at the position shown in FIG. 10C. Therefore, in order to satisfy the permissible interval 10 between the via holes A and B, a processing reservation is made for the via hole B which has become a neighboring unit. Next, the via hole B for which processing is reserved in step S25 is detected, the process returns to step S24, and processing is performed using the via hole B as a processing element.
As shown in (a), the process moves and reserves a via hole C which is a neighboring element. Then, returning to step S24 again via step S25, if it is found that the via hole C satisfies the allowable interval 10 with the neighboring element, the steps S24 and S25 by the allowable interval compaction unit 6 are performed.
Is completed.

After the positions of the terminal 1 and the via hole 3 have been determined in this way, the flow advances to step S26, where the correction specifying means 5 shifts to a state of waiting for a command from the operator. When the correction designating means 5 receives a command to form wiring from the operator, the rewiring means 8
And the process of step S26 is executed. In step S26, the following processing is performed for each of the segments of the wiring 2 stored as the changed segments as a processing segment. The allowable interval data 11 which records the processing element of the wiring 2 is extracted, and the interval between the wiring 2 of the processing element and the terminal 1 or the via hole 3 of the processing element or the sub-element of the wiring whose position is determined is determined. Calculate the sum of the width of the wiring 2 and the required minimum gap and the sum of the radius of the terminal 1 or the via hole 3 or the radius of the wiring sub-fragment from the terminal 1 or the via hole 3 or the wiring sub-fragment. The allowable interval to the wiring 2 is 10. This allowable interval 10 is the upper and lower allowable interval 1
0, left and right allowable interval 10, and oblique 45 degree direction allowable interval 1
0. Then, these unit numbers or sub-unit numbers and the allowable interval 10 up to the wiring 2 are recorded in the wiring neighborhood data 24 whose data structure is shown in FIG. FIG.
The area within the allowable interval 10 of the wiring neighboring data 24 of the wiring 2 connecting the terminal E and the terminal F is shown by a broken line in FIG.

Next, like the wiring 2 connecting the terminals E and F in FIG.
At a position separated from the element by a distance of 10 or more. Thereby, the sub-segment of the segment data 14 of the wiring 2 is determined. As described above, the wiring 2 is provided with a margin of the width and the gap of the unprocessed wiring 2 to determine the wiring path.
In the case (c), when the route of the wiring 2 connecting the terminal G and the terminal H is searched, the possibility of the wiring 2 can be guaranteed. The above is Step S26. As described above, in this embodiment, when the operator adds or moves the terminal 1 or the via hole 3 with the correction designating means 5, the related terminal 1 is set so that the interval between the terminal 1 and the via hole 3 becomes the allowable interval 10 or more. And the via hole 3 is automatically moved. In addition, since the segments are arranged at the allowable interval of 10 or more in this manner, it is possible to maintain an interval at which the arranged segments do not hinder the later formation of wiring.

In this embodiment, the wiring lower limit position data 23 becomes unnecessary, so that the capacity of the storage device can be reduced in the present invention, and the processing time can be shortened since it is not necessary to use the wiring compaction means 7 for producing it. Further, since the arrangement position of the unit is calculated only when the arrangement position of the unit interferes with another unit, the processing time for calculating the arrangement position of the unit can be reduced. Then, by limiting the segment whose position is to be changed and partially changing the arrangement without changing the position of the other segments, the number of positions changed can be reduced, the processing time can be further reduced, and the wiring shape can be reduced. There is an advantage that the modification of the data of the result of the transmission line simulator and the result of the noise simulator can be reduced.

In the present embodiment, after reaching the step S26 via the step S25, an instruction for wiring formation from the operator is waited. However, the instruction from the operator in the step S26 is sent from the automatic wiring means. After the confirmation in step S25, the process proceeds to step S26, and the wiring process can be automatically performed. Also,
In the present invention, the via hole may penetrate all layers of the printed wiring board, or may partially penetrate it. Further, in the embodiments, the printed wiring board has been described, but the present invention is not limited to this, and can be applied to a semiconductor integrated circuit. in this case,
The terminals correspond to the terminals provided in the cell or the block.

[0038]

As described above, the graphic layout compressing apparatus and method of the present invention compact the terminals and wirings by compaction processing, and at the same time, if possible, reduce the gap between the terminal and the via hole by the gap correction amount. Therefore, there is a high possibility that there is an allowance for wiring between the wirings when the wirings are corrected later, and a layout with good correctionability can be designed later.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a graphic layout compression apparatus according to the present invention.

FIG. 2 is a flowchart showing a processing procedure according to the first embodiment of the present invention.

FIG. 3 is a plan view (part 1) showing a picture in a processing example according to the first embodiment of the present invention;

FIG. 4 is a plan view (part 2) showing a picture in a processing example according to the first embodiment of the present invention;

FIG. 5 is a diagram showing a data structure according to the embodiment of the present invention.

FIG. 6 is a plan view showing an allowable interval calculated in the embodiment of the present invention.

FIG. 7 is a view showing a data structure of terminal vertical order data in the embodiment of the present invention.

FIG. 8 is a plan view showing a movement amount and a maximum limit movement amount used in the embodiment of the present invention.

FIG. 9 is a flowchart showing a processing procedure according to a second embodiment of the present invention.

FIG. 10 is a plan view showing a picture in a processing example according to the second embodiment of the present invention (part 1);

FIG. 11 is a plan view (part 2) showing a picture in a processing example according to the second embodiment of the present invention;

FIG. 12 is a diagram showing a data structure according to a second embodiment of the present invention.

FIG. 13 is a diagram showing a data structure according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Terminal 2 Wiring 3 Via hole 4 Display means 5 Layout modification designation means 6 Compaction means within the allowable interval of component terminals and via holes 7 Wire compaction means 8 Rewiring means 9 Allowable interval calculation means of component terminals and via holes 10 Allowable interval 11 Component terminals And allowable distance data of via holes 12 Layout data 13 Layout data of component terminals and via holes 14 Element data 14 'Sub-element data 15 Moving set number 16 Element vertical order data 16' Element horizontal order data 17 Vertical order of element Data 18 Terminal / via hole vertical order data 19 Relative limit movement amount 20 Maximum limit movement amount 21 Movement amount 22 Moving set data 23 Wiring lower limit position data 24 Wiring neighborhood data

Claims (3)

[Claims] 1. A graphic layout compression apparatus for compacting a pattern of one or more layers having a wiring, a terminal and a via hole, wherein a layout correction instruction is given, and the wiring, the terminal and the via hole are decomposed into pieces to obtain a whole piece. Layout modification designating means for creating top and bottom and left and right order data, and calculating the top and bottom and left and right order of all segments, creating their order data, and the allowable spacing between terminals and via holes and neighboring terminals and via holes Allowable interval calculating means for calculating, and the terminal and via holes are shifted down or up, moved or arranged left or right, and the allowable interval compaction means for re-arranging the terminals and via holes at a sufficient interval,
Wiring compaction means for arranging wiring in a left or right-justified or left-justified manner, re-wiring means for arranging wiring at a position more than an allowable distance from a neighboring element, and layout data storage means for storing layout data A graphic layout compression apparatus, comprising: an allowable interval data storage unit for storing an allowable interval between terminals and via holes. 2. A graphic layout compression method for compacting a pattern of one or more layers having wirings, terminals and via holes, the method comprising decomposing wirings, terminals and via holes in input layout data into fragments. The process of creating upper and lower and left and right order data of all segments, the process of creating upper and lower and left and right order data of all segments, and calculating the allowable interval between terminals and via holes and its neighboring terminals and via holes, The process of moving the terminals and via holes to the left or right with justification at the allowable interval determined in the previous process and moving them to the left or right, and if possible, the width of the extra terminals and via holes for one wiring The process of rearranging with a margin for the amount of gap correction to be made, and laying the wiring down or up, laying out left or right, and storing the position as wiring limit position data And the wiring so as to have the shortest distance in the space between the position at an allowable distance from the element existing on the opposite side to the wiring packing direction and the wiring position stored as the wiring limit position data. The process of placing
A graphic layout compression method comprising: 3. A graphic layout compression method for compacting a pattern of one or more layers having wiring, terminals and via holes, wherein the wiring, terminals and via holes in the layout data are decomposed into pieces and stored, and the position is changed. Or the process of storing the added terminal and via hole segments as the starting segment, the process of creating the top and bottom and left and right order data of all the segments based on the updated layout data, and the process of storing the terminal and via holes and the vicinity thereof. The process of calculating the allowable interval between the terminal and the via hole, and the starting element and the element that has been moved due to the provision of the starting element, at least the allowable interval between the neighboring terminal and the via hole. If it can be separated, an interval obtained by adding a gap correction amount aiming at a width through which one extra wiring can be passed to the allowable interval. And a step of arranging the wiring at a position more than an allowable distance from a neighboring element, and a method of compressing the graphic layout.