JPH0990418A - Thin-film transistor, its production and liquid crystal display element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device with which the insulation between gate electrodes and non-single crystalline silicon films is ensured by simple constitution. SOLUTION: Display pixel electrodes 3, source electrodes 4 and drain electrodes 5 are formed on a glass substrate 1. An amorphous silicon, silicon nitride film 11, silicon oxynitride film 12 and silicon nitride film 13 are formed by a plasma CVD method. The gate electrodes 17 of an aluminum film 15 and a molybdenum film 16 are formed by etching. The silicon nitride film 13 of a high etching rate is etched by plasma etching of a gaseous mixture composed of CF4 and oxygen with the gate electrodes 17 as a mask and the etching is stopped by the silicon oxynitride film 12 of the low etching rate. Phosphorus hydride is doped without mass sepn. into the amorphous silicon film in a self- alignment manner with the gate electrodes 17 as a mask. The non-single crystal silicon film is irradiation in the self-alignment manner with the gate electrodes 17 as a mask, by which the amorphous silicon thereof is crystallized to the polycrystal silicon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a top gate type thin film transistor, a method of manufacturing the same, and a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, along with the increase in size of liquid crystal display devices, there has been a demand for lowering the resistance of gate lines formed together with gate electrodes and reducing the number of masks for improving productivity. A top gate type thin film transistor is used.

In this thin film transistor of the forward staggered structure, a source electrode and a drain electrode are formed on an insulating substrate, a non-single crystal silicon film is formed so as to cover the source electrode and the drain electrode, and the non-single crystal silicon film is formed. A gate insulating film is formed on the gate insulating film, and a gate electrode is laminated on the gate insulating film.

[0004]

In the case of this forward staggered thin film transistor, if the gate electrode and the gate insulating film are formed in a pattern different from that of the non-single-crystal silicon, the gate insulating film and the non-single-crystal silicon are selected. It is extremely difficult to use non-single-crystal silicon and a material that is difficult to selectively etch as a gate insulating film for the gate insulating film, especially when patterning by fluorine-based dry etching. It is difficult to use a silicon nitride film having an excellent insulating property for the film.

Further, in manufacturing, when the ohmic contact portion is self-aligned with the gate electrode by ion doping and laser annealing with the non-single-crystal silicon film in the uppermost layer, the non-single crystal film with reduced resistance is used. The crystalline silicon film and the gate electrode may come into contact with each other to cause a short circuit.

Further, when the non-single-crystal silicon film is polycrystallized by laser annealing, a laser having a considerable energy density is required, and multistage irradiation may be necessary for uniform crystallization. A problem occurs in terms of throughput.

Furthermore, when the gate insulating film is patterned by wet etching, side etching largely enters under the gate electrode, so that wet etching has an unfavorable problem.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a thin film transistor in which insulation between a gate electrode and a non-single-crystal silicon film is ensured with a simple structure, a manufacturing method thereof, and a liquid crystal display element. To aim.

[0009]

According to the present invention, there are provided a source electrode and a drain electrode formed on an insulating substrate, a non-single-crystal silicon film covering the source electrode and the drain electrode, and a source electrode and a drain electrode. And a gate insulating film formed between the non-single-crystal silicon film and the gate electrode, the first insulating film having a different etching rate from each other. The first insulating film includes a laminated film of a second insulating film
The insulating film is arranged on the non-single-crystal silicon film side so as to cover the non-single-crystal silicon film, and the second insulating film is formed at a position corresponding to the gate electrode on the first insulating film. Consists of two or more types with different etching rates,
By stopping the etching at the portion where the etching rate of the gate insulating film is slow, a part of the gate insulating film is left on the non-single-crystal silicon film having no gate electrode on the upper part, and the non-single-crystal film under the gate insulating film is left. It is possible to avoid etching into the crystalline silicon film and prevent a short circuit due to contact between the source contact region and the drain contact region and the gate electrode.

Further, according to the present invention, a step of forming a source electrode and a drain electrode on an insulating substrate, a step of forming a non-single-crystal silicon film so as to cover the source electrode and the drain electrode, and the non-single-crystal silicon. Forming a gate insulating film composed of a laminated film of a first insulating film and a second insulating film having different etching rates on the film, and corresponding to the upper part between the source electrode and the drain electrode on the gate insulating film. The method includes a step of forming a gate electrode at a position and a step of etching the first insulating film in the gate insulating film and leaving the second insulating film with the gate electrode as a mask. Different 2
The gate insulating film is composed of more than one type, and the etching is stopped at the part where the gate insulating film has a slow etching rate, so that a part of the gate insulating film is left on the non-single-crystal silicon film without the gate electrode on the upper part. It is possible to avoid etching on the underlying non-single-crystal silicon film, and to prevent a short circuit due to contact between the source contact region and the drain contact region and the gate electrode.

Further, according to the present invention, a step of doping impurities into the non-single-crystal silicon layer by ion implantation using the gate electrode as a mask, and a non-single-crystal silicon layer by irradiating a laser beam with the gate electrode as a mask. Forming a part of the layer into a polycrystalline silicon layer.

Further, according to the present invention, a step of irradiating a laser beam with the gate electrode as a mask to form a part of the non-single-crystal silicon layer into a polycrystalline silicon layer, and ion implantation with the gate electrode as a mask Doping the polycrystalline silicon layer with impurities.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to an active matrix type liquid crystal display element shown in the drawings.

In FIG. 1, reference numeral 1 is a glass substrate as an insulating substrate, and a transparent conductive film 2 of indium tin oxide is formed on one main surface of the glass substrate 1, and this transparent conductive film 2 is formed. A part of each of the pixels forms a display pixel electrode 3 arranged in a matrix. In addition, molybdenum (M) is formed on the transparent conductive film 2 continuous with the display pixel electrode 3.
o). A source electrode 4 of tungsten (W) alloy is formed, and a drain electrode 5 connected to, for example, a signal wiring (not shown) is formed on the side not having the display pixel electrode 3.

A non-single-crystal silicon film 6 of amorphous silicon as a semiconductor film is formed on the source electrode 4 and the drain electrode 5, and the non-single-crystal silicon film 6 is formed.
Source electrode 4 or drain electrode 5 on both sides of
A polycrystalline silicon film 7 as a semiconductor film for forming a source contact region of polycrystalline silicon and a polycrystalline silicon film 8 as a semiconductor film for forming a drain contact region are formed.

On the non-single-crystal silicon film 6 and the polycrystalline silicon films 7 and 8, silicon nitride films 11 and 5 having a thickness of 10 nm are formed as a first insulating film of a gate insulating film.
a silicon oxynitride film 12 having a thickness of
A silicon nitride film 13 having a thickness of 300 nm is formed as a second insulating film on the non-single-crystal silicon film 6 on the silicon oxynitride film 12, and these silicon nitride film 11, silicon oxynitride film 12 and A gate insulating film 14 is formed of the silicon nitride film 13.

Further, on the silicon nitride film 13, an aluminum film 15 of aluminum (Al) and molybdenum (M) are formed.
The molybdenum film 16 of o) is laminated and formed, the gate electrode 17 integrated with the scanning line (not shown) is formed, and these form the thin film transistors 18 arranged in a matrix corresponding to the display pixel electrodes 3. . The width of the gate electrode 17 is narrower than the width of the source electrode 4 and the drain electrode 5, and the parasitic capacitance between the source electrode 4 and the gate electrode 17 and between the drain electrode 5 and the gate electrode 17 is reduced, and the thin film transistor 18 It enables high speed operation. Further, since the source electrode 4 and the drain electrode 5 and the gate electrode 17 do not overlap with each other, the contact resistance can be reduced by using a low resistance material such as the polycrystalline silicon films 7 and 8 in the portion where the gate electrode 17 is absent.

Then, a protective film 19 of a silicon nitride film is formed so as to cover the thin film transistor 18 and the whole, and a matrix array substrate 20 is formed.

On the other hand, a counter electrode 26 made of ITO or the like is formed on one main surface of a glass substrate 25 as an insulating substrate to form a counter substrate 27.

Polyimide films 31 and 32 are formed on the facing surfaces of the matrix array substrate 20 and the facing substrate 27,
The polarizing plates 33 and 34 are attached to the opposite surfaces, the matrix array substrate 20 and the counter substrate 27 are attached to face each other, and the liquid crystal 35 is sandwiched and sealed to form a liquid crystal display device.

Next, the manufacturing method of the above embodiment will be described.

First, a transparent conductive film of ITO and a molybdenum-tungsten alloy are laminated and formed on one main surface of the glass substrate 1 and etched by photolithography to be integrated with the display pixel electrode 3 and the display pixel electrode 3. The source electrode 4 and the drain electrode 5 are formed.

Next, the non-single-crystal silicon film 6 and the polycrystalline silicon films 7 and 8 are formed so as to cover the source electrode 4 and the drain electrode 5, and amorphous silicon having a film thickness of 100 nm and the gate insulating film 14 are formed. A silicon nitride film 11 having a film thickness of 10 nm, a silicon oxynitride film 12 having a film thickness of 5 nm, and a silicon nitride film 13 having a film thickness of 300 nm are sequentially formed by a plasma CVD method in this order. In addition, plasma CVD
By continuously forming without breaking the vacuum system, the interface state between the non-single crystal silicon film 6 and the gate insulating film 14 is improved, and the characteristics are also improved.

Subsequently, aluminum and molybdenum are laminated, and the gate electrode 17 having the aluminum film 15 and the molybdenum film 16 laminated is formed by etching by photolithography. At this time, the width of the gate electrode 17 is narrower than the width of the source electrode 4 and the drain electrode 5, and the offset structure is formed.

Subsequently, the silicon nitride film 13 having a high etching rate is etched in the same pattern as the gate electrode 17 by, for example, plasma etching using a gas mixture of CF ₄ and oxygen to obtain an etching rate of a high oxygen content. The slow silicon oxynitride film 12 stops the etching. That is, in the case of fluorine-based dry etching, the larger the oxygen / nitrogen ratio, the slower the etching rate, and the selective etching ratio between the silicon oxynitride 12 and the silicon nitride film 13 is 1
Close to 00, which is sufficient to stop the etching. Further, while red light emission is observed when the silicon nitride film 13 is dry-etched with a fluorine-based compound, no light emission is observed during dry etching of the silicon oxynitride film 12, which is observed when the silicon nitride film 13 is etched. By monitoring the red emission, the end point of etching can be easily identified. And the gate electrode 17
Silicon nitride film 11 is formed on the amorphous silicon film where there is no
And the silicon oxynitride film 12 is left. That is, it is effective when it is difficult to selectively etch the gate insulating film 17 and the non-single crystal silicon film 6.

Subsequently, with the silicon nitride film 11 and the silicon oxynitride film 12 left on the amorphous silicon film in the portion where the gate electrode 17 is not present, the gate electrode 17 is used as a mask in a self-aligned manner. The amorphous silicon film is doped with phosphorus hydride without mass separation. In this case, since the silicon nitride film 11 and the silicon oxynitride film 12 are present on the upper layer portion of the non-single-crystal silicon film, it is preferable to drive with an acceleration voltage as high as possible. Further, the accelerating voltage depends on the film thickness of the silicon nitride film 11 and the silicon oxynitride film 12 on the amorphous silicon film or the non-single crystal silicon film, but is, for example, 30 to 60.
It is about kV.

Next, an excimer laser using XeCl or the like is irradiated in a self-aligned manner using the gate electrode 17 as a mask,
Amorphous silicon of the non-single crystal silicon film is converted to polycrystalline silicon. At this time, the silicon nitride film 11 and the silicon oxynitride film 12 are present on the non-single-crystal silicon film, and since these films have a lower surface reflectance for excimer laser light than amorphous silicon, Since it is difficult to reflect light and the absorption efficiency is increased, amorphous silicon can be converted into polycrystalline silicon with high efficiency. Therefore, the amorphous silicon can be crystallized at an energy density about half that of a laser for converting the amorphous silicon into polycrystalline silicon, and the throughput is improved. It is also desirable to overlap and strike 50% or more of the beam width in order to improve the distribution of crystallization.

Further, the silicon nitride film 11 and the silicon oxynitride film 12 prevent short circuit between the gate electrode 17 and the low resistance polycrystalline silicon films 7 and 8.

Next, the polycrystalline silicon films 7 and 8 are etched by photolithography to form a source contact region and a drain contact region.

Further, the whole is covered with a protective film 19 such as a silicon nitride film, and molybdenum / tungsten on the peripheral electrode portion and the display pixel electrode 3 is removed by etching by photolithography.

Further, a counter electrode 26 is formed on one main surface of the glass substrate 25 to form a counter substrate 27.

Then, the polyimide films 31 and 32 are formed on the facing surfaces of the matrix array substrate 20 and the counter substrate 27, and the deflection plates 33 and 34 are adhered to the opposite surfaces thereof.
Further, the counter substrate 27 is opposed to and adhered to the liquid crystal 35 so as to be sandwiched and sealed to form a liquid crystal display device.

The insulating substrate is not limited to one having an insulating property in the substrate itself, and the same effect can be obtained by using any substrate having an insulating film formed thereon.

Further, the film thickness of the laminated film composed of the silicon oxynitride film 12 and the silicon nitride film 11 is set to 50 nm or less and the film thickness of the silicon nitride film 11 is set to 20 nm or less, so that the ion doping process can be performed. At this time, processing can be performed at a low accelerating voltage, and hydrogen degassing from the non-single-crystal silicon film can be facilitated by thinning the silicon nitride film 11 in the laser annealing process, and the throughput and the process margin can be expanded.

Further, the same effect can be obtained by forming the silicon oxynitride film 12 with a silicon oxide film or a laminated film of a silicon oxynitride film and a silicon oxide film.

Furthermore, in the above embodiment, ion doping is performed before laser irradiation, but the same effect can be obtained by performing laser irradiation after performing ion doping.

According to the above embodiment, the yield improvement,
A liquid crystal display device with high productivity can be manufactured.

[0038]

According to the present invention, the gate insulating film is composed of two or more kinds having different etching rates, and the etching is stopped at a portion of the gate insulating film having a slow etching rate, so that there is no gate electrode above. A part of the gate insulating film can be left on the single crystal silicon film to avoid etching to the non-single crystal silicon film below the gate insulating film, and to prevent the source and drain contact regions and the gate electrode from being etched. It is possible to prevent a short circuit due to the contact of.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a liquid crystal display device according to an embodiment of the present invention.

[Explanation of symbols]

 1 glass substrate as an insulating substrate 4 source electrode 5 drain electrode 6 non-single-crystal silicon film 7, 8 polycrystalline silicon film 11 silicon nitride film 12 silicon oxynitride film 14 gate insulating film 17 gate electrode 18 thin film transistor 20 array substrate 27 counter substrate 35 LCD

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/78 627G (72) Inventor Kaichi Fukuda 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Toshiba Yokohama Office

Claims (13)

[Claims] 1. A source electrode and a drain electrode formed on an insulating substrate, a non-single-crystal silicon film covering the source electrode and the drain electrode, and a position corresponding to an upper portion between the source electrode and the drain electrode. And a gate insulating film formed between the non-single-crystal silicon film and the gate electrode, the gate insulating film having a different etching rate from each other.
It is composed of a laminated film of an insulating film and a second insulating film, the first insulating film is arranged on the non-single crystalline silicon film side so as to cover the non-single crystalline silicon film, and the second insulating film is a gate electrode on the first insulating film. A thin film transistor, which is formed at a position corresponding to. 2. The source region and the drain region of the non-single crystal silicon film are composed of polycrystalline silicon doped with impurity ions, and the distance between the source electrode and the drain electrode is wider than the width of the gate electrode. The thin film transistor according to claim 1. 3. The gate insulating film comprises any one of a silicon nitride film, a silicon oxynitride film, and a silicon oxide film, and the oxygen / nitrogen composition ratio of the first insulating film in the gate insulating film is the second insulating film. The thin film transistor according to claim 1 or 2, wherein the oxygen / nitrogen composition ratio of the film is larger than that of the film. 4. The first insulating film is composed of a laminated film of a silicon nitride film and a silicon oxynitride film or a laminated film of a silicon nitride film and a silicon oxide film,
4. The thin film transistor according to claim 1, wherein the laminated film has a thickness of 50 nm or less and the silicon nitride film has a thickness of 20 nm or less. 5. The first insulating film comprises a laminated film of a silicon nitride film and a silicon oxynitride film or a laminated film of a silicon nitride film and a silicon oxide film, and the second insulating film comprises a silicon nitride film. 5. The thin film transistor according to claim 1, wherein the thin film transistor is a thin film transistor. 6. A step of forming a source electrode and a drain electrode on an insulating substrate, a step of forming a non-single-crystal silicon film so as to cover the source electrode and the drain electrode, and mutually forming on the non-single-crystal silicon film. A step of forming a gate insulating film composed of a laminated film of a first insulating film and a second insulating film having different etching rates; and a gate electrode at a position above the source electrode and the drain electrode on the gate insulating film. Forming a gate insulating film using the gate electrode as a mask;
And a step of leaving the second insulating film remaining by etching the insulating film. 7. A step of forming a source electrode and a drain electrode on an insulating substrate, a step of forming a non-single-crystal silicon film so as to cover the source electrode and the drain electrode, and a step of mutually forming on the non-single-crystal silicon film. A step of forming a gate insulating film composed of a laminated film of a first insulating film and a second insulating film having different etching rates; and a gate electrode at a position above the source electrode and the drain electrode on the gate insulating film. Forming a gate insulating film using the gate electrode as a mask;
A step of etching the insulating film to leave a second insulating film; a step of doping impurities into the non-single-crystal silicon layer by ion implantation using the gate electrode as a mask; and a laser beam irradiation using the gate electrode as a mask. And a step of forming a part of the non-single-crystal silicon layer into a polycrystalline silicon layer. 8. A step of forming a source electrode and a drain electrode on an insulating substrate, a step of forming a non-single-crystal silicon film so as to cover the source electrode and the drain electrode, and a step of mutually forming on the non-single-crystal silicon film. A step of forming a gate insulating film composed of a laminated film of a first insulating film and a second insulating film having different etching rates; and a gate electrode at a position above the source electrode and the drain electrode on the gate insulating film. Forming a gate insulating film using the gate electrode as a mask;
A step of etching the insulating film to leave the second insulating film; a step of irradiating a laser beam with the gate electrode as a mask to turn a part of the non-single-crystal silicon layer into a polycrystalline silicon layer; And a step of doping the polycrystalline silicon layer with impurities by ion implantation as a mask. 9. The step of forming a non-single crystal silicon film comprises:
9. The amorphous silicon is formed by plasma CVD, and the step of forming the first insulating film in contact with the amorphous silicon film is performed by forming a silicon nitride film by plasma CVD. A method for manufacturing the thin film transistor described. 10. The first insulating film is formed of a laminated film of a silicon nitride film and a silicon oxynitride film or a laminated film of a silicon nitride film and a silicon oxide film, and the laminated film has a thickness of 50 n.
9. The method of manufacturing a thin film transistor according to claim 6, wherein the thickness of the silicon nitride film is m or less and the film thickness is 20 nm or less. 11. The gate insulating film comprises any one of a silicon nitride film, a silicon oxynitride film, and a silicon oxide film, and the oxygen / nitrogen composition ratio of the first insulating film in the gate insulating film is the second insulating film. 9. The method of manufacturing a thin film transistor according to claim 6, wherein the oxygen / nitrogen composition ratio of the film is made larger and the fluorine-based dry etching is performed. 12. The first insulating film is formed of a laminated film of a silicon nitride film and a silicon oxynitride film or a laminated film of a silicon nitride film and a silicon oxide film, and the second insulating film is formed of a silicon nitride film. 12. The method of manufacturing a thin film transistor according to claim 6, wherein the dry etching is performed with a fluorine system. 13. An array substrate on which the thin film transistor according to claim 1 is formed, a counter substrate provided so as to face the array substrate, and a liquid crystal disposed between the array substrate and the counter substrate. A liquid crystal display device characterized by being provided.