JPH098653A - Device and method for detecting phase - Google Patents

Abstract

PURPOSE: To reduce jitter at a phase detector and to improve reliability. CONSTITUTION: From a phase comparator 1, an input signal inputted there and an error signal proportional to the phase difference of an input signal from a VCO 3 are outputted and supplied to an APL 11. Based on the error signal from the phase comparator 1 and an output signal from a loop filter 2, among the error signals inputted from the phase comparator 1, only the error signal in a prescribed reference range is selectively outputted to the loop filter 2 by the APL. The VCO 3 outputs the signal of a frequency corresponding to the input signal from the loop filter 2 and supplies that signal to the phase comparator 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase detecting apparatus and method, for example, a phase detecting apparatus and method suitable for use in an external clock type recording apparatus and the like.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional digital phase lock loop (DPLL).
It is a block diagram which shows the structure of an example of (d Loop).
The phase comparator 1 outputs an error voltage proportional to the phase difference between the two input signals. The loop filter 2 blocks high-frequency signals of the input signal, passes only low-frequency signals, and selectively passes only signal components to be traced by the DPLL. Voltage Controlled Oscillator (VCO: Voltage Control)
ed Oscillator) 3 is a loop filter 2
It oscillates at a predetermined frequency on the basis of a signal (control voltage) supplied from the device.

When the input signal and the output signal from the VCO 3 are input to the phase comparator 1, an error voltage corresponding to the phase difference between those signals is output. The output error voltage is supplied to the loop filter 2, where only the component to be tracked by the DPLL is selectively passed and supplied to the VCO 3 as a control voltage. Therefore, unwanted components such as noise will be removed. Next, VC
O3 generates and outputs a signal having a predetermined frequency based on the control voltage supplied thereto.

The DPLL is the frequency of the input signal and the VCO3.
When the oscillating frequency is different, the VCO 3 operates so that the oscillating frequency matches the frequency of the input signal. Then, finally, the frequencies of these signals coincide with each other and become a steady state (lock).

[0005]

However, in a real DPLL, it is not possible to remove all the unwanted components of the input signal, and the unwanted residual components pass through, so the output signal of the DPLL should be followed. There is a problem that jitter occurs around a signal, and if this jitter is too large, the DPLL synchronization may be lost.

The present invention has been made in view of such a situation, and detects an abnormal change in the error signal from the phase comparator and removes this error signal to pass an unwanted component of the input signal. It is possible to suppress the noise, reduce the jitter, and improve the reliability.

[0007]

According to a first aspect of the present invention, there is provided a phase detection device including a DPLL for detecting the phase of a reproduced waveform of a clock mark which is a timing reference. Determination means for determining whether or not the phase detection result of is an abnormal value,
When the determination means determines that the phase detection result is an abnormal value, the phase detection result is replaced with a calculation value calculated based on the past phase detection result.

A storage means for storing the past phase detection result and a calculation means for calculating the calculated value by a predetermined method based on the past phase detection result stored by the storage means may be further provided. it can.

The replacing means may replace the phase detection result with a calculated value when the DPLL is in a locked state.

According to a fourth aspect of the present invention, there is provided a phase detection method comprising a DPLL for detecting a phase of a reproduced waveform of a clock mark which is a timing reference. If the phase detection result is determined to be an abnormal value, the phase detection result is replaced with a predetermined calculation value calculated based on the past phase detection result. .

When the DPLL is in the locked state, the phase detection result can be replaced by the calculated value.

[0012]

In the phase detector according to the present invention, the judging means judges whether or not the phase detection result of the reproduced waveform of the predetermined clock mark is an abnormal value, and the judging means determines the phase detection result. When is determined to be an abnormal value, the replacement unit replaces the phase detection result with a predetermined calculation value calculated based on the past phase detection result. Therefore, the abnormal phase detection result can be removed.

In the phase detection method according to the fourth aspect, it is determined whether or not the phase detection result of the reproduced waveform of the predetermined clock mark is an abnormal value, and the phase detection result is determined to be an abnormal value. In this case, the phase detection result is replaced with a predetermined calculation value calculated based on the past phase detection results. Therefore, the abnormal phase detection result can be removed.

[0014]

1 is a block diagram showing the configuration of an embodiment of a digital phase locked loop (DPLL) applied to a phase detection device of the present invention. In this example, FIG.
In the conventional embodiment shown in FIG. 1, an adaptive phase limiter (APL: Ad) is provided between the phase comparator 1 and the loop filter 2.
The active phase limiter 11 is provided. The APL 11 detects an abnormal change in the error voltage supplied from the phase comparator 1 and cancels it.

The other structure and operation are basically the same as those of the conventional case, and the description thereof will be omitted.

FIG. 2 is a block diagram showing the detailed structure of the APL 11. The comparator 21 (determination means) is composed of, for example, a logic circuit, and the error voltage (phs [kT] (where kT is time (t) (t = kT), k = kT), which is output from the phase comparator 1. Integer, T represents the update cycle of the error voltage)) and the VCO from the loop filter 2
When the control voltage (vco (t)) for 3 is input,
Based on these, a predetermined signal (out) is output.

The controller 22 inputs a signal (out) from the comparator 21 and a signal (locked) from an external circuit (DPLL lock detector) (not shown), and in response to them, a predetermined select signal (sel_con).
Is output.

The selector 23 (replacement means) has an error voltage (phs [kT]) from the phase comparator 1 and an output signal (phs_bup) from an adder 26 (arithmetic means) described later.
[KT]) is input, and the signal phs [k] based on the select signal (sel_con) from the controller 22.
T] or the signal phs_bup [kT] is selectively output as the output signal phsc [kT].

The storage element 24a (storage means) stores the output signal phsc [kT] from the selector 23 and stores it for a time T.
Output signal phsc from the selector 23
It is designed to hold until [kT] is supplied. The output signal phsc [kT] is
It is represented as phsc [(k-1) T].

The next output signal phsc from the selector 23
When [kT] is supplied, it is stored, and the signal phsc [(k-1) T] held up to then is supplied to the multiplier 25a (arithmetic means) and the memory element 24b (memory means). ) Also supplies.

The memory element 24b stores the signal phsc [(k-1) T] supplied from the memory element 24a, and after a lapse of time T, the next signal phsc from the memory element 24a is stored.
Hold until [(k-2) T] is supplied. After a lapse of time T, the signal phsc [(k-
2) When T] is supplied, store it.

After a lapse of time T, the storage element 24a supplies the held signal phs [(k-1) T] to the multiplier 25a and also to the storage element 24b. When the signal phs [(k-1) T] from the memory element 24a is supplied, the memory element 24b multiplies the signal phsc [(k-2) T] held until then by the multiplier 25.
b (calculation means).

The multiplier 25a, the signal phsc from the storage element 24a [(k-1) T ] to multiply a predetermined coefficient a _1, and outputs. The multiplier 25b is configured to multiply the signal phsc [(k-2) T] from the storage element 24b by a predetermined coefficient a ₂ and output it.

The adder 26 adds the multiplication result from the multiplier 25a, a ₁ × phsc [(k-1) T], and the multiplier 25b.
The result of multiplication from a is added with a ₂ × phsc [(k−2) T] and output as a signal phs_bup [kT].

Next, the operation will be described. When the error voltage (phs [kT]) output from the phase comparator 1 and the output signal (vco (t)) from the loop filter 2 are input to the comparator 21, the comparator 21
Is the error voltage (phs [kT]) and the output signal ((1 / (Lpf
_Gain)) × vco [kT]), and if the two values are too different, that is, if the condition expressed by the following equation 1 is satisfied, the value of the error voltage (phs [kT]) is For example, the signal (out) corresponding to the value 1 is output to the controller 22. For example, if there is a noise burst, or if the medium is defective,
The error voltage shows an abnormal value.

| Phs [kT] − (1 / (Lpf_gain)) × vco [kT] | ≧ Rng (Equation 1)

In equation 1, the constant Lpf_gain is
By the scaling based on it, the signal vco [k
T] is the loop filter DC gain such that it is brought back to the level of the error voltage, and the constant Rng is the limit value of the predetermined range selected by the designer.

When the condition of Expression 1 is satisfied, that is, when the value of the error voltage (phs [kT]) is determined to be abnormal, the comparator 21 outputs a signal (out) corresponding to the value 1, for example. When it is output and the condition of Expression 1 is not satisfied, that is, when the condition of Expression 2 is satisfied and the value of the error voltage is determined to be normal, the error voltage (phs
The value of [kT]) is considered to be normal, and for example, a signal (out) corresponding to the value 0 is output and supplied to the controller 22.

| Phs [kT] − (1 / (Lpf_gain)) × vco [kT] | <Rng (Equation 2)

In the controller 22, a select signal (sel_co) for controlling the selector 23 based on the output signal (out) from the comparator 21 and the output signal (locked) from the DPLL lock detector.
n) is generated and supplied to the selector 23. here,
Output signal (locked) from the DPLL lock detector
Captures when the DPLL is not locked (Captur
In the e) mode, the digital signal corresponding to the value 0 is set, and the tracking (Track) with the DPLL locked.
ing) mode, it is a digital signal corresponding to the value 1.

The value of the select signal (sel_con) is
It is expressed by the following equation.

Sel_con = locked AND out (Equation 3)

That is, the controller 22 is composed of a logic circuit, and has a signal (locked) and a signal (out).
Are both digital signals corresponding to the value 1,
The select signal (sel_con) corresponding to the value 1 is output. In other cases, the select signal (s
el_con) is output.

Output signal from the DPLL lock detector (l
ocked) is a digital signal corresponding to the value 0 (capture mode), the APL 11 is in the idle state,
The input signal phs from the phase comparator 1 is output as it is as an output signal phsc. That is, the controller 2
When the digital signal (locked) corresponding to the value 0 is input to 2, the controller 22 generates the select signal (sel_con) corresponding to the value 0 from Expression 3, and supplies the select signal (sel_con) to the selector 23.

Select signal (sel_c
The selector 23 supplied with (on) outputs the input signal (phs [kT]) from the phase comparator 1 as it is as an output signal phsc [(k + 1) T] at a predetermined timing.

Therefore, in this case, the time t of the APL 11
The relationship between the input signal at (= kT) and the output signal at time (t + T) after the elapse of the time (T) for the error voltage update period is represented by the following Expression 4.

Phsc [(k + 1) T] = phs [kT] (where locked = 0) (Equation 4)

On the other hand, when the output signal (locked) from the DPLL lock detector is a digital signal corresponding to the value 1 (tracking mode), the APL 11 is in the active state. At this time, when it is determined that the error voltage (phs [kT]) input from the phase comparator 1 is abnormal, that is, when the value of the input signal (out) from the comparator 21 is 1, the equation 3 Thus, the controller 22 causes the select signal (sel_co
n) is generated and supplied to the selector 23.

When the select signal (sel_con) corresponding to the value 1 is supplied, the selector 23 is expressed by the following equation 3 instead of the error voltage (phs [kT]) input from the phase comparator 1. The signal (phs_bup [kT]) input from the adder 26 is output. That is, the error voltage phs [kT] is represented by the following expression 5, and the past n error voltages phsc [(k−i) T] which are not abnormal.
For each of (i = 1, 2, ..., N), the constant a
_It is replaced by the average (phs_bup [kT]) of those weighted by _i (i = 1, 2, ..., N).

[0040]

[Equation 1]

Alternatively, it is also possible to replace it with another value represented by the following equation 6, which is actually the average value of the error voltages in the past.

(1 / (Lpf_gain)) × vco [kT] (Equation 6)

Further, in the case of another operation mode, it is possible to use the average value of the error voltage phs [kT] including the abnormal value of the error voltage in the past. All of these approaches are examples of various trade-offs between DPLL response speed, the amount of jitter that can be tolerated, and circuit complexity.

In this way, it is predicted that the changing tendency of the error voltage will continue, and the discarded error voltage is replaced with the history of the error voltage (weighted average of past error voltages). Therefore, the active mode (l
The operation in locked = 1) can be expressed analytically as follows.

When locked = 1, | phs [kT]-(1 / (Lpf_gain)) × v
When co [kT] |> Rng,

[Equation 2]

When locked = 1, | phs [kT]-(1 / (Lpf_gain)) × v
When co [kT] | ≦ Rng, phsc [(k + 1) T] = phs [kT] (Equation 8)

According to the equations (4), (7) and (8), the APL
Eleven actions are fully defined.

Next, the operation when the input signal represented by the above equation 5 or 7 is replaced is shown in FIG.
This will be described in detail with reference to FIG. FIG. 2 shows A when n = 2.
The structure of PL11 is shown.

When the current time t = kT (where k is an arbitrary integer and T is an error voltage update period), the selector 2
3 output signal phsc [(k-1) T] (where
At time t = (k−1) T, the signal phsc [(k−1)
T] is an output signal at time (k−1) T, which is earlier by the error voltage update period T when the current time t = kT is used as a reference) is supplied to the storage element 24a. , Remembered.

Next, after the error voltage update period T has elapsed, the signal phsc [(k-2) held in the storage element 24a is stored.
T] (where time t = (k−2) T is the signal phsc
[(K−2) T] is an output signal at time (k−2) T, which is a time (2 × T) earlier than the current time t = kT. , Storage element 24
is supplied to b and stored.

The signal phs stored in the storage element 24a
[(K-1) T] is supplied to a multiplier 25a, after being multiplied by a predetermined coefficient a _1, it is supplied to the adder 26. On the other hand, the signal phs [(k-
2) T] is supplied to the multiplier 25b, and a predetermined coefficient a ₂
After being multiplied by, it is supplied to the adder 26.

In the adder 26, the multiplication result from the multiplier 25a and the multiplication result from the multiplier 25b are added, and the addition result (phs_bup [k
T]) is supplied to the selector 23.

Phs_bup [kT] = (a ₁ phsc [(k−1) T] + a ₂ phsc [(k−2) T]) / 2 (Equation 9)

Select signal (s from controller 22
When the value of el_con) is 1, the operation result (phs_bup [k
T]) is selectively output as the signal phsc [kT].

For example, as the values of the coefficients a ₁ and a ₂ ,
Coefficient a ₁ = a ₂ = 0.5, or coefficient a ₁ = 0.
7 and the coefficient a ₂ = 0.3. Generally, newer ones of the past error voltages are assigned more weights, and thus newer histories are emphasized. Past error voltage phs [(k-1) T]
Since and phs [(k−2) T] are held in the storage elements 24a and 24b as described above, it is possible to perform the operation represented by Expression 9.

As described above, in the above embodiment,
Detects abnormal error voltage and discards it. The abnormal error voltage is outside the predetermined range defined by the DPLL and the input signal characteristics of the DPLL. This range is not constant and can be automatically updated according to the operation mode (idle mode or active mode) of the DPLL and the drift of the input signal of the DPLL.

Fast error voltage changes (eg, caused by noise and / or other imperfections) are not completely eliminated by loop filter 2, but
It only decreases, thus increasing PLL jitter and increasing the probability of loss of synchronization. By using the adaptive phase limiter (APL11), it is possible to completely cancel an excessive error voltage exceeding a predetermined reference value. For example, some of the unwanted components of the input signal caused by strong noise ghosts or defects in the clock mark pattern can be suppressed non-linearly and completely. As a result, the performance of the DPLL can be improved with respect to reduction of jitter and improvement of reliability. This method is practical and can be implemented economically in various ways.

Thus, the error voltage is compared online with its history. Here, the history of the error voltage is a weighted average of past values of the error voltage. If the difference between the error voltage and its history is greater than a predetermined reference value, it is considered abnormal, probably because of a noise burst or a defect in the medium. Therefore, the error voltage regarded as abnormal is replaced by another value.

This replacement can be performed simply by a past value of the error voltage, a linear combination of the past error voltages, a linear combination of only the error voltages that are not abnormal, or a history of the error voltages. The history of the error voltage can be obtained by various calculation methods as described above. For example, the output of the loop filter 2 may be multiplied by the reciprocal of the DC gain of the loop filter to convert the output of the loop filter 2 into the error voltage level. Alternatively, it can be calculated as a weighted average of past error voltages selected indiscriminately. Alternatively, it can be calculated as a weighted average of only error voltages that are not abnormal.

In the above embodiment, the value of the variable n in the expression 5 or the expression 7 is set to 2 and corresponding to this,
The case where the number of storage elements and the number of multipliers are two has been described, but the number is not limited to this.

[0061]

According to the phase detecting device and the phase detecting method of the fourth aspect, it is determined whether or not the phase detection result of the reproduced waveform of a predetermined clock mark is an abnormal value. If it is determined that the phase detection result is an abnormal value, the phase detection result is replaced with a predetermined calculation value calculated based on the past phase detection result. Can be removed. Therefore, the jitter can be reduced, the reliability can be improved, and the performance of the device can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a DPLL applied to a phase detection device of the present invention.

FIG. 2 is a block diagram showing a detailed configuration example of an APL 11 shown in FIG.

FIG. 3 is a block diagram showing a configuration of an example of a conventional DPLL.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 phase comparator 2 loop filter 3 VCO 11 APL 21 comparator (determination means) 22 controller 23 selector (replacement means) 24a, 24b storage element (storage means) 25a, 25b multiplier (calculation means) 26 adder (calculation means)

Claims (5)

[Claims] 1. A phase detection device comprising a DPLL for detecting the phase of a reproduction waveform of a clock mark which is a timing reference, and determines whether or not the phase detection result of the reproduction waveform of a predetermined clock mark is an abnormal value. And a replacement unit that replaces the phase detection result with an operation value calculated based on the phase detection result in the past when the determination unit determines that the phase detection result is an abnormal value. A phase detection device comprising: 2. A storage means for storing the past phase detection result, and a computing means for computing the calculated value by a predetermined method based on the past phase detection result stored by the storage means. The phase detection device according to claim 1, further comprising: 3. The phase detecting apparatus according to claim 1, wherein the replacing means replaces the phase detection result with the calculated value when the DPLL is in a locked state. 4. A phase detection method comprising a DPLL for detecting a phase of a reproduced waveform of a clock mark which is a timing reference, and determines whether or not a phase detection result of a reproduced waveform of a predetermined one of the clock marks is an abnormal value. Then, when it is determined that the phase detection result is an abnormal value, the phase detection result is replaced with a predetermined calculation value calculated based on the past phase detection result. 5. When the DPLL is in a locked state,
The phase detection method according to claim 4, wherein the phase detection result is replaced by the calculated value.