JPH096534A - Computer system and input device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system including a central processing unit(CPU), a memory circuit, an I/O auxiliary processor, a touch pad, and two joy sticks positioned on both the sides of the touch pad. SOLUTION: An input device 18 acts as an interface to the CPU 30 through a serial data link 22 connected to the I/O auxiliary processor 36. The touch pad 19 has a default templet graphic image set up on the surface or inside the pad 19 itself and a retainer for detachably fixing a templet overlay to be used together with the pad 19 instead of a default templet.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates generally to coordinate type pointing devices for use in digital systems, and more specifically to a touchpad with a preset default template associated therewith, An input device having a retainer for removably securing a template overlay to a pad surface and a pair of joysticks positioned one on each side of the touchpad.

[0002]

BACKGROUND OF THE INVENTION This application is related to US patent application Ser. No. 08 / 210,672, filed Mar. 18, 1994.

Video graphics computer
The system is a well known and popular consumer product. A typical system includes a data processing unit that connects to a conventional television set to display an image of a game or other application. The data processing unit receives control software from read only memory (ROM), which is typically packaged in the form of a cartridge. The cartridge is plugged into the data processing unit in a removable manner. The data processing unit includes a mouse, joystick, touch pad, touch screen, switch pad, light At least one pointing device, such as a gun, is also connected.

Generally, a data processing unit includes a single central processing unit (CPU) and associated volatile and non-volatile memory, including all random access memory (RAM) and bootstrap read only memory (boot ROM). A memory, a television (RF video) signal generator,
And an input / output processor for interfacing to various pointing devices. These devices are in circuit communication. One of the distinctive features of such a system is the use of a motherboard or system planar to electrically connect these components together.

A joystick is a directional type pointing device used to enter directional data into a computer system. A joystick typically includes a base and an elongated "stick," which is typically held in the user's hand. Generally "stick"
Pivots from one point on the base and has a default position perpendicular to the base. The pivoting movement of the stick from the default vertical position is interpreted as a directional input parallel to the base in the direction required to displace the stick from the default vertical position. Generally, a button is located on the top of the stick. The switch closure event is used as a control input for an application running on a computer system.

A touchpad is a coordinate type pointing device used to enter coordinate type data into a computer system. Touchpads are generally pressure-sensitive bounded planes on the surface of which local pressure can be detected. When the user touches the surface with a finger, stylus, etc., the touchpad reports the coordinates of the touch location to the connected computer system. In response, the computer executes the function, if any, associated with the pressed position.

Generally, one or more areas of the touchpad are assigned to a given function within the system.
The template allows the user to know which function is associated with each area. The template is a graphic-designed sheet, usually placed on and in contact with the touchpad surface. Graphic designs generally map areas of the touchpad surface, and are typically labeled to remind the user of the functions associated with the various mapped areas.

Generally, the touchpad system is (1)
Either you have a persistent template configured in or on the touchpad surface and cannot accept a template overlay, or (2) you do not have a configured persistent template but you have a means to accept a template overlay. It is either equipped. For this reason, each application that uses a touchpad as an input device must either exclusively use the configured persistent template or provide a template overlay. Therefore, when using a typical system, software application designers should limit the possible input from the touchpad (by using only persistent templates) or
Or, one is forced to design and define one or more custom templates for use with that particular software application.

Further, joysticks are typically coupled only with switches and other closed type input devices. Therefore, joysticks are typically not used in other coordinate based input devices.

[0010]

SUMMARY OF THE INVENTION The present invention provides an input device having a touchpad and a pair of joysticks positioned one on each side of the touchpad. This joystick has two people, for example,
It is positioned so that adults and children can provide position input to computer systems at the same time, but in a way that one can support the other.

[0011]

A touchpad removably secures a preset default template graphic design and other template overlays for use with the touchpad in place of the default template graphic design. And a retainer for. The default preconfigured template has a set of commands that can be used by many software applications. The template overlay has a command set for one or more specific software applications.

Accordingly, one of the advantages of the present invention is to provide an input device configured to allow two persons to provide location information at the same time and to provide command access within the entire package.

Therefore, another advantage of the present invention is that
The goal is to provide the software application with a common set of functions accessible from the default template graphic image, while providing access to the custom template overlay to the software application.

The above and other advantages of the invention will be more apparent from the detailed description of the invention.

The accompanying drawings, which are incorporated in and constitute a part of this specification, show an embodiment of the present invention. This embodiment, together with the outline of the present invention described above, will be described in detail below. It serves to illustrate the principles of the present invention.

[0016]

1 and 2, a computer system 10 of the present invention is shown. As shown in FIG. 1, the system 10 includes a program cartridge 14 detachably connected thereto.
And a data processing unit 12 with. The data processing unit 12 also includes a standard television receiver (TV) 1
6 and an input device 18 are also connected, and the input device is a touch pad 19 and two joysticks 20a, 2
0b. The input device 18 is the touch pad 1
The data of the coordinate type corresponding to the contact position of the finger, the stylus 21, etc. on the 9 is transmitted to the data processing unit 12. Further, the input device 18 includes a joystick 20.
The direction type data corresponding to the movements a and 20b is transmitted to the data processing unit 12. Although not shown in FIG. 1, the standard TV 16 can be replaced with a pair of speakers and a display device that accepts the composite video signal. The input device 18 is connected to the data processing unit 12 via a serial data link 22. The TV 16 is connected to the data processing unit 12 via an RF video line 24.

Cartridge 14 has an edge card connector, generally indicated at 26, which is a cartridge
Connect to connector 28, thereby allowing cartridge 14
The devices therein are electrically connected to the devices within the data processing unit 12.

The processing unit 12 has a SY associated with it.
Central processing unit (CPU) having STEM bus 31
30, an audio / video (A / V) controller / auxiliary processor 32, and a SYS generated by the A / V controller / auxiliary processor 32 from the SYSTEM bus 31.
A system memory 33 connected to the TEM bus 34,
First and second decoder chips (not shown), an I / O coprocessor 36, two cartridge connectors (one shown at 28, the other not shown),
It includes additional circuitry 38 needed to generate audio and video signals, and expansion connector 39. These devices are connected in circuit connection as shown. The additional circuit 38 is shown in FIG. 2 and described in more detail in the text accompanying FIG.

The CPU 30 is a DATA bus, ADDRESS bus, CONTROL, as is well known in the art.
A plurality of buses called L buses are generated. These three buses are collectively called the SYSTEM bus 31. In the preferred embodiment, CPU 30 is an Intel Corporation (3065 Bowers Av
e., Santa Clara, California, 95051) 80376
It is. The 80376 is well known in the art and is also known from the Intel Corp. 80386SX.
Is a variation of. The 80376 differs from the 80386SX in that the 80376 starts up in 32-bit mode instead of 16-bit mode. Specifically, the CR0 register is forced to 0011H (hexadecimal notation of 0011)
State, bit 0 forced to logic 1 and 376
Effectively operate in 32-bit memory mode.
Paging is enabled to allow virtual 386 operation.

The A / V controller / auxiliary processor 32
Three spare general purpose I / O decoder lines (GPIO1, GPIO2, GPIO3) are generated from the SYSTEM bus 31 and each provides a 32 bit I / O address range. A general purpose decoder allows devices external to the A / V controller / auxiliary processor 32 to have three active low chip enables.
les) can be provided. Data processing unit 1
At 2, the general purpose decoder is used to decode the address range to the I / O coprocessor 36 (GPIO1) and the two cartridge connectors (GPIO2 and GPIO3). The remaining circuitry of the A / V controller / coprocessor 32 is described below.

The system memory 33 includes a screen RAM and
It includes system RAM and bootstrap ROM (neither shown). On-board screen RAM and system RAM are 1 megabyte of 32-bit DRAM. One suitable DRAM is 256 kilobytes from Toshiba configured to provide 32-bit memory.
6-bit memory chip TCS14170BJ
There is. A portion of the CPU 30 address space consists of several 8-bit blocks in the A / V controller / coprocessor 32.
Decoded in register. All internal locations are on even address boundaries, and word-wise I / O read / write can be performed at appropriate locations. In this particular example,
It is not possible to write byte-wise on a word-wise register, nor can I / O cycles be used to access odd addresses.

The bootstrap ROM is always 16 bits wide. The bootstrap ROM includes two 27C512 erase / programmable read-only memories manufactured by many manufacturers, thereby providing a 128K bootstrap ROM. After reset, 1 in the range of F20000H to FFFFFFH including ROM and internal memory
The megabyte window is repeated over the 16 megabyte address range.

The system memory 33 is shared by a plurality of devices. The A / V controller / auxiliary processor 32
Arbitrator for system memory 33 (arbitrato
r). Therefore, the SYSTEM bus 31 is
/ V controller / auxiliary processor 32
M bus 34 (DATA bus not shown, AD
(Including a DRESS bus and a CONTROL bus). As a result, the system memory 33 is
It is accessed via the TEM bus 34.

The input / output auxiliary processor 36 is the input device 1
8, a keyboard (not shown), various control devices (not shown), a mouse (not shown), an optional device such as a printer (not shown), and the like, and an interface between the CPU 30 and a large number of input / output devices. take. In the preferred embodiment, this I / O coprocessor 36 is a Motorola preprogrammed MC68HC705C8 (hereinafter "68HC705") operating at 2 MHz. 68HC705
The I / O coprocessor 36 uses the 68HC70 as follows.
By configuring 5 as a peripheral device, it interfaces with the CPU 30. That is, (1) PA0
~ PA7 is connected to D0 to D7 of the DATA bus,
(2) PB7, PB1, and PB2 are GPIO1 of the ADDRESS bus and the CONTROL bus (A as described later).
/ V controller / 32-byte address range decoded by auxiliary processor 32), A1 and A2, respectively, and (3) PB3, PB4, and PB5 are CONTR.
It is connected to ADS, READY, and W / R of the OL bus, respectively. The I / O coprocessor 36 has four 16-bit addresses (hereinafter, AS0, AS2,
AS4, AS6)) to be decoded by the A / V controller / coprocessor.

The program in the 68HC705 interfaces with the CPU 30 as follows. 68HC7
05 is directly connected to the processor bus and is designed to operate as an input / output port to the CPU 30.
A pair of internal latches store data to and from each processor until the remaining processors are ready to receive. The status bits for each processor are
Indicates the state of the data latch. Each processor can check its status bit to determine if the previous data was read and if it is waiting for new data to be read.

Input / output coprocessor 36 is, among other things,
(1) 50 ms timer, (2) serial controller link for receiving communication packets from input device, (3) cartridge 14 in each cartridge connector
There are various functions such as a cartridge / expansion sense for discriminating the presence or absence of an expansion device or a CD drive in the expansion connector, (4) system reset, (5) I ² C non-volatile RAM (NVRAM) interface. To be realized. The I / O coprocessor 36 also implements an optional DSA compact disc control serial line to enable communication with an optional CD drive. The I / O coprocessor can also perform the I / O device authorization function by matching the unique I / O device authorization code with the preprogrammed I / O device authorization code. The I / O device authorization function can be part of the system input controller (SIC) located in the I / O space, and the CP / 1 ASIC GPI01.
It can be accessed by the address defined and decrypted by. All I / O transfers to and from the SIC are 8 bits. Alternatively, the SIC is 376 / 386SX
CPU3 which interrupts the processor interface and executes the matching of the authorized I / O device authorization code
Pass the I / O device message to 0. The I / O device authorization code is (in addition to the standard device type identification data), for example, a trade name and / or manufacturer name and / or other details of the device, and any password, whether encrypted or not. Alternatively, it can be a desired authorization data and sequence, such as a code. From the SIC of the I / O coprocessor to the system 1
2 contains the product or source identifier or anagram or code or password of an I / O device authorized to interface with the system for display on the monitor 16 when passed to the computer or recognized by the CPU 30. , Text or graphics to display validated I / O device authorization data
It may further include routines or both.
Therefore, displaying the I / O device authorization data to the user is such that the connected I / O device is an identified type, which is manufactured by the identified source or manufacturer of the I / O device, which is To indicate to the user that the system has been effectively authorized.

Input data from the I / O controller is sent to the system via an asynchronous serial data message consisting of the device type and number (including any authorization code and / or password) and input data. To be Input device data messages are SI
Received by C and decoded. For example, the message generated by the external input control device and input to the system can be 10 different messages. First
Bytes are byte counts. The second byte is the device ID (type). The device ID includes two parts. The upper 4 bits are the device number of the I / O chain,
The lower 4 bits are the ID for the device. The additional bytes are
It may or may not be sent, depending on the device type and the required device authorization data. As explained below, the last byte is a checksum, which uses an 8-bit checksum and ignores carry (modulo 256), when all bytes of the message have been added, This is to force the total of all message packets to zero.

The 50 ms timer is implemented by configuring the watchdog timer of the 68HC705 I / O coprocessor 36 to time out at 50 millisecond intervals. Each time the watchdog timer expires, the I / O coprocessor 36 uses the analog interrupt 0 (AI0) of the A / V controller / coprocessor 32 to interrupt the CPU 30 (A / V controller / The auxillary processor interrupts the CPU via the IRQ line in response to the I / O auxillary processor pulling AI0 low). The CPU enables and disables the 50 ms timer by writing either byte 0F0H or byte 00H to I / O port AS0, respectively. This timer is enabled by default.

During the CPU interrupt acknowledge cycle, A /
The VController / Auxiliary Processor asserts the address of the interrupt handling routine. By the interrupt processing routine,
The CPU 30 reads one byte or a plurality of bytes from the 16-bit input / output port AS0 corresponding to the input / output auxiliary processor. During each read of the I / O port AS0, the A / V controller / coprocessor 32 selects the I / O processor 36, which enables data transfer between the CPU 30 and the I / O coprocessor 36.

The I / O auxiliary processor 36 always prepares one byte to be transferred to the CPU in response to the 50 ms interrupt. The lower 4 bits of this byte contain the number of 50 ms time outs since the last interrupt acknowledge cycle, and the upper 4 bits of this byte contain the number of I / O device messages to be transferred to the CPU. 50 ms
If the timer is disabled, the lower 4 bits of this byte will be zero. If more than 16 messages are received, 15 will be sent in the upper 4 bits and the remaining messages will be sent on the next transfer. Depending on the contents of this first byte, the CPU will send the following bytes to the I / O coprocessor 3
6 can be read, and for the most part they will be packets of data from the input device. Generally, the input device will send messages only when their respective states change, thereby keeping the message transmission frequency very low.

Input device 18 and all other input devices are connected to input / output coprocessor 36 via serial data link 22. An individual input device (eg, input device 18) serializes the movement of the controller.
Convert to a format suitable for transmission by link 22. The input device 18 sends data packets to the system unit 12 via the serial data link 22. As described below, the structure of the data packet depends on the type of input device. Coordinate type devices (mouse, analog joystick, touchpad, etc.)
Has a different data packet structure than switch closed type devices (keyboards, digital joysticks, switch pads, etc.).

The serial controller link 22 is composed of three lines: a data receiving line, a VCC (+5 VDC) line, and a ground line. 68HC705 is the 68HC705
The PD0 / RDI pin of is used to implement the data receive line of the controller serial link. This pin is designed to be used as an interface to serial devices using the well known asynchronous format. Serial transmission uses the format of 4800 bits per second, no parity, 8 data bits, 1 stop bit. In an alternative embodiment, a clocked synchronous format could be used. The serial controller link 22 is connected to an external device known in the art by a 6 wire mini DIN plug connector (not shown). The input devices are daisy chained, thus physically a single device is connected to the data processing unit 12. For example, if a so-called mouse pointing device is added to the system 10, the mouse is connected to the input device 18 and the input device 18 is connected to the processing unit 12.

The cartridge sense and expansion sense are for determining the presence or absence of the cartridge 14 in the respective cartridge connector or expansion connector, and to cause the I / O coprocessor 36 to poll the pins of the cartridge connector 28. Is realized by This pin is pulled to a logic one by an appropriate pull-up resistor (not shown) on the system planar, and when the cartridge 14 is properly connected, the cartridge pulls the pin to a logic zero.
Therefore, a 1 in each cartridge sense means that there is no cartridge 14, and a 0 means that there is a cartridge 14. Similarly, an expansion sense of 1 means that there is no expansion device such as an optional CD drive, and 0 means that there is an expansion device.

Reset is accomplished by giving the I / O coprocessor 36 control over the reset signal of the A / V controller / coprocessor 32 and then the A / V coprocessor 36.
V controller / coprocessor 32 controls the reset signal of CPU 30. CPU 30 may instruct I / O coprocessor 36 to reset system 10 by causing I / O coprocessor 36 to reset the A / V controller / coprocessor.
The V Controller / Auxiliary Processor resets the CPU 30. The CPU causes the I / O controller to generate a system reset by writing byte 0FFH to I / O port AS0. Further, the input / output auxiliary processor 36
Monitors an optional reset switch (not shown) for the system and resets the system when it detects switch closure.

Finally, the I / O coprocessor is 512
To read, write, and test the contents of a byte of non-volatile system RAM, an I ² C non-volatile RAM (NVR)
AM) is realized. NVRAM (not shown) is Philip
s Semiconductor PCF8594, which is in circuit communication with the I / O coprocessor through the I ² C interface. Multiple PCF8594s can be cascaded to provide more NVRAM capacity. A 3-byte sequence is used to access NVRAM. All three bytes are accessed via the input / output port AS0. The first byte written by the CPU to the I / O coprocessor indicates whether the transfer is a read or a write and provides the I / O coprocessor with a segment address. The lower 4 bits of this byte indicate the type of transfer, 01H is NVRAM
02H indicates a read from NVRAM and 02H indicates a read from NVRAM. The upper 4 bits of this byte are 2 of NVRAM
It is a 4-bit segment number corresponding to a 56-byte segment. In 512 bytes of NVRAM, only the bottom two segments (0 and 1) are used. The next byte will be the same for both reads and writes, and the next byte will be written by the CPU and will be the address of the byte accessed in that segment. The last byte becomes a data byte that is written to or read from the I / O coprocessor by the CPU and read from or written to NVRAM.

In alternative embodiments, the I / O coprocessor can be implemented in other ways. For example, a tri-state readable shift register should be able to properly receive information from serial data link 22. In that case, the CPU 30 periodically reads the shift register to access the data packet from the input device.

The first decoding chip (not shown) is
CPU 30, A / V control device / auxiliary processor 32, 2
In electrical circuit communication with one cartridge connector 28 (the other not shown). The first decode chip accepts the two address lines at the top of the SYSTEM bus 31 as inputs and puts the 16 megabyte address space of the 80376 CPU 30 into four 4 megabyte areas represented by the three chip select lines. Decrypt. Of these chip selection lines, two are cartridge connectors 28
One is for the A / V controller / auxiliary processor 32 (the other is not shown). The upper 4 bytes and the lower 4 bytes are decoded into an A / V controller / auxiliary processor chip select and the remaining two 4 megabyte areas are decoded into two cartridge connector chip selects.

The second decoder chip (not shown) is
Used to implement chip selection for expansion connector 39. The second decode chip is the SYSTEM bus 3
4 in circuit communication with the A / V controller / auxiliary processor 32 and expansion connector 39. The second decode chip allows the A / V controller / coprocessor 32
128 of system ROM starting from F20000H
K blocks can be decoded. F40000H
The range ~ FFFFFFH is decoded by the second decoding chip for use by expansion connector 39.
The ROM of this block, which is decoded by the second decoding chip, is transferred to the system 10 via the expansion connector 39.
Used to add ROM to.

The data processing unit 12 also includes a pair of cartridge connectors (one shown at 28 and the other not shown) for bringing the cartridge 14 into circuit communication with the CPU 30 and other system components. . The cartridge 14 is connected to a connector 28 of the data processing unit 12 via a gold-plated 62-pin (31 lines of conductive wire in two rows) edge card connector 26. The processor unit 12 is an edge
Two cartridge connectors 28 are provided to receive the edge card connections of card connector 26. The cartridge 14 includes a gold-plated card edge connection to fit the conductors of the connector 28 to allow the cartridge 14 to be pluggably connected to the processor unit 12. The following signals are sent to the external device via the cartridge connector 28 (the other one not shown). That is, the SYSTEM bus 31 signal, cartridge sense line, power supply, ground, analog interrupt 1 or 2 (each cartridge has one unique interrupt), and GPIO 2 or 3
(Each cartridge has its own chip selection) and lock lines (80376 and 80386).
(Typical signal on the SX SYSTEM bus 31)
And a cartridge selection generated by the first decoding chip. In an alternative embodiment, the signals necessary to connect to an optional CD drive can also be connected to an external device via cartridge connector 28.

In addition, the processor unit 12 has a single 112 pin edge card expansion connector 39 (56 pins in two rows). This expansion connector 39 allows the device to add more memory to the system memory 33 and various other features. The device connected to the expansion connector 39 has a gold-plated card edge to fit the expansion connector, allowing the device to be plugged into the processor unit 12. The following signals are expansion connector 3
9 to the external device. That is, SYSTE
M bus signal, expansion connector 39 sense line, power supply,
Ground, CAS and RAS lines, second decoding
An expansion connector 39 selection generated by the chip. In an alternative embodiment, the signals needed to connect to an optional CD drive can also be connected to external devices via expansion connector 39.

The program cartridge 14 includes a program ROM 40 and a decoder 42. In an alternative embodiment, the decoder 42 may be designed within the processing unit 12. Program ROM 40 contains code suitable for execution on CPU 30 in a read-only memory format. In alternative embodiments, other memory types, such as battery backed RAM, may be used as the storage device in cartridge 14. The program ROM 40 is in circuit communication with the CPU 30, as shown in FIG.

The address decoder 42 in the cartridge 14 programs the entire width of the ADDRESS bus into a program RO.
Decode to memory range suitable for M40 and chip select signal 44 required by ROM 40 as is well known in the art.
Generate Address decoder 42 is implemented in a 16V8 programmable array logic circuit (PAL),
It is well known in the art and is manufactured by numerous manufacturers such as AMD Corp. If the decoder 42 is designed in the processing unit 12, the selection 44
Are electrically connected to the ROM 40 by the connector 26.

Referring now to FIG. 2, the additional circuit 3 of FIG.
8 is shown connected to the A / V controller / auxiliary processor 32. The additional circuit 38 is a video digital analog converter (video DAC) 50, NTSC.
/ PAL ("PAL" means the well-known European television signal standard) encoder 52, audio digital
Analog converter / analog / digital converter / compressor / decompressor (ADC / DAC / CODEC) 54, R
It includes four devices, the F modulator 56. Each device is connected as shown in the accompanying drawings.

The electronics of the audio / video controller / auxiliary processor (A / V controller / auxiliary processor) 32 is called an ASIC (application specific integrated circuit) 1.
Approximately housed in one large custom logic chip. An A / V controller / coprocessor 32 compatible with the description herein is available from MSU Ltd. (270 Upper 4th Street, Wit
an Gate West, Central Milton Keynes, MK9 1DP Engla
nd). The A / V controller / auxiliary processor 32 has a processor interface 60.
A processor cache 62, a memory interface / refresh 64, a video controller 66,
It includes an interrupt controller 68, a video blitter 70, an optional CD block decoder, a digital signal processor (DSP) 74, and a DSP memory 76.
Processor interface 60, memory interface / refresh 64, and video controller 66
Collectively referred to as video / memory controller 67. The system memory 33, central processing unit 30, and other devices are external to the A / V controller / auxiliary processor 32.

The A / V controller / auxiliary processor 32
The SYSTEM bus 31 to the SYSTEM bus 34 are generated, so that the system memory 33 to the CPU 30 are generated.
Is separated. Therefore, the SYSTEM bus 34 electrically connects various devices to the system memory 33.
Memory refresh 64, video controller 66, optional CD block decoder (not shown), DSP 7
4, blitter 70, CPU 30 (by processor interface 60), 6 possible bus masters (highest to lowest priority) are SY
The STEM bus 34 is shared. SYSTEM Bus 3
Only four bus masters can control four at a time.
The arbitrator in the video / memory controller 67 controls the priority changes of the various devices and is in electrical communication with all the devices in the A / V controller / coprocessor 32 as described herein. ing. For example, CPU3
0 has the lowest priority of all bus masters until an interrupt occurs. Therefore, the arbitrator includes the CPU interface 60 and the interrupt controller 6.
8 are in circuit contact with both.

The cache 62 is not a cache in the sense of prefetching instructions for the CPU 30. Rather, the cache 62 can be used by the CPU 30 for variables, stacks, or program code to speed up program execution, F14000.
It is a static RAM of 512 × 16 bits located in H to F143FFH.

A video / memory controller 67 (processor interface 60, memory interface / refresh 64, video controller 66) controls the SYSTEM bus 34 and, as is well known in the art, a SYSST.
It provides memory timing signals (eg, CAS, RAS, writable, etc.) to memory devices connected to the EM bus 34. This suspends the operation of the bus master in the video line for a short period of time to fetch the video display data and refresh the dynamic RAM (DRAM). It also controls the interface with the CPU 30.

The video controller 66 has a flexible video timing generator that can be programmed to meet various TV standards, up to 640 x 480V.
Monitor up to GA standard. The correct video format is horizontal period in the A / V controller / auxiliary processor, horizontal sync, end of horizontal blanking, start of horizontal blanking, start of horizontal display, end of horizontal display, start of horizontal fetch, end of horizontal fetch Controlled by setting various registers: horizontal vertical sync, vertical period, vertical sync, vertical blank erase end, vertical blank erase start, vertical blank start, vertical display start, vertical display end, video interrupt, light pen register. It The video controller 66 is provided with three color resolutions: 4 bits per pixel, 8 bits per pixel, and 16 bits per pixel. The screen memory map is not bound by the video display width, but is defined independently.

The video / memory controller 67 has 8037
6 Decode the 16 megabyte address range of CPU 30 into the following memory map. That is, 1MB system RAM (000000H to 0FFFFFH),
4MB for the first cartridge ROM (400000H
~ 7FFFFFH), 4 for the second cartridge ROM
MB (800000H to BFFFFFH), 64KB internal memory (F10000H to F1FFFFH) for audio / video controller / auxiliary processor, 128K
B block system ROM (FE0000H to FFF)
FFFH). The 64 kilobytes of internal memory includes palette RAM, blitter registers, DSP registers and memory. The palette address range is as described above. The blitter register is F10400H
To F107FFH. DSP memory is F10
It ranges from 800H to F18000H.

When adding an optional CD drive to the system, another 1MB of system RAM (100000
H ~ 1FFFFFH) and 128 KB for CD drive
The area (FC0000H to FDFFFFH) is added to the memory map.

The interrupt controller 68 has a video interrupt (highest priority), an analog interrupt 0 (AI0), an analog interrupt 1 (AI1), an analog interrupt 2 (AI2), and a C interrupt.
Interfaces the D block decoder interrupt and DSP interrupt (lowest priority) to the CPU 30 in six ways. The interrupt controller automatically clears the interrupt when the CPU 30 executes the interrupt acknowledge cycle. One mask bit is prepared for each interrupt.

The blitter 70 is a graphic processor for high-speed screen updating and animation, and operates as a hardware graphic subroutine for the CPU 30 or the DSP 74. It executes commands written to memory by CPU 30 and DSP 74. Also, by reading a new command set from system memory 33, arbitrarily long sequences of graphic operations can be performed. The blitter 70 becomes a bus master by the operation of the blitter program, and therefore
It may have exclusive control of the SYSTEM bus 34 for a considerable period of time. However, the priority for the CPU 30 is not absolute, and when an interrupt occurs,
In some cases, it may be required to give up the SYSTEM bus 34 to the CPU 30. Although CPU 30 is the lowest priority bus master at the system level, it has complete control over other hardware, and is therefore SYSTE.
The use of M-bus 34 is completely under the control of the CPU 30 program.

The blitter 70 comprises a versatile comparator for enabling sophisticated blitting operations and a logic functional unit (LFU) for producing output data. The logic functional unit may combine the contents of the data registers in some useful way to produce output data, the comparator performing a given comparison on the data,
You can prohibit write operations and optionally stop blitter operations.

The logic function unit produces output data,
This data is written to the destination in system memory 33. This unit is capable of performing a logical combination of source and destination register pixels. The "source data pixel" can be selected from either the source data register or the data pattern data register. The LFU is a four Boolean minterm (A & B, of two sets of input data from the data register.

[Equation 1] Is hereinafter referred to as A bar. & B, A &

[Equation 2] Is hereinafter referred to as B bar. , A bar & B bar) to generate a logical OR of the two selected minimum terms. This allows any logical combination of the input data, so that there are 16 possible function possibilities.

The comparator can perform various comparisons on the data in the source, destination, and pattern data registers. If the comparison condition is met, the comparator produces an inhibit signal. This inhibit signal is used to inhibit the write operation as well as optionally stop the blit operation. The comparator can also be used for collision detection and system memory 33 search operations, and as an aid to character painting, to provide a pixel plane effect to provide a transparent color.

The DSP 74 is a simple and very fast processor for speech synthesis, with a maximum of 33 million instructions / second (M
IPS). It can access the SYSTEM bus 34 via a DSP DMA controller (not shown), which allows bytes or words to be read from or written to the system memory 33. Such transfers are done in short bursts and
It is under the control of the P program. The DSP 74 actually executes the program and has its own private high speed memory 76.
To store data.

The DSP74 audio coprocessor is
It is a general-purpose arithmetic auxiliary processor with sufficient capability to realize a high-performance music synthesizer. A synchronous serial output is provided to produce a stereo audio signal with 16-bit precision, providing the audio quality normally associated with compact disc technology. DSP74 is CPU3 of host
It is microprogrammable from scratch and its instruction set is flexible enough to allow the user to program the device to implement a wide variety of functions that are quite different from those of the "music synthesizer". As such application fields, algorithmic voice generation, audio analysis by a fast Fourier transform technique, and three-dimensional figure rotation can be considered. The DSP 74 uses a Harvard architecture (separate program and data buses) for maximum data throughput. Further, the DSP 74 is an arithmetic logic unit (A
LU), which features hardware 16-bit by 16-bit hardware multiplication / accumulation as well as addition, subtraction, and logical functions. Also, 1 per moment
There is also a separate serial division unit that produces one quotient bit.

The ALU in the DSP 74 is a 16-bit arithmetic logic unit with the same functionality as the Texas Instruments 74181 well known in the art. General arithmetic operations are coded as instructions, but uncommon instructions are
This can be done by setting up the LU mode bits directly.

The DSP 74 has a DSP memory 76 associated with it. DSP memory 76 includes program RAM, data RAM, register / constant table, and sine ROM (all not shown). In general,
The DSP memory 76 is accessible in both the DSP internal address space as well as the system memory 33 address space. The DSP program RAM is 512 18-bit words. These positions are CPU30
It can only be written by and is program read-only as far as the DSP 74 is concerned. Program RAM
Does not appear in the DSP internal address space. The program RAM is inaccessible to the host when the DSP 74 is executing, but is accessible when the DSP is idle.

The DSP 74 also includes a serial audio digital to analog converter (DAC) interface. D by serial DAC interface
SP74 is a synchronous serial (I ² S or similar)
It allows both driving of the DAC and data input from a synchronous serial data source such as a CD drive.

The video controller 66 of the A / V controller / auxiliary processor 32 connects to an external video DAC 50 which, as is well known in the art, has 18 bits of pixel information 78 (red) from the video controller 66. , 6 bits each for green and blue) are converted into RGB signals 80. Each color channel (R80
a, G80b, B80c) are R2 as shown in FIG.
It is realized by an R resistor tree and a 2N2222 transistor. The various devices of FIG. 3 are in circuit communication as shown. In addition, each of the resistors 86a to 86j in FIG. 3 is a 0.25 watt resistor having a value shown within an allowable range of 5%. The transistor 88 is a 2N2222.

Referring again to FIG. 2, the RGB signal 8
0 is NTSC by NTSC / PAL encoder 52
It is converted into a composite video signal 90. The NTSC / PAL encoder 52 is an A / V controller / auxiliary processor 32.
Chroma Clock 92, HSYNC, VSYNC signals 94 generated by the video controller 66 of FIG.
b and blue 80c video outputs are accepted and well-known NT
It produces a composite video signal 90 in SC or baseband video format. In an alternative embodiment, the well known P
AL (European Television Signal Standard) format can be generated. The composite video signal 90 is connected to an external device with a single female RCA type phone jack (not shown), as is well known in the art. In the preferred embodiment, NTSC / PAL encoder 52 is a Sony CXA1145. In an alternative embodiment, the Motorola MC1377 can also be used.

Audio ADC / DAC / CODEC5
4 is linked to the DSP 74 by a serial link 96 compatible with the well known Phillips I ² S protocol. The ADC / DAC / CODEC 54 performs conversion from analog data to digital data and vice versa, and performs compression and decompression of digital data. The ADC / DAC / CODEC 54 interfaces external stereo analog data 97a-97b from any microphone to the A / V controller / auxiliary processor 32. The audio inputs 97a-97b are
Connects to external devices with standard stereo 1/4 "connectors. Also audio ADC / DAC / CODE
C54 is a left / right audio line output signal 98a-98b
To interface digital data from the A / V controller / coprocessor to external devices. These signals 98a-98b are connected to an external device, such as any speaker (not shown) with two female RCA phone jacks, as is known in the art. As described above, the audio line signals 98a-9
8b is also added to the RF video signal 22.

In the preferred embodiment, ADC / DAC / C
ODEC54 is CS42 made by Crystal Semiconductor
Sixteen. This part contains the microphone input with programmable gain as well as the output by the programmable attenuator. Both gain and attenuation are DSP7
Programmatically controlled by 4.

In an alternative embodiment, ADC / DAC / COD
Philips TDA1311 instead of EC54
A DAC can be used. When using this chip, the ADC function and the CODEC function cannot be used.

The RF modulator 56 outputs the composite video signal 90 and audio A from the NTSC / PAL encoder 52.
The left and right audio line output signals 98a and 98b from the DC / DAC / CODEC 54 are integrated on the carrier frequency to produce an RF video signal 22 suitable for direct input to the TV 16. Different PAL (European television signal standard)
Different RF modulators and crystals must be used to generate the formats and NTSC formats. The RF video signal 22 is connected to an external device with a single female type F coaxial connector, as is well known in the art.

Referring now to FIGS. 4-17, these figures show an embodiment of the input device 18 of the present invention.
As shown in the figure, the input device 18 includes a touch pad 19 and two joysticks 20a and 20b enclosed in a single enclosure 100. The enclosure 100 is made of ABS-T (Wong's Electronics Co. LTD. (Wongs Industrial Ce.
ntre, 180 Wai Yip Street, Kwun Tong, Kowloon, Hong
Made from acrylonitrile, butadiene, styrene) sold by Kong. The input device 18 accepts template overlays 102, each of which includes a body 104, a tab 106, and an identification pattern 108 at one of the bottom edges. The template overlay 102 can be coated paper, coated cardboard,
Made of thin material such as polyester film. One suitable polyester film is manufactured by DuPont and is widely sold under the DuPont trademark "Mylar". The body 104 has a graphic image set therein or thereon. That is, write on or inside the overlay body 104,
Permanent graphic design by printing, painting, engraving, engraving, silkscreening, etc. The tab 106 extends from the body 104 and is used to grab the template overlay 102.
The identification pattern 108 will be described in the text accompanying FIGS. 10 to 14.

The touch pad 19 has a pad surface 110, which is exposed so that it can be touched by a finger, a stylus 21, or the like. The pad surface has a default template graphic design set within the pad surface 110. That is, a default template graphic image is provided on or in the pad surface 110 by permanent writing, printing, painting, engraving, engraving, silkscreening, or the like.

As shown in FIG. 4, by default template graphic design set inside or on the pad surface 110, "input", "end",
"Pause", "Previous", "Next", arrow keys (up, down, left,
It can support various functions (right). In an alternative embodiment, "select" can be used in place of "input" and "cancel" can be used in place of "end". Further, in an alternative embodiment, ten rectangular areas could be mapped, one for each Arabic numeral. Further, in alternative embodiments, each letter may be mapped to a region of the touchpad. In a further alternative embodiment, a QWERTY on the pad surface 110
It is also possible to map the keyboard. Virtually any pattern or combination of patterns and symbols can be selected. However, the default template graphic image is system 10
Should be selected to be useful for a large number of applications aimed at.

Input device 18 includes two forms of retainers for securing template overlay 102 proximate pad surface 110. That is,
(1) an overhanging lip 112 that defines a generally U-shaped slot 114 and includes three straight lips 112a-c that hold the template overlay 102 on three sides; and (2) a template on the fourth side. A pair of ridges 116 a, 116 b holding the overlay 102. Lip 112, slot 114, ridge 11
6a and 116b are shown and described in more detail in FIGS. 6, 7, and 8 and the accompanying text.

Also shown in FIG. 4 is a handle 118 for carrying the input device 18 and a tubular aperture 120 for housing the stylus 21.

Referring now to FIG. 5, there is shown a plan view of the input device 18 with the template overlay 102 mounted proximate the pad surface 110. As shown in the figure, the three sides of the main body 104 of the overlay 102 have three lip portions 112 a to 112.
It is slipping under c. Also shown in the figure is a ridge 11 that holds the fourth side of the body 104 of the overlay 102.
6a, 116b are also shown, but the ridges are positioned one on each side of the tab 106 of the overlay 104. Overlay 102
The left and right sides of the body 104 of the
Body 1 of overlay 102 slipped under 12c
It has been inserted by sliding overlay 102 down until the bottom edge of 04 is under another lip 112b. Finally, overlay 1
02 is released and the tab 106 has ridges 116a and 116
Nested between b, this ridge holds the overlay 102 on top.

6, 7 and 8 show ridges 116a and 1a.
16b and details of overlay 102 are shown. Figure 7
Shows tab 106 extending over ridge 116b. FIG. 8 shows the body 104 of the overlay 102 adjacent the ridge 116b.

The overlay 102 grasps the tab 106 with the thumb and forefinger, and the body 104 of the overlay 102 is grasped.
Of the overlay 102 by sliding it over the ridges 116a, 116b so that the overlay 102 slides out from under the U-shaped lip 112 onto the ridges 116a, 116b.

FIG. 9 shows a slot 114 that holds the overlay 102 on three sides. Also shown in the figure is a touchpad sensor 122, an overlay sensor 124, and a plurality of template overlays 10.
2, a cavity 126 for storing 2, and a sensor 122.
Also shown is a substantially rigid base 127 made of the same material as the enclosure 100 that provides sufficient resistance to be able to detect any contact.

The touch pad sensor 122 is located close to the pad surface 110, and is configured so that the sensor 122 can detect the contact position by the pressure on or near the pad surface 110 by the finger, the stylus 21, or the like. ing.

Touchpad sensor 122 may be of any of a number of types, including impedance-based sensors, acoustic sensors, switch closure type sensors, and the like. As an example, see, for example, US Pat.
A thin film switch matrix such as the device disclosed in 736190, and US Pat. No. 4 to Ito et al.
There is a high resolution switch closure type sensor such as the device disclosed in 5299959. Suitable sensor 1
One of 02 is Wong's E as part number PR39983
lectronics Co. LTD. (Wongs Industrial Centre, 180
It can be purchased from Wai Yip Street, Kwun Tong, Kowloon, Hong Kong).

The sensor 122 produces at least one electrical signal in response to a stylus 21, finger, etc. that contacts the pad surface 110 or contacts the template overlay 102 adjacent the pad surface 110.
For example, in a switch closure type sensor, multiple drivers generally drive many wires on one axis in series, and multiple receivers drive which of the wires on the other axis by the driver. It is necessary to detect whether the transmitted signal is conducted. By knowing which driver generated the signal and which receiver detected it, the position of the contact causing the switch closure can be determined.

The overlay sensor 124 is a sensor that produces an electrical signal corresponding to the identification pattern 108 on the overlay 102. Therefore, the touchpad 1
9 overlay sensor 124 and template overlay 102 identification pattern 108 must correspond in both position and device technology. A suitable overlay sensor 124 is a bank of six optoelectronic transmitters / receivers each having one angled transmitter and one angled receiver,
This is well known in the art and is part number PR
It is sold as 39990 by Wong's Electronics Co. LTD.

As shown in FIG. 10, the overlay sensor 124 includes six holes 1 provided in the enclosure 100.
Optically coupled to the identification pattern 108 by 28a to 128f. Below each hole 128 is a single optoelectronic transmitter / receiver pair (not shown). In another embodiment (not shown), the six receiver / transmitter pairs of overlay sensor 124 and the six holes 128a-128f are divided into two groups of three, on either side of touchpad sensor 122. It can be positioned one by one. That is, the three holes 128
a-128c (and its associated receiver / transmitter pair) under one lip 112a and the remaining three holes 128d-128f (and its associated receiver / transmitter pair) the other lip 112c. Can be positioned below.

11 to 14 show examples of the identification pattern 108. The identification pattern 108 is located on one edge of the template overlay 102. There are six individual marks, one for each individual transmitter / receiver pair of overlay sensor 124. When the overlay 102 is in place, the identification pattern 108 is in alignment with the sensor 124. In the alternative embodiment described above, where two groups of three holes are used for the sensor, the identification pattern 108 is similarly divided into two groups of three and positioned one on each side of the touchpad sensor 122. There must be.

A photoelectric transmitter / sensor is used as the sensor 124.
With receiver pairs, a very simple identification pattern 1
08 can be designed into the template overlay 102. If the material that creates the overlay is white, use one area of the identification pattern with black ink or paint on the back side of the overlay and the other area with white area without black ink. be able to.

11 to 14 show examples of several possible combinations of identification patterns. 11 to 14 show 0100.
01 _2, 011110 _2, 000000 _2, 111111 ₂
Identification patterns 108 corresponding to the binary patterns of
Is shown. Therefore, the identification pattern looks like a group of light and dark regions spaced along the edge of the template overlay 102. The 000000 ₂ pattern is shown for illustrative purposes only. In actual use, the all-white 000000 ₂ pattern is probably unused. This is because the pattern corresponds to the case without the template overlay 102, in which case the default template graphic image is used.

FIG. 15 is a front view of the input device 18 of the present invention, showing the positioning of the joysticks 20a and 20b, one on each side of the touchpad 19.
As shown in the figure, each joystick 20a,
20b includes momentary pushbutton switches 130a, 130b attached to their respective ends. FIG. 15 also shows a rectangular aperture 132 that opens into the cavity 126 and is used to store multiple template overlays.

FIG. 16 is a partial cross-sectional view taken substantially along the plane indicated by the line 2M-2M in FIG. 4, showing the details of the joystick used in the input device of the present invention. The details of FIG. 16 are the joysticks 20a and 20b.
Is reproduced in both. Furthermore, the details of FIG. 16 are 90 degrees rotationally symmetric. Therefore, there are many structures in the figure.
Although shown individually, this particular embodiment actually uses four identical structures. The joystick 20a is attached to a rod 134, which is the aperture 1
It extends through 36 into the volume defined by the enclosure 100. Rod 134 terminates at pivot point 138, which pivots on switch base 140. The switch base 140 includes four screws 142a-142 to several standoffs 144a-144b.
It is fixed to the enclosure 100 by d, and its standoffs are physically attached to the enclosure 100. Aperture 136 is sealed by an annular seal 146, the annulus of which fits snugly around rod 134, the outer edge of which physically attaches to enclosure 100 at the position of the aperture in a conventional manner.

The joystick 20a has a freedom of movement of 14 degrees around the turning point. That is, rod 134 can move 7 degrees in almost all directions from a position that is completely perpendicular to the plane defined by switch base 140. The rod 134 comprises four switch actuator arms 148a-148d physically attached to it. Actuator
Arm 148 is located proximate to four rubber dome instant pushbutton switches 150a-150d, which are physically attached to switch base 140. Arm 148 and switch 150 are configured such that when joystick 20a is displaced from the vertical position, one or more arms 148 cause an associated switch 150 closure event. Therefore, the operation of the joystick 20a is performed by the switch 1
Detected by 50 closure events. In an alternative embodiment,
Other structures, such as potentiometer-based systems known in the art, allow joysticks 20a, 2
0b can be realized.

Referring now to FIG. 17, a block diagram of the circuitry within the input device 18 is shown. The input device 18 includes a touch pad sensor 122, an overlay sensor 124, and a joystick sensor 200.
a, 200b, a coordinate determination circuit 202, an overlay detection circuit 204, a 100 millisecond timer 208, and an interface circuit 210, all of which are connected in electrical circuit connection as shown in FIG.

The touchpad sensor 122 and overlay sensor 124 are as described in the text accompanying FIG. The coordinate determination circuit 202 includes a touch pad sensor 122 and interface circuits 210 and 100.
It is in circuit communication with the millisecond timer 208. Further, the coordinate determination circuit 202 is configured to receive the electric signal 203 from the touch pad sensor 122 and determine the X-axis value and the Y-axis value corresponding to the contact position with the finger, the stylus 21, or the like. For example, touchpad sensor 122
Is a switch type sensor, the coordinate determination circuit 2
02 is a driver and receiver for determining which switch is closed, as is known in the art,
Logic for converting the switch position into a meaningful value for the pad surface 110.

Overlay detection circuit 204 is in circuit communication with overlay sensor 124 and interface circuit 210. Overlay detection circuit 204 receives electrical signal 205 from overlay sensor 124,
Identification pattern 108 or 000000 ₂ as described above
Produces a message corresponding to its lack of detection.

The direction determining circuit 206 includes the joystick sensors 200a and 200b and the interface circuit 21.
I am in circuit contact with 0. Joystick sensor 20
0a, 200b includes four rubber dome switches 150a-150d and two joystick switches 130a, 130b, as described above. The direction determination circuit generates a message based on the closing event of these switches.

The 100 millisecond timer 208 is in electrical communication with the coordinate determination circuit 202. Timer 208 is 1
The time-out of the period of 00 milliseconds is repeatedly determined, and the signal 209 indicating the time-out of the period is generated. The coordinate determination circuit 202 uses this signal 209 to use the timer 116.
The change in the contact position of the finger, the stylus 21, or the like between the time-outs of the period of 100 milliseconds detected by the device is detected.

The interface circuit 210 includes a coordinate determination circuit 202, an overlay detection circuit 204, a data processing unit 12 (via the serial data line 22) and other input devices, if any, serially connected to the device.
The data line extension 23 is in circuit communication. The interface circuit 210 accepts the coordinate values determined by the coordinate determination circuit 202, the overlay message generated by the overlay detection circuit 204, and the message generated by the direction determination circuit 206, and sends such information to the serial data. -Transmit to the data processing unit 12 via the link 22.

All input devices are daisy chained to the processing unit 12. Therefore, the interface circuit sends packets from other input devices to the CPU 3
Must be passed to 0. As will be detailed below, each input device connected to the processing unit 12 has a unique device number. The device closest to the processing unit 12 is given the device number 0, and the farther the device is from the processing unit 12, the higher the device number. However, the input device does not know the device number of itself or other devices. Therefore, each device needs to add 1 to the device number of data packets passed from other input devices of the same type. Input devices in the chain with device numbers greater than 15 are ignored.

For example, assume that three input devices α, β, γ of the same type are connected to the processing unit 12 as follows. That is, it is assumed that α is connected to the processing unit 12, β is connected to α, and γ is connected to β. Therefore, α has the device number 0, β has the device number 1, and γ has the device number 2. No other device knows itself or any other device number. Each device sends a dedicated data packet with device number 0.

When α passes the data packet to processing unit 12, the default device number 0 is correct because α is closest to processing unit 12. However, β and γ also transmit the data packet with the device number 0.
To remedy such a situation, each device adds 1 to the device number of the passed packet. Therefore,
If β passes the data packet from γ to α, β will add 1 to the device number, thereby giving the packet from γ the device number 1. Similarly, if α passes a data packet with γ to processing unit 12, α will add 1 to the device number, thereby giving the packet from γ the correct device number 2. Therefore, each device in the chain will add 1 to the device number of each data packet passed from the same type of device to the next device.

Therefore, in addition to passing the data packet received from another input device (if any), the interface circuit 210 causes the serial data line extension 2
Data from the same type of device received via
Add 1 to the device number of the packet. The interface circuit 210 passes to the data processing unit 12 the data packet with the device number after the correction and the device number before the correction.

System 1 with input device 18 of the present invention
Using 0 is very simple. The input device sends the data packet to the data processing unit 12 via the serial link 22. As mentioned above, the input device interfaces to the CPU 30 via the I / O coprocessor 36. Each input device is daisy chained to the next input device. The I / O coprocessor 36 receives the data packet and stores it in a re-first in first out (FIFO) manner.

The I / O auxiliary processor 36 interrupts the CPU 30 every "moment" of 50 msec.
In response, the CPU accesses a single byte at I / O port AS0 of auxillary processor 36, and as described above, the number of instants since the last access by the CPU,
Determine the number of device messages to transfer. The 10 types of device messages are shown in the table below.

[0099]

[Table 1]

As shown in the table, this message structure has various lengths and is closely related to the input device to which it corresponds. The device message in the table is
It is the same as the data sent to the I / O coprocessor from the individual I / O devices as the data sent to the CPU by the I / O coprocessor. Each message from the I / O device to the I / O coprocessor has the structure described above plus a checksum to ensure that uncorrupted data is sent from the input device 18 to the processor unit 12. . This checksum is
A standard modulo 256 checksum such that the value required to bring the sum of all bytes to zero (ignoring carry in the sum) is the checksum value. The I / O coprocessor removes this checksum before sending the data to the CPU. Therefore, the byte stream read by the CPU will be nearly identical to the byte stream received by the I / O coprocessor. However, exceptionally, (1) the first byte read by the CPU is a special byte containing the number of instants and the number of I / O device messages, and (2) the checksum is missing.

PS / 2 mouse and keyboard devices are supported as device type 0. The keyboard has chain number 0 and the mouse has chain number 1. These devices are supported by the I / O coprocessor using the existing PS / 2 protocol over the serial data link 22.

This device type 1 is for a device having a plurality of buttons. Up to 255 bytes (8 buttons per byte) using this message type
Or 2040 buttons can be entered into the system. Open buttons are sent as logic 0, while closed buttons are sent as logic 1. This is a variable length message.

Digital joysticks such as joysticks 20a, 20b are supported as device type 2. Two joysticks are associated with each touchpad 19. Each joystick has a unique chain number. Each left joystick has an odd number (1, 3,
5, 7, 9, etc.) and each right joystick is an even number (0, 2, 4, 6, etc.). Each joystick is reported repeatedly. The message is a fixed length message. However, the digital joystick sensor has a plurality of switches 150a-1.
Note that it includes 50d. This message is
One byte representing up to eight switches, which are motion sensor switches 150a-150d.
And a data input switch such as the switch 130a. The individual bits of the message byte for this type are: upper switch (MSB), lower switch, left switch,
Right switch, switch # 1, switch # 2, switch #
3 and switch # 4 (LSB). Joysticks 20a, 20 included with the touchpad 19
There is only one button 130 on b, which corresponds to switch # 1 above. The remaining three buttons are always reported as zero.

Coordinate devices such as mice and trackballs are reported as device type 3. The first byte following the ID is for reporting the button information for that device. Up to 8 buttons can be reported.
The next byte is the Delta X value, followed by the Delta Y value. The Delta X and Delta Y values are based on the last reported device position. The application program must convert this value to absolute coordinates if necessary. The maximum movement is 255. Actual movement is 2
If more than 55, then two or more messages are sent. This is a fixed length message.

Touchpad 19 is supported as device type 4. Other devices of this device type include analog joysticks. The first byte following the ID is used to report button information. The next byte is used to report the absolute X position. The absolute Y position follows. The absolute X value and the absolute Y value are each 1 byte, and are limited to the range of 0 to 255.
This is a fixed length message.

Touchpad overlay 102 is reported as device type 5. The touchpad overlay is sensed using a 6-bit sensor 124 within the touchpad. When the touchpad senses the overlay change, a message is generated. All overlay code is application dependent, so
The application program must be aware of the code for each overlay. This message is a fixed length message.

Action messages can be generated differently by multiple device types, but have a common set of predefined device-independent functions that are similarly used and interpreted by the system and application programs. Used to define Action messages are reported as device type 6 using variable length messages. In this particular embodiment, ST
ART (start an activity or process), PAUSE
3 (pause activity or process), SELECT (select one of multiple events or actions)
One device independent function is defined and associated with the lower 3 bits of this byte. These bits are set to report these capabilities. All other bits are reserved for future use and are reported as 0 to the CPU.

The system passthrough message type is used to handle device types that do not apply to the predefined device types. Use message type 14. This is a variable length message. Data definitions are device-dependent and application-specific. Each application must translate this type of message into the required functionality.

The first message from each device is device type 15. It is used to inform the system that a device will send an input message. This message also defines future device types used to report the input. This is a variable length message.

At system power up and 50 ms
At every interval, the I / O coprocessor scans the cartridge and extended sense lines to determine their configuration, alert the system, and sends a configuration byte to the CPU. This is the first byte that the CPU receives from the I / O coprocessor at power up. Since the I / O coprocessor only generates a module configuration interrupt when a change is sensed, a system reset occurs when the cartridge status changes, causing the I / O coprocessor to send another configuration byte to the CPU. It will be. The relevant bit set in the byte sent is set to indicate the presence of the related item. That is, bit 0 corresponds to cartridge 1, bit 1 corresponds to cartridge 2, bit 2
Corresponds to the optional CD drive. The remaining bits are set to 0.

Further, the CPU writes the information to the input / output auxiliary processor 36, and thereby the serial link 2
Data can be transmitted to the input / output device via the terminal 2. Data bytes are written to the I / O port AS0 with a 03H byte preceding each byte. The I / O coprocessor writes these bytes to the I / O device. This function is used, for example, to send data to a printer (not shown) or the like.

The interface to the input device of the present invention having two joysticks and a touchpad with a preset default template graphic image is also easy to interface. System BIOS to CPU
An interrupt handler running on 30 receives data from the input device via the I / O coprocessor 36. The interrupt handler simply puts in memory 33 what was transmitted from I / O coprocessor 36. CPU
The application program executed on 30 is
Operating periodically by software interrupt
Poll the system BIOS to determine if input has been received. If received, the input is
The application program is contacted by the operating system in response to the software interrupt.

The application program monitors the current template. A default template graphic image has been detected (overlay sensor 124 has detected all transmission type identification patterns 108,
That is, to detect the 000000 _2), the application program operates responsive to the default template. If, on the other hand, the template overlay 102 is detected, the application program determines that particular template overlay 10
It operates in response to 2.

While the invention has been illustrated and described in considerable detail by the description of examples of the invention, it is not intended to limit or limit the scope of the claims to such detailed description. Absent. Other advantages and modifications will be readily apparent to those skilled in the art. For example, a QWERTY or other type of keyboard may be set up on or on the touchpad surface 100. As another example, the coordinate determination circuit 20
2, the overlay detection circuit 204, the joystick circuit 206, the 100 millisecond timer 208, and the interface circuit 210 can all be implemented in a single microcontroller. As such, the invention in its broader aspects is not limited to the specific details, exemplary apparatus and methods, and examples shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of applicant's general inventive concept.

In summary, the following matters will be disclosed regarding the configuration of the present invention.

(1) (a) Central processing unit (CPU)
Generating (b) a memory circuit in circuit communication with the CPU, and (c) in circuit communication with the CPU and memory, the electrical signal corresponding to a visual image displayed on a video display device. And (d) a peripheral device interface circuit in circuit communication with the CPU for interfacing signals from an external device to the CPU, and (e) to enable contact with a finger, stylus, etc. An exposed pad surface, (f) a retainer for releasably securing the template overlay proximate the pad surface, and (g) at least one said proximate pad surface. An electrical signal is configured to correspond to the coordinates of the contact location, touching the pad surface or proximate to the pad surface A coordinate sensor for generating at least one electrical signal responsive stylus, etc. to the finger in contact with the template overlay that,
(H) a rigid base close to the pad surface,
(I) a stylus in circuit communication with the coordinate sensor, which contacts the pad surface or contacts a template overlay proximate the pad surface.
A coordinate determining circuit for determining coordinates of a finger or the like, and (j)
An interface circuit in circuit communication with the coordinate determination circuit and the peripheral interface circuit for communicating the determined coordinates thereto, the pad surface having a preset default template graphic image associated therewith. A computer system comprising: (2) The computer according to (1) above, wherein the peripheral device interface circuit includes a data port for receiving identification data from an input / output device.
system. (3) The computer according to (1) above, wherein the peripheral device interface circuit includes a data port for receiving permission data from an input / output device.
system. (4) The computer system according to (3) above, further comprising a video display device connected to the video circuit and operable to display input / output device authorization data. (5) An input device for use in a computer system having a central processing unit (CPU) enclosed within a central enclosure, having an associated joystick circuit, the joystick circuit responsive to joystick operation. And at least two joysticks configured to generate a joystick signal and a touchpad having a pad surface and configured to generate a contact position signal in response to contact of the pad surface. , In circuit communication with the joystick circuit and the touchpad, configured to communicate to the CPU a data packet corresponding to the operation of the joystick, and further corresponding to a contact position on the pad surface by a finger, stylus, etc. CP data packet
An interface circuit configured to communicate with U. (6) The input device according to (4) above, wherein the interface circuit is further configured to communicate the unique input / output device permission data to the CPU.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall layout of the system of the present invention.

FIG. 2 is a block diagram showing the overall layout of the system of the present invention.

FIG. 3 is a schematic diagram showing details of a video digital-to-analog converter used in the system of the present invention.

FIG. 4 is a plan view of an input device of the present invention showing a touchpad with a default template, two joysticks, and a template overlay.

Figure 5: Template overlay is a template
FIG. 6 is a plan view of the input device of the present invention inserted in an overlay retainer.

FIG. 6 is an enlarged partial plan view showing a part of the input device of the present invention shown in FIG.

FIG. 7 is a cross-sectional view taken substantially along the plane indicated by lines 2D-2D in FIG.

8 is a cross-sectional view taken substantially along the plane indicated by lines 2E-2E in FIG.

9 is a cross-sectional view taken substantially along the plane indicated by lines 2F-2F in FIG.

FIG. 10: FIG. 4 with parts removed for clarity
FIG. 3 is a partial plan view of the input device of the present invention shown in FIG.

FIG. 11 is a bottom view of various examples of edges of a template overlay showing an identification pattern.

FIG. 12 is a bottom view of various examples of edges of a template overlay showing an identification pattern.

FIG. 13 is a bottom view of various examples of edges of a template overlay showing an identification pattern.

FIG. 14 is a bottom view of various embodiments of edges of a template overlay showing identification patterns.

FIG. 15 is a front view of the input device according to the present invention.

16 is a partial cross-sectional view taken along substantially the plane indicated by lines 2M-2M of FIG. 4, showing details of the joystick used in the input device of the present invention.

FIG. 17 is a block diagram showing an electric circuit of the input device of the invention.

[Explanation of symbols]

10 computer system 12 data processing unit 14 program cartridge 16 standard television receiver (TV) 18 input device 19 touchpad 20a joystick 20b joystick 21 stylus 22 serial data link 23 serial data line extension 24 RF video line 26 Edge Card Connector 28 Cartridge Connector 30 Central Processing Unit (CPU) 31 SYSTEM Bus 32 Audio / Video (A / V) Controller / Auxiliary Processor 33 System Memory 34 SYSTEM Bus 36 Input / Output Auxiliary Processor 38 Video DAC / NTSC encoder / RF modulator / Audio DAC 39 Expansion connector 40 ROM 42 Decoder 44 Chip selection signal

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Claims (6)

[Claims] 1. A video display device comprising: (a) a central processing unit (CPU); (b) a memory circuit in circuit communication with the CPU; (c) a circuit in circuit communication with the CPU and memory. A video circuit for generating an electrical signal corresponding to the visual image displayed above, and (d) a peripheral device interface circuit in circuit communication with the CPU for interfacing signals from an external device to the CPU. (E) a pad surface exposed to allow contact with a finger, stylus, etc., (f) a retainer for releasably securing the template overlay proximate the pad surface, g) The pad proximate to the pad surface and configured such that at least one of the electrical signals corresponds to the coordinates of the contact location. Or contact with the surface, or stylus in contact with the template overlay proximate to the pad surface, in response, such as the finger at least 1
A coordinate sensor for generating two electrical signals; (h) a rigid base proximate to the pad surface; (i) in circuit communication with the coordinate sensor, in contact with the pad surface, or A stylus that contacts the template overlay in close proximity to the pad surface,
A coordinate determining circuit for determining coordinates of a finger or the like; and (j) an interface circuit in circuit communication with the coordinate determining circuit and the peripheral device interface circuit for communicating the determined coordinates thereto, A computer system, wherein the pad surface has a preset default template graphic image associated with it. 2. The computer system of claim 1, wherein the peripheral device interface circuit includes a data port for receiving identification data from an input / output device. 3. The computer system of claim 1, wherein the peripheral device interface circuit includes a data port for receiving authorization data from an input / output device. 4. The computer system of claim 3, further comprising a video display device connected to the video circuit and operable to display input / output device authorization data. 5. An input device for use in a computer system having a central processing unit (CPU) enclosed within a central enclosure, the device having an associated joystick circuit, the joystick circuit operating a joystick. A touch having at least two joysticks configured to generate a joystick signal in response to a touch pad and configured to generate a touch position signal in response to touching the pad surface. A pad is in circuit communication with the joystick circuit and the touchpad and is configured to communicate a data packet corresponding to the operation of the joystick to the CPU, and further to a contact position on the pad surface by a finger, stylus, or the like Contact the CPU with the corresponding data packet Input apparatus characterized by comprising an interface circuit configured to so that. 6. The input device of claim 4, wherein the interface circuit is further configured to communicate unique input / output device authorization data to the CPU.