JPH0964655A - Semiconductor amplifier - Google Patents
Semiconductor amplifierInfo
- Publication number
- JPH0964655A JPH0964655A JP21444195A JP21444195A JPH0964655A JP H0964655 A JPH0964655 A JP H0964655A JP 21444195 A JP21444195 A JP 21444195A JP 21444195 A JP21444195 A JP 21444195A JP H0964655 A JPH0964655 A JP H0964655A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- amplification factor
- electrode
- semiconductor
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、通信装置や画像処
理装置等において、高周波数、小振幅の信号を増幅する
ために利用される半導体増幅装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor amplifier device used for amplifying a signal of high frequency and small amplitude in a communication device, an image processing device or the like.
【０００２】[0002]
【従来の技術】通信装置や画像処理装置等の小型化及び
軽量化に伴い、高周波数、小振幅の信号を増幅する半導
体増幅装置のニーズが高まっている。2. Description of the Related Art With the downsizing and weight reduction of communication devices and image processing devices, the need for semiconductor amplifying devices for amplifying signals of high frequency and small amplitude is increasing.
【０００３】以下、従来の半導体増幅装置について説明
する。A conventional semiconductor amplifier device will be described below.
【０００４】図６は基本的な反転増幅回路の回路図であ
る。図６において、１１はオペアンプ、１２は第１の抵
抗、１３は第２の抵抗であり、入力端子１４に入力され
る信号Ｖinは、信号グランド電位Ｖsgを中心として増幅
され出力端子１５から信号Ｖout として出力される。第
１の抵抗１２の抵抗値をＲ1 、第２の抵抗１３の抵抗値
をＲ2 とすると、図６に示す反転増幅回路の増幅率Ａ
は、次式のようになる。 Ａ＝Ｒ2 ／Ｒ1 …（１）FIG. 6 is a circuit diagram of a basic inverting amplifier circuit. In FIG. 6, 11 is an operational amplifier, 12 is a first resistor, and 13 is a second resistor. The signal V in input to the input terminal 14 is amplified around the signal ground potential V sg and is output from the output terminal 15. It is output as the signal V out . Assuming that the resistance value of the first resistor 12 is R 1 and the resistance value of the second resistor 13 is R 2 , the amplification factor A of the inverting amplifier circuit shown in FIG.
Is as follows: A = R 2 / R 1 (1)
【０００５】また、この反転増幅回路を半導体装置とし
て実現するとき、第１の抵抗１２及び第２の抵抗１３は
半導体基板１６上に形成される。半導体基板１６には基
板電位が与えられている。When the inverting amplifier circuit is realized as a semiconductor device, the first resistor 12 and the second resistor 13 are formed on the semiconductor substrate 16. A substrate potential is applied to the semiconductor substrate 16.
【０００６】[0006]
【発明が解決しようとする課題】ところが、従来の半導
体増幅装置には以下のような問題がある。However, the conventional semiconductor amplifier device has the following problems.
【０００７】図７は第２の抵抗１３の構造を示す断面図
である。第２の抵抗１３は半導体基板１６上に絶縁膜１
８を介して形成される。このような構造により、第２の
抵抗１３と半導体基板１６との間に分布容量１７ａ〜１
７ｄが生じている。また、第２の抵抗１３の単位面積当
たりの分布容量の大きさは、製造工程により一意に決定
される。FIG. 7 is a sectional view showing the structure of the second resistor 13. The second resistor 13 is an insulating film 1 on the semiconductor substrate 16.
8 is formed. With such a structure, the distributed capacitances 17a to 1 are provided between the second resistor 13 and the semiconductor substrate 16.
7d has occurred. The size of the distributed capacitance per unit area of the second resistor 13 is uniquely determined by the manufacturing process.
【０００８】図８は半導体増幅装置における増幅率の周
波数特性を示すグラフである。縦軸は増幅率、横軸は周
波数の対数である。実線は図６に示す従来の半導体増幅
装置における増幅率の周波数特性であり、破線は理想的
な半導体増幅装置における増幅率の周波数特性である。
また、斜線部Ｗは増幅する対象となる信号の周波数帯域
である。FIG. 8 is a graph showing the frequency characteristic of the amplification factor in the semiconductor amplifier device. The vertical axis represents the amplification factor, and the horizontal axis represents the logarithm of frequency. The solid line shows the frequency characteristic of the amplification factor in the conventional semiconductor amplifying device shown in FIG. 6, and the broken line shows the frequency characteristic of the amplification factor in the ideal semiconductor amplifying device.
The shaded area W is the frequency band of the signal to be amplified.
【０００９】半導体増幅装置の増幅率は、破線で示すよ
うに周波数にかかわらず一定であることが理想であり、
周波数帯域Ｗの信号は一律に増幅されることが望まし
い。しかし、実際には、高周波信号の場合、図７に示す
ような抵抗−半導体基板間に生じる分布容量の影響が無
視できなくなり、実線で示すように周波数の増加に伴い
増幅率も増加し、式（１）で表される増幅率Ａ以上の増
幅率になるという問題があった。また、分布容量が極め
て大きい場合、増幅率が極端に大きくなると共に信号の
位相のずれが大きくなることにより、最悪の場合には、
半導体増幅装置が発振状態に陥ってしまうという問題が
あった。Ideally, the amplification factor of the semiconductor amplifier device is constant regardless of the frequency, as indicated by the broken line,
It is desirable that signals in the frequency band W be uniformly amplified. However, in the case of a high-frequency signal, the effect of the distributed capacitance generated between the resistor and the semiconductor substrate as shown in FIG. 7 cannot be ignored, and the amplification factor increases as the frequency increases as shown by the solid line. There is a problem that the amplification factor is equal to or higher than the amplification factor A represented by (1). In addition, when the distributed capacitance is extremely large, the amplification factor becomes extremely large and the phase shift of the signal becomes large. In the worst case,
There is a problem that the semiconductor amplifying device falls into an oscillating state.
【００１０】前記の問題に鑑み、本発明は、所望の周波
数帯域において増幅率が一定であり且つ発振状態に陥る
ことのない半導体増幅装置を提供することを目的とす
る。In view of the above problems, it is an object of the present invention to provide a semiconductor amplifier device which has a constant amplification factor in a desired frequency band and does not fall into an oscillation state.
【００１１】[0011]
【課題を解決するための手段】前記の目的を達成するた
め、本発明は、増幅率を決定する抵抗の上又は下に電極
を配置して分布容量を生じさせることにより、増幅率の
周波数特性を改善するものである。In order to achieve the above-mentioned object, the present invention provides a frequency characteristic of the amplification factor by arranging an electrode above or below a resistor that determines the amplification factor to generate a distributed capacitance. To improve.
【００１２】具体的に請求項１の発明が講じた解決手段
は、半導体基板上に絶縁膜を介して形成された抵抗を備
え、入力される信号を前記抵抗の抵抗値により決定され
る増幅率で増幅して出力する半導体増幅装置を前提と
し、前記抵抗の上に絶縁膜を介して電極が配置されてお
り、前記抵抗と前記半導体基板との間に生じている分布
容量が信号周波数に対する増幅率の特性に与える影響
を、前記抵抗と前記電極との間に生じる分布容量によっ
て抑制する構成とするものである。Specifically, the means for solving the problems according to the invention of claim 1 is to include a resistor formed on a semiconductor substrate via an insulating film, and to amplify an input signal by a resistance value of the resistor. On the premise of a semiconductor amplifying device that amplifies and outputs a signal, an electrode is arranged on the resistor via an insulating film, and a distributed capacitance generated between the resistor and the semiconductor substrate is amplified with respect to a signal frequency. The influence of the rate characteristics on the distribution capacitance generated between the resistance and the electrode is suppressed.
【００１３】具体的に請求項２の発明が講じた解決手段
は、半導体基板上に絶縁膜を介して形成された抵抗を備
え、入力される信号を前記抵抗の抵抗値により決定され
る増幅率で増幅して出力する半導体増幅装置を前提と
し、前記絶縁膜のうち一部の絶縁膜の内部又は下側に電
極が配置されており、前記抵抗と前記半導体基板との間
に生じている分布容量が信号周波数に対する増幅率の特
性に与える影響を、前記抵抗と前記電極との間に生じる
分布容量によって抑制する構成とするものである。Specifically, the means for solving the problems according to the invention of claim 2 is to provide a resistor formed on a semiconductor substrate via an insulating film, and to amplify an input signal by a resistance value of the resistor. Assuming that a semiconductor amplifier device that amplifies and outputs in the above, an electrode is arranged inside or under a part of the insulating film of the insulating film, and a distribution generated between the resistor and the semiconductor substrate. The distributed capacitance generated between the resistance and the electrode suppresses the influence of the capacitance on the characteristic of the amplification factor with respect to the signal frequency.
【００１４】[0014]
（第１の実施形態）図１は本発明の第１の実施形態に係
る半導体増幅装置の構成を示す回路図である。図６に示
す従来の半導体増幅装置と同様に、１１はオペアンプ、
１２は第１の抵抗、１３は第２の抵抗であり、入力端子
１４に入力される信号Ｖinは、信号グランド電位Ｖsgを
中心として増幅され出力端子１５から信号Ｖout として
出力される。また、第１の抵抗１２及び第２の抵抗１３
は半導体基板１６上に形成される。(First Embodiment) FIG. 1 is a circuit diagram showing a configuration of a semiconductor amplifier device according to a first embodiment of the present invention. Like the conventional semiconductor amplifier device shown in FIG. 6, 11 is an operational amplifier,
Reference numeral 12 is a first resistor, 13 is a second resistor, and the signal V in input to the input terminal 14 is amplified around the signal ground potential V sg and output from the output terminal 15 as a signal V out . In addition, the first resistor 12 and the second resistor 13
Are formed on the semiconductor substrate 16.
【００１５】本実施形態では、出力端子１５に接続され
た電極１が第２の抵抗１３の上に配置されていることを
特徴とする。This embodiment is characterized in that the electrode 1 connected to the output terminal 15 is arranged on the second resistor 13.
【００１６】図２は図１に示す半導体増幅装置における
第２の抵抗１３の構造を示す断面図である。図７と同様
に、第２の抵抗１３は半導体基板１６上に絶縁膜１８を
介して形成されており、第２の抵抗１３と半導体基板１
６との間に分布容量１７ａ〜１７ｄが生じている。FIG. 2 is a sectional view showing the structure of the second resistor 13 in the semiconductor amplifier device shown in FIG. Similar to FIG. 7, the second resistor 13 is formed on the semiconductor substrate 16 with the insulating film 18 interposed therebetween.
The distributed capacitances 17a to 17d are generated between the electrodes 6 and 6.
【００１７】また、出力端子１５に接続された電極１が
第２の抵抗１３上に絶縁膜２を介して形成されており、
このような構造により電極１と第２の抵抗１３との間に
分布容量２ａ〜２ｄが生じている。この分布容量の電極
単位面積当たりの大きさは製造工程により一意に決定さ
れる。The electrode 1 connected to the output terminal 15 is formed on the second resistor 13 via the insulating film 2.
With such a structure, distributed capacitances 2a to 2d are generated between the electrode 1 and the second resistor 13. The size of this distributed capacitance per unit area of electrode is uniquely determined by the manufacturing process.
【００１８】図３は本実施形態に係る半導体増幅装置に
おける増幅率の周波数特性を示すグラフである。図３に
おいて、縦軸は増幅率、横軸は周波数の対数である。実
線は図１に示す本実施形態に係る半導体増幅装置におけ
る増幅率の周波数特性であり、破線は理想的な半導体増
幅装置における増幅率の周波数特性である。また、斜線
部Ｗは増幅する対象となる信号の周波数帯域である。FIG. 3 is a graph showing the frequency characteristics of the amplification factor in the semiconductor amplifier device according to this embodiment. In FIG. 3, the vertical axis represents the amplification factor and the horizontal axis represents the logarithm of frequency. The solid line shows the frequency characteristic of the amplification factor in the semiconductor amplifying device according to the present embodiment shown in FIG. 1, and the broken line shows the frequency characteristic of the amplification factor in the ideal semiconductor amplifying device. The shaded area W is the frequency band of the signal to be amplified.
【００１９】本実施形態に係る半導体増幅装置による
と、電極１を構成することにより、第２の抵抗１３と半
導体基板１６との間に生じる分布容量が増幅率の周波数
特性に対して及ぼす影響を抑制することができる。分布
容量２ａ〜２ｄの大きさは電極１の面積等により最適化
できるので、図３の実線が示すように、周波数帯域Ｗに
おける増幅率を一定にすることができる。また、本実施
形態に係る半導体増幅装置は電極１と第２の抵抗１３と
の間の分布容量２ａ〜２ｄによって低域通過特性を持つ
ことになり、周波数帯域Ｗよりも高い周波数において増
幅率が低下するので、発振状態に陥ることがなくなる。According to the semiconductor amplifying device of this embodiment, by configuring the electrode 1, the influence of the distributed capacitance generated between the second resistor 13 and the semiconductor substrate 16 on the frequency characteristic of the amplification factor is affected. Can be suppressed. Since the size of the distributed capacitances 2a to 2d can be optimized depending on the area of the electrode 1 and the like, the amplification factor in the frequency band W can be made constant as shown by the solid line in FIG. Further, the semiconductor amplifier device according to the present embodiment has a low-pass characteristic due to the distributed capacitances 2a to 2d between the electrode 1 and the second resistor 13, and the amplification factor is higher in the frequency higher than the frequency band W. Since it lowers, it does not fall into the oscillation state.
【００２０】（第２の実施形態）図４は本発明の第２の
実施形態に係る半導体増幅装置の構成を示す回路図であ
る。図１に示す第１の実施形態に係る半導体増幅装置と
同様に、１１はオペアンプ、１２は第１の抵抗、１３は
第２の抵抗であり、入力端子１４に入力される信号Ｖin
は、信号グランド電位Ｖsgを中心として増幅され出力端
子１５から信号Ｖout として出力される。また、第１の
抵抗１２及び第２の抵抗１３は半導体基板１６上に形成
される。(Second Embodiment) FIG. 4 is a circuit diagram showing a configuration of a semiconductor amplifier device according to a second embodiment of the present invention. Similar to the semiconductor amplifier device according to the first embodiment shown in FIG. 1, 11 is an operational amplifier, 12 is a first resistor, 13 is a second resistor, and a signal V in input to the input terminal 14 is input.
Is amplified around the signal ground potential V sg and output from the output terminal 15 as a signal V out . Further, the first resistor 12 and the second resistor 13 are formed on the semiconductor substrate 16.
【００２１】本実施形態では、出力端子１５に接続され
た電極３が第２の抵抗１３の下に配置されていることを
特徴とする。This embodiment is characterized in that the electrode 3 connected to the output terminal 15 is arranged below the second resistor 13.
【００２２】図５は図４に示す半導体増幅装置における
第２の抵抗１３の構造を示す断面図である。図５に示す
ように、半導体基板１６中に基板不純物とは異なる導電
性の不純物を注入することにより、電極３は形成されて
いる。このような構造により、電極３と第２の抵抗１３
との間の絶縁膜の一部１８ａに分布容量４ａ及び４ｂが
生じていると共に、第２の抵抗１３と半導体基板１６と
の間の絶縁膜の他部１８ｂに分布容量１７ａ及び１７ｂ
が生じている。また、電極３により生じている分布容量
の電極単位面積当たりの大きさは、製造工程により一意
に決定される。FIG. 5 is a sectional view showing the structure of the second resistor 13 in the semiconductor amplifier device shown in FIG. As shown in FIG. 5, the electrode 3 is formed by implanting into the semiconductor substrate 16 a conductive impurity different from the substrate impurity. With such a structure, the electrode 3 and the second resistor 13
Distributed capacitances 4a and 4b are generated in a portion 18a of the insulating film between the second resistor 13 and the semiconductor substrate 16, and distributed capacitances 17a and 17b are formed in another portion 18b of the insulating film between the second resistor 13 and the semiconductor substrate 16.
Is occurring. The size of the distributed capacitance generated by the electrode 3 per unit area of the electrode is uniquely determined by the manufacturing process.
【００２３】本実施形態に係る半導体増幅装置による
と、電極３を構成することにより、第２の抵抗１３と半
導体基板１６との間に生じる分布容量が増幅率の周波数
特性に対して及ぼす影響を抑制することができる。電極
３と第２の抵抗１３との間の分布容量の大きさは電極３
の面積等により最適化できるので、本実施形態に係る半
導体増幅装置における増幅率の周波数特性もまた、図３
のグラフの実線のようになる。すなわち、周波数帯域Ｗ
における増幅率を一定にすることができる。また、本実
施形態に係る半導体増幅装置は電極３と第２の抵抗１３
との間の分布容量４ａ及び４ｂによって低域通過特性を
持つことになり、周波数帯域Ｗよりも高い周波数におい
て増幅率が低下するので、発振状態に陥ることがなくな
る。According to the semiconductor amplifying device of this embodiment, by configuring the electrode 3, the influence of the distributed capacitance generated between the second resistor 13 and the semiconductor substrate 16 on the frequency characteristic of the amplification factor is affected. Can be suppressed. The size of the distributed capacitance between the electrode 3 and the second resistor 13 depends on the electrode 3
The frequency characteristics of the amplification factor in the semiconductor amplifier device according to the present embodiment are also shown in FIG.
It looks like the solid line in the graph. That is, the frequency band W
It is possible to keep the amplification factor at constant. In addition, the semiconductor amplifier device according to the present embodiment includes the electrode 3 and the second resistor 13.
Since the distributed capacitances 4a and 4b between and have a low-pass characteristic, and the amplification factor decreases at a frequency higher than the frequency band W, the oscillation state does not occur.
【００２４】なお、本実施形態では電極３を半導体基板
１６中に形成したが、第２の抵抗１３と半導体基板１６
との間の絶縁膜１８内に形成しても同様の効果が得られ
る。Although the electrode 3 is formed in the semiconductor substrate 16 in this embodiment, the second resistor 13 and the semiconductor substrate 16 are formed.
The same effect can be obtained by forming it in the insulating film 18 between and.
【００２５】[0025]
【発明の効果】請求項１の発明に係る半導体増幅装置に
よると、増幅率を決定する抵抗の上に電極が配置されて
おり、抵抗と電極との間に生じる分布容量によって、抵
抗と半導体基板との間に生じている分布容量が信号周波
数に対する増幅率の特性に与える影響を抑制することが
できるので、所望の周波数帯域における増幅率を一定に
できると共に半導体増幅装置が発振状態に陥るのを防ぐ
ことができる。According to the semiconductor amplifying device of the first aspect of the present invention, the electrode is arranged on the resistor that determines the amplification factor, and the distributed capacitance generated between the resistor and the electrode causes the resistor and the semiconductor substrate. Since it is possible to suppress the influence of the distributed capacitance generated between and on the characteristic of the amplification factor with respect to the signal frequency, it is possible to keep the amplification factor in a desired frequency band constant and prevent the semiconductor amplification device from falling into an oscillation state. Can be prevented.
【００２６】請求項２の発明に係る半導体増幅装置によ
ると、増幅率を決定する抵抗と半導体基板との間の絶縁
膜のうち一部の絶縁膜の内部又は下側に電極が配置され
ており、抵抗と電極との間に生じる分布容量によって、
抵抗と半導体基板との間に生じている分布容量が信号周
波数に対する増幅率の特性に与える影響を抑制すること
ができるので、所望の周波数帯域における増幅率を一定
にできると共に半導体増幅装置が発振状態に陥るのを防
ぐことができる。According to the semiconductor amplifying device of the second aspect of the invention, the electrode is arranged inside or under a part of the insulating film between the resistor for determining the amplification factor and the semiconductor substrate. , The distributed capacitance generated between the resistor and the electrode
Since the influence of the distributed capacitance generated between the resistor and the semiconductor substrate on the characteristics of the amplification factor with respect to the signal frequency can be suppressed, the amplification factor in the desired frequency band can be made constant and the semiconductor amplification device can oscillate. Can be prevented from falling into.
【図１】本発明の第１の実施形態に係る半導体増幅装置
の構成を示す回路図である。FIG. 1 is a circuit diagram showing a configuration of a semiconductor amplifier device according to a first embodiment of the present invention.
【図２】本発明の第１の実施形態に係る半導体増幅装置
の第２の抵抗１３の構造を示す断面図である。FIG. 2 is a sectional view showing a structure of a second resistor 13 of the semiconductor amplifier device according to the first embodiment of the present invention.
【図３】本発明の実施形態に係る半導体増幅装置におけ
る増幅率の周波数特性を示すグラフである。FIG. 3 is a graph showing a frequency characteristic of an amplification factor in the semiconductor amplifier device according to the embodiment of the present invention.
【図４】本発明の第２の実施形態に係る半導体増幅装置
の構成を示す回路図である。FIG. 4 is a circuit diagram showing a configuration of a semiconductor amplifier device according to a second embodiment of the present invention.
【図５】本発明の第２の実施形態に係る半導体増幅装置
の第２の抵抗１３の構造を示す断面図である。FIG. 5 is a sectional view showing the structure of a second resistor 13 of the semiconductor amplifier device according to the second embodiment of the present invention.
【図６】従来の半導体増幅装置の構成を示す回路図であ
る。FIG. 6 is a circuit diagram showing a configuration of a conventional semiconductor amplifier device.
【図７】従来の半導体増幅装置の第２の抵抗１３の構造
を示す断面図である。FIG. 7 is a sectional view showing a structure of a second resistor 13 of a conventional semiconductor amplifier device.
【図８】従来の半導体増幅装置における増幅率の周波数
特性を示すグラフである。FIG. 8 is a graph showing frequency characteristics of amplification factor in a conventional semiconductor amplifier device.
１ 電極 ２ 絶縁膜 ２ａ，２ｂ，２ｃ，２ｄ 分布容量 ３ 電極 ４ａ，４ｂ 分布容量 １１ オペアンプ １２ 第１の抵抗 １３ 第２の抵抗 １４ 入力端子 １５ 出力端子 １６ 半導体基板 １７ａ，１７ｂ，１７ｃ，１７ｄ 分布容量 １８ 絶縁膜 １８ａ 絶縁膜の一部 １８ｂ 絶縁膜の他部 DESCRIPTION OF SYMBOLS 1 electrode 2 insulating film 2a, 2b, 2c, 2d distributed capacitance 3 electrodes 4a, 4b distributed capacitance 11 operational amplifier 12 first resistor 13 second resistor 14 input terminal 15 output terminal 16 semiconductor substrate 17a, 17b, 17c, 17d distribution Capacity 18 Insulating film 18a Part of insulating film 18b Other part of insulating film
Claims (2)
た抵抗を備え、入力される信号を前記抵抗の抵抗値によ
り決定される増幅率に従って増幅して出力する半導体増
幅装置において、 前記抵抗の上に絶縁膜を介して電極が配置されており、 前記抵抗と前記半導体基板との間に生じる分布容量が信
号周波数に対する増幅率の特性に与える影響を、前記抵
抗と前記電極との間に生じる分布容量によって抑制する
ことを特徴とする半導体増幅装置。1. A semiconductor amplifier device, comprising a resistor formed on a semiconductor substrate via an insulating film, for amplifying an input signal according to an amplification factor determined by a resistance value of the resistor and outputting the amplified signal. An electrode is disposed on the above with an insulating film interposed therebetween, and the influence of the distributed capacitance generated between the resistance and the semiconductor substrate on the characteristics of the amplification factor with respect to the signal frequency is increased between the resistance and the electrode. A semiconductor amplifier device characterized by being suppressed by the generated distributed capacitance.
た抵抗を備え、入力される信号を前記抵抗の抵抗値によ
り決定される増幅率に従って増幅して出力する半導体増
幅装置において、 前記絶縁膜のうち一部の絶縁膜の内部又は下側に電極が
配置されており、 前記抵抗と前記半導体基板との間に生じる分布容量が信
号周波数に対する増幅率の特性に与える影響を、前記抵
抗と前記電極との間に生じる分布容量によって抑制する
ことを特徴とする半導体増幅装置。2. A semiconductor amplifier device, comprising a resistor formed on a semiconductor substrate via an insulating film, for amplifying an input signal according to an amplification factor determined by a resistance value of the resistor and outputting the amplified signal. An electrode is arranged inside or under a part of the insulating film of the film, and the influence of the distributed capacitance generated between the resistor and the semiconductor substrate on the characteristic of the amplification factor with respect to the signal frequency is A semiconductor amplifier device, characterized in that it is suppressed by a distributed capacitance generated between the electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21444195A JP3174248B2 (en) | 1995-08-23 | 1995-08-23 | Semiconductor amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21444195A JP3174248B2 (en) | 1995-08-23 | 1995-08-23 | Semiconductor amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0964655A true JPH0964655A (en) | 1997-03-07 |
| JP3174248B2 JP3174248B2 (en) | 2001-06-11 |
Family
ID=16655833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21444195A Expired - Fee Related JP3174248B2 (en) | 1995-08-23 | 1995-08-23 | Semiconductor amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3174248B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010081249A (en) * | 2008-09-25 | 2010-04-08 | Toshiba Corp | Stabilization circuit and semiconductor device having stabilization circuit |
| JP2013070403A (en) * | 2012-11-12 | 2013-04-18 | Toshiba Corp | Semiconductor device having stabilization circuit |
-
1995
- 1995-08-23 JP JP21444195A patent/JP3174248B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010081249A (en) * | 2008-09-25 | 2010-04-08 | Toshiba Corp | Stabilization circuit and semiconductor device having stabilization circuit |
| US8427248B2 (en) | 2008-09-25 | 2013-04-23 | Kabushiki Kaisha Toshiba | Stabilization network and a semiconductor device having the stabilization network |
| JP2013070403A (en) * | 2012-11-12 | 2013-04-18 | Toshiba Corp | Semiconductor device having stabilization circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3174248B2 (en) | 2001-06-11 |
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