JPH0944377A - Endless loop detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an endless loop detector which prevents the system down by monitoring a bus cycle signal even in the case of the absence of code fetch on a bus and detecting an endless loop without erroneous reaction upon a semipermanent loop which is normally operated. SOLUTION: The just preceding bus cycle signal is stored in a count-up bus cycle register 11 of a loop detection circuit 1 and is compared with the present bus cycle signal by a count-up bus cycle comparator 12, and a count-up signal is generated in the case of coincidence but a reset signal is generated in the other case, and a loop counter 21 of an endless loop detection circuit 2 is counted up in response to supply of the count-up signal and is initialized in response to supply of the reset signal; and when the counted value is equal to or larger than a certain value, an endless loop detection signal is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an infinite loop detecting device, and more particularly to an infinite loop detecting device that detects an infinite loop generated by a failure of a computer program or a system and outputs an infinite loop detecting signal to the system.

[0002]

2. Description of the Related Art When a program is executed by a microcomputer, an endless loop for repeatedly executing a specific portion of the program may be caused due to a defect of the program or a failure of the system.

[0003] If such an endless loop occurs, the processing of the microcomputer will not proceed and the system will be down.

Japanese Patent Application Laid-Open No. Sho 62-106552 discloses a technique for monitoring a program address being executed and detecting an infinite loop when the same program address is looped a predetermined number of times or more.

[0005]

The above-described conventional infinite loop detecting apparatus monitors a program address being executed, but uses a central processing unit (hereinafter referred to as a CPU) having a code cache therein. In the system, a program is stored inside the CPU, and the program address being executed may not come out of the CPU. When the program stored in the CPU loops, an infinite loop is detected. There is a problem that can not be.

[0006] In addition, since an infinite loop is determined only by the number of loops, an infinite loop due to a failure is determined even if the program is in a normal state in which the program loops semi-permanently until the user of the system performs any input. Had the problem that

[0007] An object of the present invention is to provide a loop (I / O cycle, etc.) even when a code is not looped by a program stored in the CPU and a code etch does not appear on the bus.
The CPU monitors a signal flowing on the bus during the bus cycle executed by the CPU (hereinafter referred to as a bus cycle signal), and detects an infinite loop due to a failure without erroneously reacting to a semi-permanent loop which is a normal operation. To provide an infinite loop detection device which is useful for preventing system down.

[0008]

According to a first aspect of the present invention, an infinite loop detecting apparatus monitors a bus cycle signal flowing on a bus during a bus cycle to determine a loop state in a single bus cycle. The loop detection means generates a count-up signal when it is in a loop state and generates a reset signal at other times, and performs a count operation in response to the supply of the count-up signal and is initialized in response to the supply of the reset signal. And an infinite loop detecting means for generating an infinite loop detection signal when the count value becomes equal to or more than a predetermined value.

According to a second aspect of the present invention, there is provided an infinite loop detecting apparatus for monitoring a bus cycle signal flowing on a bus during a bus cycle, and detecting a loop state in a bus cycle sequence including a plurality of continuous bus cycles. Loop detection means for generating a count-up signal when in a loop state and generating a reset signal otherwise.
And an infinite loop detecting means configured to perform a counting operation in response to the supply of the count-up signal, to be initialized in response to the supply of the reset signal, and to generate an infinite loop detection signal when the count value becomes equal to or greater than a predetermined value. Have been.

An infinite loop detecting device according to a third aspect of the present invention comprises
Alternatively, in the infinite loop detecting device according to the second invention, when a bus cycle signal designated in advance is detected, a counting unnecessary loop detecting means for supplying a reset signal for initializing the infinite loop detecting means to the infinite loop detecting means is included. It is composed of

According to a fourth aspect of the present invention, there is provided an infinite loop detecting apparatus comprising:
Alternatively, in the infinite loop detection device according to the second or third invention, the infinite loop detection device is configured to include an operation control unit for individually setting whether the operation of the loop detection unit and the countless loop detection unit is enabled or disabled.

According to a fifth aspect of the present invention, there is provided an infinite loop detecting apparatus comprising:
Alternatively, in the infinite loop detecting apparatus according to the second, third or fourth aspect of the present invention, the infinite loop detecting apparatus includes setting means for externally setting a constant value of the infinite loop detecting means.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of an infinite loop detecting apparatus according to the present invention.
It is a block diagram showing an embodiment.

As shown in FIG. 1, an infinite loop detecting apparatus according to a first embodiment includes a loop detecting circuit 1 for determining and detecting a loop in a single bus cycle and generating a count-up signal; The count value of the infinite loop detection circuit 2 that counts the number of occurrences and generates an infinite loop detection signal when the count reaches a certain number or more, and the count value of the infinite loop detection circuit 2 when a bus cycle signal corresponding to a predetermined count unnecessary loop arrives A countless loop detection circuit 3 that generates a reset signal for resetting the clock, a bus cycle signal corresponding to a designated countless loop is set in advance in the countless loop detection circuit 3, and a fixed numerical value is set in the infinite loop detection circuit 2. And a loop detection circuit 1 and a countless loop detection circuit 3
And a control register unit 4 for enabling and disabling the respective operations.

The loop detection circuit 1 is currently executing the count-up bus cycle register 11 which always holds the immediately preceding bus cycle signal, and the bus cycle signal held in the count-up bus cycle register 11. A count-up bus cycle comparator 12 is provided for supplying a count-up signal when comparing and matching the signals of the bus cycle, and supplying a reset signal when the signals are different.

The infinite loop detecting circuit 2 is a reset signal OR unit 22 for generating a logical sum of the reset signals output from the loop detecting circuit 1 and the counting unnecessary loop detecting circuit 3.
And a loop counter 21 which counts up by a count-up signal output from the loop detection circuit 1 and is reset by a reset signal from a reset signal OR unit 22 to generate an infinite lube detection signal when the count value exceeds a predetermined value. And

The count-unnecessary loop detecting circuit 3 includes a plurality of reset bus cycle registers 31a, 31b,... Capable of setting a reset bus cycle signal, which is a bus cycle signal corresponding to a designated count-unnecessary loop, and reset bus cycles. Are provided with a plurality of reset bus cycle comparators 32a, 32b,... Which respectively generate reset signals when the registers 31a, 31b,...

The control register section 4 includes a reset bus cycle setting register 41 for externally setting a reset bus cycle signal to a plurality of reset bus cycle registers 31a, 31b,..., An external count-up bus cycle comparator 12, An enable / disable control register 42 for enabling / disabling the plurality of reset bus cycle comparators 32a, 32b,..., And a loop count data setting register 4 for externally setting the count data of the loop counter 21
3 and 3.

When a bus cycle is executed by the CPU, the count-up bus cycle register 11 holds the bus cycle signal.

Next, when the bus cycle is executed by the CPU, the bus cycle signal held in the count-up bus cycle register 11 and the bus cycle signal currently being executed are compared with the count-up bus cycle comparator 1.
Compare with 2.

At this time, the count-up bus cycle comparator 12 outputs a count-up signal to the infinite loop detection circuit 2 if the comparison results match, and outputs a count-up signal to the infinite loop detection circuit 2 if the comparison results do not match. To output a reset signal.

In the countless loop detection circuit 3, the CP
Each time U executes a bus cycle, the contents of the plurality of reset bus cycle registers 31a, 31b,... Are compared with the currently executed bus cycle signal. A reset signal is output to the circuit 2.

In the infinite loop detection circuit 2, the loop counter 21 is counted up by the count-up signal output from the loop detection circuit 1, and when the count value becomes equal to or more than the value set in the loop count data setting register 43, That is, when a single bus cycle is repeated a certain number of times or more, an infinite loop detection signal is output. However, when a reset signal is output from the loop detection circuit 1 or the countless loop detection circuit 3, the loop counter 21 is reset and the single bus cycle is repeated less than a certain number of times, and the specified normal operation is predicted in advance. An infinite loop detection signal for a certain semi-permanent loop is not generated.

Here, the count-up bus cycle comparator 12 and the plurality of reset bus cycle comparators 32
a, 32b,... can output a count-up signal or a reset signal when enabled in the enable / disable control register 42 (setting can be performed for each comparator). If it is set, the comparison operation is stopped.

As described above, in the first embodiment, by detecting an infinite repetition of a loop composed of a single bus cycle signal by a bus cycle signal, the loop is executed by a program stored in the CPU. Even if the code fetch does not appear on the bus, an infinite lube can be detected, and a bus cycle signal corresponding to the countless loop is set in advance to detect the countless loop. By eliminating the need for counting, an infinite loop can be efficiently detected without erroneous reaction to a semi-permanent loop which is a normal operation, which can be used to prevent a system down.

FIG. 2 shows a second embodiment of the infinite loop detecting device according to the present invention.
It is a block diagram showing an embodiment.

Here, successive bus cycles are represented by B1, B2, B
3, ... In the first embodiment, B1 → B1 → B1 →.
Infinite loop was detected. Therefore, in the second embodiment, it is possible to detect an infinite loop in a plurality of continuous bus cycles, such as B1, B2, B3, B1, B2, B3, B1, B2, B3, and so on.

As shown in FIG. 2, the infinite loop detection apparatus according to the second embodiment includes a loop detection circuit 100 for determining and detecting a loop of a plurality of consecutive bus cycles and generating a count-up signal, and a loop detection circuit 100. The count value of the infinite loop detection circuit 2 which counts the number of occurrences and generates an infinite loop detection signal when the number of occurrences exceeds a certain number, and the count value of the infinite loop detection circuit 2 when a bus cycle signal corresponding to a previously designated counting unnecessary loop arrives. Unnecessary loop detection circuit 3 for generating a reset signal for resetting the signal and a bus cycle signal corresponding to a predetermined unnecessary loop detection circuit are set in the unnecessary loop detection circuit 3 and a fixed numerical value is set in the infinite loop detection circuit 2. And a control register unit 4 for enabling and disabling the loop detection circuit 100 and the counting unnecessary loop detection circuit 3, respectively. It is constituted comprise.

The loop detection circuit 100 has a bus cycle register 1 which always holds the immediately preceding bus cycle signal.
14a, a bus cycle register 114b that always holds the two previous bus cycle signals, and a bus cycle register 114 that always holds the three previous bus cycle signals
, and a plurality of bus cycle registers 114a, 114b, 114c,..., which are held in order, and the respective bus cycle registers 114a, 114b, 114.
, and bus cycle comparators 115a, 115b, 115c,... for comparing the bus cycle signals held in c,... with the currently executed bus cycle signal, and bus cycle registers 114a, 114b, 114c,. A bus cycle register signal selector 113 for selecting one bus cycle signal to be set in the count-up bus cycle register 111 from a plurality of bus cycle signals, and a bus cycle register signal selector 113
A count-up bus cycle register 111 capable of writing the supplied bus cycle signal or resetting the written bus cycle signal.
And compares the bus cycle signal held in the count-up bus cycle register 111 with the currently executed bus cycle signal, and outputs a count-up signal to the infinite loop detection circuit 2 when they match. From the comparison result of the count-up bus cycle comparator 112 and the bus cycle comparators 115a, 115b, 115c,..., The write signal / reset signal of the bus cycle signal to the count-up bus cycle register 111 and the bus cycle register signal selector 113 A bus cycle signal candidate that issues a data select signal and a reset signal to the infinite loop detection circuit 2 to form an infinite loop (an infinite loop is formed by repeating a bus cycle signal sequence consisting of one or more continuous bus cycle signals) This sequence is composed Refers to one of the candidates of the bus cycle signal) comprises determining the bus cycle comparison result decision unit 116.

FIG. 3 shows a bus cycle comparison result determiner 116.
FIG. 3 is a block diagram showing an example of the configuration of FIG.

Bus cycle comparison result determiner 1 shown in FIG.
16 is each bus cycle comparator 115a, 115b, 11
A decoder 1161 which detects a bus cycle comparator which receives an output signal from 5c,... And outputs a coincidence signal and outputs a data select signal for selecting a coincident bus cycle signal from the bus cycle register signal selector 113
And each bus cycle comparator 115a, 115b, 115
OR circuit 1 for creating a logical sum of the output signals from c,.
162, an inverter 1165 for inverting the output signal of the OR circuit 1162, an AND circuit 1163 and a flip-flop 1164, which are set by receiving a coincidence signal from the OR circuit 1162 to generate a write signal and self-hold. The write signal generation circuit 1167 counts the number of consecutive bus cycles, and is reset by the count-up signal from the count-up bus cycle comparator 112 or the output signal of the inverter 1165 to reset the count value to a constant value (of the bus cycle register). Counter 1166 which is reset by generating a reset signal when
It is comprised including. This reset signal also resets write signal generation circuit 1167.

In this manner, bus cycle comparison result determiner 116 generates a data select signal, a write signal, and a reset signal.

Here, in order to count successive bus cycles by the counter 1166, an address strobe signal indicating the start of a bus cycle or a ready signal indicating the end of a bus cycle can be used.

Next, the operation of generating a data select signal, a write signal and a reset signal output from bus cycle comparison result determiner 116 will be described with reference to FIG.

The bus cycle comparison result determiner 116 determines a bus cycle signal in a bus cycle signal sequence forming an infinite loop, selects a candidate, and if it is inappropriate, searches for another candidate.

The data select signal is generated each time from the decoder 1161 when at least one of the bus cycle comparators outputs a coincidence signal, and forms a loop with the coincident bus cycle signal by the bus cycle register signal selector 113. And count-up bus cycle register 111
To supply.

A write signal is generated when at least one of the bus cycle comparators first outputs a coincidence signal after resetting of the write signal generation circuit 1167, and thereafter, until a reset signal is supplied. Maintain state.
Writing by the write signal is used as a 0 → 1 state change signal.

The reset signal is generated when the count value becomes equal to or more than the number of the bus cycle registers without resetting the counter 1166.

The reset signal is generated even if all of the continuous bus cycle signals equal in number to the bus cycle registers coincide with one of the bus cycle signals stored in the bus cycle register. This is the case when no match signal is supplied from the device 112.

This is because even if a bus cycle signal candidate for an infinite loop configuration is detected and written to the count-up bus cycle register 111 for a period of time, the number of consecutive bus cycle signals equal to the number of bus cycle registers after that is detected. If the bus cycle signal candidate is not detected, it is excluded from the bus cycle signal candidates for the infinite loop.

This is also because the number of bus cycle registers is limited, so that detection of an infinite loop of a continuous number of bus cycle signals larger than this number is temporarily excluded.

Therefore, in such a case, the reset signal is supplied to the infinite loop detection circuit 2 and other circuits to cancel the bus cycle signal candidate for the infinite loop configuration.

In this manner, the bus cycle comparison result determiner 116 determines a true infinite loop configuration target bus cycle signal from the infinite loop configuration target bus cycle signal detected by each bus cycle comparator.

The infinite loop detection circuit 2 has a reset signal OR unit 22 for generating a logical sum of the reset signals output from the loop detection circuit 1 and the counting unnecessary loop detection circuit 3.
And a loop counter 21 which counts up by a count-up signal output from the loop detection circuit 1 and is reset by a reset signal from a reset signal OR unit 22 to generate an infinite lube detection signal when the count value exceeds a predetermined value. And

The countless loop detection circuit 3 includes a plurality of reset bus cycle registers 31a, 31b,... Capable of setting a reset bus cycle signal, which is a bus cycle signal corresponding to a designated countless loop, in advance. Are provided with a plurality of reset bus cycle comparators 32a, 32b,... Which respectively generate reset signals when the registers 31a, 31b,...

Further, the control register unit 4 has a reset bus cycle setting register 41 for externally setting a reset bus cycle signal to the plurality of reset bus cycle registers 31a, 31b, ... An enable / disable control register 42 for controlling enable / disable of the plurality of reset bus cycle comparators 32a, 32b, ... And a loop count data setting register 4 for setting count data of the loop counter 21 from the outside.
3 and 3.

Now, as an example, B1 → B2 → B1 →
A case where a loop is performed in a cycle of two buses like B2 → B1 ... will be described.

First, when the bus cycle B1 is executed,
This bus cycle signal is transmitted to the bus cycle register 114a.
Is held. Next, when the bus cycle B2 is executed, the bus cycle signal of the bus cycle register 114a is held in the bus cycle register 114b, and the bus cycle signal of B2 is held in the bus cycle register 114a. Next, when the bus cycle B1 is executed, the bus cycle signal matches the content of the bus cycle register 114b, so that a match signal is output from 115b.

At this time, the bus cycle comparison result determiner 1
Reference numeral 16 outputs a data select signal for selecting a bus cycle signal of the bus cycle register 114 b to the bus cycle register signal selector 113 and a write signal of a bus cycle signal for the count-up bus cycle register 111. Here, the write signal to the count-up bus cycle register 111 is not output again until a reset signal to the count-up bus cycle register 111 described later is output.

Count-up bus cycle register 11
1 holds the bus cycle signal of the bus cycle register 114b selected by the bus cycle register signal selector 113 by the write signal of the bus cycle comparison result determiner 116. Thereafter, the count-up bus cycle comparator 112 outputs a count-up signal each time the bus cycle B1 is executed.

When the bus cycle signal does not match any of the contents of the bus cycle registers 114a, 114b, 114c,..., The counter 1166 is reset. This is because in order to form an infinite loop, successive bus cycle signals must be followed by a match signal.

When the bus cycle is the bus cycle register 1
14a, 114b, 114c,... Are executed as many times as the number of bus cycle registers 114a, 114b, 114c,. When the count-up signal is not output from 112, the bus cycle comparison result determiner 116 outputs a reset signal to the count-up bus cycle register 111 and the infinite loop detection circuit 2 to cancel the bus cycle signal candidate.

In the counting unnecessary loop detecting circuit 3, C
Each time the PU executes a bus cycle, the contents of the plurality of reset bus cycle registers 31a, 31b,... Are compared with the currently executed bus cycle signal. A reset signal is output to the circuit 2.

In the loop counter 21, the loop detection circuit 1
The counter is counted up by a count-up signal output from the counter, and when the count becomes equal to or more than the value set in the loop count data setting register 43, an infinite loop detection signal is output. However, when a reset signal is output from the loop detection circuit 1 or the counting unnecessary loop detection circuit 3, the loop counter 21 resets the counter.

Here, the count-up bus cycle comparator 12 and the plurality of reset bus cycle comparators 32
a, 32b,... can output a count-up signal or a reset signal when enabled (disabled for each comparator) in the enable / disable control register 42.

As described above, in the second embodiment, by detecting an infinite repetition of a loop composed of a plurality of bus cycle signals by a bus cycle signal, the loop is executed by a program stored in the CPU. Therefore, even when the code fetch does not appear on the bus, an infinite lube can be detected.

Further, by setting a bus cycle signal corresponding to the counting unnecessary loop in advance and detecting the counting unnecessary loop and making it unnecessary to count, it does not erroneously react to a semi-permanent loop which is a normal operation, and efficiently. In addition, an infinite loop can be detected to prevent the system from going down.

[0059]

As described above, the infinite loop detection device of the present invention monitors the bus cycle executed by the CPU and detects the infinite loop without erroneously reacting to the semi-permanent loop which is a normal operation. Therefore, it is possible to quickly cope with an infinite loop due to a program defect, a system failure, or the like, and to prevent the system from going down.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a first embodiment of an infinite loop detection device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of the infinite loop detection device of the present invention.

FIG. 3 is a block diagram showing a configuration of an example of a bus cycle comparison result determiner.

[Explanation of symbols]

1, 100 loop detecting circuit 2 infinite loop detecting circuit 3 counting unnecessary loop detecting circuit 4 control register section 11, 111 count-up bus cycle register 12, 112 count-up bus cycle comparator 21 loop counter 22 reset signal OR unit 31a, 31b reset Bus cycle registers 32a, 32b Reset bus cycle comparator 41 Reset bus cycle setting register 42 Enable / disable control register 43 Loop count data setting register 113 Bus cycle register signal selector 114a, 114b, 114c Bus cycle register 115a, 115b, 115c Bus Cycle comparator 116 bus cycle comparison result determiner 1161 decoder 1162 OR circuit 1163 AND circuit 1164 Lip prop 1165 inverter 1166 counter 1167 write signal generating circuit

Claims (5)

[Claims] 1. A bus cycle signal flowing on a bus during a bus cycle is monitored to determine a loop state in a single bus cycle, and a count-up signal is generated during the loop state to generate a count-up signal. A loop detecting means for generating a reset signal, and performing a counting operation in response to the supply of the count-up signal, initializing the supply in response to the supply of the reset signal, and outputting an infinite loop detection signal when the count value becomes a certain value or more. An infinite loop detecting means for generating the infinite loop. 2. A bus cycle signal flowing on the bus during a bus cycle is monitored to determine a loop state in a bus cycle sequence composed of a plurality of continuous bus cycles, and to count up when the loop state occurs. A loop detecting means for generating a signal and generating a reset signal at other times, and performing a counting operation in response to the supply of the count-up signal, and is initialized in response to the supply of the reset signal, and the count value becomes equal to or more than a certain value. And an infinite loop detection means for generating an infinite loop detection signal when an error occurs. 3. A counting unnecessary loop detecting means for supplying a reset signal for initializing the infinite loop detecting means to the infinite loop detecting means when a bus cycle signal designated in advance is detected. 3. The infinite loop detection device according to 1 or 2. 4. An infinite loop detecting apparatus according to claim 1, further comprising an operation control means for individually setting whether the loop detecting means and the countless loop detecting means can operate or not. . 5. An infinite loop detecting apparatus according to claim 1, further comprising a setting means for externally setting a constant value of the infinite loop detecting means.