JPH0934794A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a random number generator suitable for installation inside a semiconductor memory device with simple and small scale circuit configuration by inputting data to be used inside the semiconductor memory device and outputting the parity arithmetic value of those data as random number data. SOLUTION: A random number generation circuit 10 is composed of a parity arithmetic circuit. Based on inputted data, the random number generation circuit 10 outputs the data of '0' or '1' at random. Concretely, address data are received from an address buffer 1, parity arithmetic is performed to these data by the parity arithmetic circuit and as a result, parity output data P are supplied to a data switching circuit 30. The random number generation circuit 10 is usually composed of plural counters or frequency dividers but in this case, since the parity arithmetic circuit is used, the random number can be easily generated in small circuit scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a data protection function. By providing the random number generation circuit in the semiconductor memory device, the generated random number can be used to give the semiconductor memory device an additional function of preventing data duplication and theft.

[0002]

2. Description of the Related Art Normally, a random number generating circuit is composed of a plurality of counters and frequency dividers. The specific configuration of the random number generation circuit varies depending on the type of random number to be generated, the required amount of random numbers, etc., but it is necessary to configure the circuit using multiple elements even when generating relatively simple random numbers. However, the circuit scale must be large to some extent.

On the other hand, RO such as mask ROM and EPROM
In M, the memory contents can be read relatively easily by designating an address and sequentially accessing the three areas. Therefore, by reading the stored contents of all the storage areas in the ROM, it is possible to duplicate the ROM having exactly the same contents or to tamper the stored contents.

[0004]

When a random number generation circuit is provided in a semiconductor memory device, it is desirable to realize the random number generation circuit with a circuit configuration as small as possible in order to prevent an increase in circuit scale. Therefore, a normal random number generation circuit using a plurality of counters and frequency dividers is not suitable for being provided in a semiconductor device.

Further, the ROM as described above may store information having confidential contents such as a certain program and special data. Therefore, from the viewpoint of maintaining the confidentiality of the stored contents, it is required to prevent or make it difficult to read the stored data for the purpose of duplication, falsification and the like.

Therefore, a first object of the present invention is to provide a random number generation circuit having a simple and small-scale circuit configuration, which is suitable for being provided in a semiconductor memory device. A second object of the present invention is to provide a semiconductor memory device capable of preventing unauthorized reading for the purpose of copying stored data by utilizing the random numbers generated by the random number generation circuit. is there.

[0007]

In view of the above problems, the invention according to claim 1 is configured such that data used in a semiconductor memory device is input and a parity operation value of the data is output as random number data. did.

According to a second aspect of the present invention, a data storage unit, a random number generation circuit for outputting the parity operation values of a plurality of data used in the semiconductor storage device as random number data, and reading from the data storage unit. An output circuit which receives the stored data and the random number data output by the random number generation circuit, selects the stored data in a normal read state, selects the random number data in an illegal read state, and outputs the random number data to the outside. It is configured to have.

According to the third aspect of the present invention, an address match detection circuit that stores an address that is not accessed in the normal read state and detects whether the input address matches the stored address and an address match detection circuit. Is detected, an output data control unit is provided for generating a control signal for causing the output circuit to output random number data.

[0010]

According to the invention described in claim 1, the semiconductor memory device outputs the parity operation value of the data used in the input semiconductor memory device as random number data.

According to the second aspect of the invention, the random number generation circuit (10) outputs the parity operation value of a plurality of data used in the semiconductor memory device as random number data to the output circuit (3).
0).

As a result, the output circuit (30) selects the storage data stored in the data storage unit (3) in the normal read state and outputs it to the outside, and selects the random number data in the illegal read state to the outside. Output.

According to the third aspect of the invention, the address coincidence detection circuit stores an address that is not accessed in the normal read state, detects whether the input address coincides with the stored address, and outputs the output data control section ( 20) generates a control signal for causing the output circuit to output the random number data when an address match is detected.

[0014]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. First Embodiment First, a first embodiment of the present invention will be described. FIG.
1 shows a configuration of a semiconductor memory device according to a first example of the present invention.

The address buffer 1 sequentially generates internal address signals and supplies them to the row decoder 2, column decoder 4 and random number generation circuit 10. The row decoder 2 selects one of the plurality of row address lines of the memory cell array 3 based on the control signal output from the control circuit 5.

The memory cell array 3 has a plurality of row addresses.
Line, column address line, and memory cell
Data. The column decoder 4 is controlled by the control circuit 5.
The memory cell array 3 is duplicated based on the output control signal.
Select any of several column address lines. Row Deco
Memory cell selected by the decoder 2 and the column decoder 4
The data stored in No. 3 is output to the output buffer 6. memory
A part of the stored data D read from the cell array 3
Data C is an output buffer via the data switching circuit 30.
6 is input. The control circuit 5 includes a row decoder 2 and
The control signals are supplied to the RAM decoders 4, respectively, and
Whether to read the output data control circuit 20 to be illegal or not
Related control data S ₁Supply the necessary control to each part.
A control signal is also supplied to control the entire device.

The random number generation circuit 10 is composed of a parity calculation circuit. That is, the random number generation circuit randomly outputs "0" or "1" data based on the input data. More specifically, it receives address data from the address buffer 1, performs a parity operation on the address data, and supplies the result to the data switching circuit 30. The random number generation circuit is usually composed of a plurality of counters, frequency dividers, etc., but in the present invention, by using the parity calculation circuit, it is possible to easily generate a random number with a small circuit scale.

FIG. 2 shows the configuration of the random number generation circuit 10. As shown in the figure, the random number generation circuit 10 is formed by connecting seven exclusive OR (EOR) circuits in cascade, and outputs even parity as a calculation result. That is, "1" is output when the number of data "1" included in the input 8-bit address data A _0a -A _3b is odd, and "0" is output when the number of data "1" is even. Is output.

FIGS. 3A and 3B show truth tables of input / output data of the random number generating circuit 10. 3A, the input A _0a -A _3a , the output Y _3a , and the input A _0a -A _3a
The relationship between _0b- A _3b and output Y _3b is shown in FIG. 3 (b).
_3a -Y _3b and shows the relationship between the output P.

As can be understood from this truth table, an odd number (1 _,, 8) of 8-bit address data A _0a -A _3b .
When the data of 3, 5, 7) is “1”, the parity output data P becomes “1”, and the even number (0, 2, 4,
When the data 6 and 8) is "1", the parity output data P is "0". In this way, the random number generation circuit 1
If a plurality of data that are not related to each other are input to the input of 0, the output can be regarded as a kind of random number data unrelated to the storage data of the memory cell array 3, and the random number generation circuit is realized by the parity operation circuit. It In the present embodiment, the parity operation circuit has 8 inputs,
The number of input data is not limited to this.

The output data control circuit 20 supplies the data switching signal S ₂ to the data switching circuit 30 based on the control signal S ₁ from the control circuit 5. The data switching signal S ₂ becomes “1” (H level) when the memory cell array 3 is in an illegal read state, and the random number generation circuit 1
The output data of 0 is output to the outside via the output buffer 6. On the other hand, when the memory cell array 3 is in a normal read state, it becomes "0" (L level) and the stored data of the memory cell array 3 is output to the outside as it is.

FIG. 4 shows the configuration of the output data control circuit 20. As shown, the output data control circuit 20 includes a switch circuit 21 including transistors Tr _{1 to} Tr ₅ connected in series, and inverter circuits 22 and 23 that function as buffers and the like.

FIG. 5 shows the control signal S ₁ and the transistor Tr.
The relationship between _1- Tr ₅ , the node N _1, and the control signal S ₂ is shown. The threshold voltage (V _T ) of the P-channel transistors Tr ₁ and Tr ₂ is about −1.1V, and the threshold voltage of the N-channel transistor Tr ₃ is about 0.7V. It is turned on / off with V _cc + 3V as a threshold value. The gates of the transistors Tr ₄ and Tr ₅ are given the voltage V _cc, is always in the ON state.
However, the transistors Tr ₄ and Tr ₅ are the transistors T
The current drivability is lower than that of r ₁ -Tr ₃ , and the value of the current flowing in the ON state is small.

Now, the control signal S from the control circuit 5₁Is V
_ccIn the following cases, the transistor Tr₁The board (sub
Straight) voltage does not exceed the gate voltage
State, and as a result, the transistor Tr_Two, Tr_ThreeAlso off
Is in a state. At this time, the transistor Tr_FourAnd Tr_FiveIs
Since it is in the ON state, node N₁Becomes "0" and control
Signal S_TwoAlso becomes "0". Control signal S₁Voltage is V_ccTo
When it exceeds, firstly the transistor Tr₁Is turned on,
Transistor Tr_TwoAnd Tr_ThreeAlso starts to shift to the ON state
However, at this point node N is still₁Remains "0"
is there. Then control signal S₁Voltage increases and V_cc+ 3V
Transistor Tr₁-Tr_ThreeIs turned on.
You. In this case, all transistors are turned on
But transistor Tr_FourAnd Tr_FiveCurrent is small
Therefore, the transistor Tr₁-Tr _ThreeCurrent flowing through
Most of the current flows into the inverter circuit 22 side, and the node N₁
Becomes "1". As a result, the output signal S_TwoIs also "1"
You.

By the above operation, the output data control circuit 2
0 indicates that the control signal S ₁ supplied from the control circuit 5 is V _cc +3
When the voltage is V or less, “0” is set, and the control signal S ₁ is V _cc + 3V
Outputs as the control signal S ₂ to "1" when the least.

The data switching circuit 30 receives the output data C of the memory cell array 3 from the column decoder 4 and the parity output data P from the random number generation circuit 10.
In response to the data switching signal S ₂ from the output data control circuit 20 and selects and outputs the selected signal as data D _x .

An embodiment of the data switching circuit 30 is shown in FIG.
FIG. 6A shows the truth table, and FIG. 6B shows the truth table. The data switching circuit 30 is composed of two AND circuits 30a and 30b, a NOT circuit 30c, and an OR circuit 30d. The storage data C and the inverted signal of the control signal S ₂ generated by the NOT circuit 30c are input to one AND circuit 30a, and the parity output data P and the control signal S ₂ are input to the other AND circuit 30b. To be done. The outputs of the two AND circuits are input to the OR circuit 30d, and the OR circuit 30d selectively outputs either the storage data C or the parity output data P according to the control signal S ₂ . That is, as can be seen from FIG. 6B, when the data switching signal S ₂ is “0”, the memory cell array 3
The stored data C is output as it is as data D _x . On the other hand, when the data switching signal S ₂ is “1”, the storage data C of the memory cell array 3 is not output,
Instead, the parity output data P from the random number generation circuit 10
Is output as data D _x .

Another embodiment of the data switching circuit 30 is shown.
7 (a) and its truth table are shown in FIG. 7 (b).
The data switching circuit 30 shown in FIG. 7A has three Ns.
OR circuits 30e, 30f, 30g, and NOT circuit 3
It is composed of 0h. The NOR circuit 30e stores the memory data.
C and control signal S_TwoIs input to the NOR circuit 30f.
Depends on the parity output data P and the NOT circuit 30h.
Generated control signal S _TwoThe inverted signal of is input. Two
The outputs of the NOR circuits 30e and 30f are
The NOR circuit 30g receives the stored data C and the
Control signal S_TwoIn response to the
Output selectively. In this case as well, data switching
Signal S_TwoIf the value is “0”, the stored data C
Switching signal S_TwoIf is “1”, the parity output data
Data P is data D_xIs output as Column decoder
4 and data D output from the data switching circuit 30
Data output from D_xVia the output buffer 6
It is output to the outside.

Next, the flow of the actual operation will be described. First, in a normal operation state (hereinafter, referred to as “normal state”), the control circuit 5 supplies a predetermined control signal or the like to each unit, and the data stored at a predetermined address of the memory cell array 3 is output to the output buffer. 6 is output. A part of the data passes through the data switching circuit 30. Further, the control circuit 5 outputs a control signal S ₁ (V _cc +) for outputting the stored data of the memory cell array 3 as it is to the outside.
3V or less) is supplied to the output data control circuit 20,
The output data control circuit 20 supplies the data switching signal S ₂ of “0” to the data switching circuit 30. Therefore, the data switching circuit 30 supplies the storage data C of the memory cell array 3 to the output buffer 6 as the data D _x (see FIGS. 6B and 7B). As a result, the data stored in the memory cell array 3 is output from the output buffer 6 to the outside. The above is the operation in the normal state.

Next, the operation when the memory cell array 3 is illegally read will be described. In this embodiment, it is determined outside the semiconductor memory device whether or not illegal reading is performed. That is, the other part in the system in which the semiconductor memory device is mounted monitors the presence / absence of illegal reading, and outputs a signal indicating whether illegal reading is being performed to the external input terminal of the semiconductor memory device. Is supplied to the control circuit 5 via. Control circuit 5
When receiving a signal indicating that the illegal reading is being performed (hereinafter, referred to as “abnormal state”), the control signal S ₁ (V _cc + 3V) is supplied to the output data control circuit 20. In response to this, the output data control circuit 20 supplies a high level (“1”) as the data switching signal S ₂ to the data switching circuit 30. Therefore, the data switching circuit 30 operates in the memory cell array 3
The output of the stored data C is prohibited, and the parity output data P from the random number generation circuit 10 is supplied to the output buffer 6 as the data D _x instead. As a result, the output buffer 6 outputs the parity output data P to the outside instead of the data stored in the memory cell array 3. In this way, it is prohibited to directly output the storage data of the memory cell array 3 at the time of illegal reading, and the copy of the storage data is prevented. The above is the operation in the abnormal state. In the above example, the signal indicating whether the unauthorized reading is performed is input from the outside of the semiconductor memory device and supplied to the output data control circuit 20 via the control circuit 5. The configuration may be such that the output data control circuit 20 is directly supplied without going through the control circuit 5.

After that, when the signal indicating that the illegal reading is being performed is stopped, the control circuit 5 outputs the data stored in the memory cell array 3 as it is so as to return to the normal operation. The signal S ₁ is supplied to the output data control circuit 20. As a result, the data switching circuit 30 outputs the storage data C, and the output buffer 6 outputs the storage data of the memory cell array 3 to the outside as usual. Second Embodiment Next, a second embodiment of the present invention will be described. In the first embodiment, the control circuit 5 generates the control signal S ₁ on the basis of a signal indicating an illegal read input from the outside, and in response thereto, the output data control circuit 20 sends a switching signal to the data switching circuit 30. It was supplying S ₂ . That is, the instruction to prohibit the output of the storage data of the memory cell array 3 is supplied from the outside of the semiconductor memory device. In contrast,
In the second embodiment, the presence / absence of illegal reading is detected by the output data control circuit 20 in the semiconductor memory device. In particular,
The output data control circuit 20 stores a predetermined address value in advance. When the address is accessed from outside, it is determined that the illegal reading is being performed, and the switching signal S ₂ for selecting the parity output data is selected. (“1”) is output to the data switching circuit 30.

The reason for having such a structure is as follows. Normally, when storing specific data in ROM, etc.,
Data is not necessarily written to all addresses in the ROM. Although it depends on the amount of data to be stored, there are usually some addresses that are not used, that is, no data is written (hereinafter referred to as “unused addresses”). That is, when this ROM is normally used, unused addresses are not accessed. However, a person who wants to read out the stored contents of the ROM for the purpose of copying or the like will access the stored data at all addresses. Therefore, such an unused address is stored in advance, and if the address is accessed, it is determined that an illegal read will be performed, and the parity output data unrelated to the stored data is output to the outside. Of.

FIG. 8 shows the configuration of the output data control circuit according to the second embodiment. As shown in the figure, the output data control circuit 20 of this embodiment has an address match detection section 24 and a latch circuit 25. The address coincidence detection unit 24 is configured by connecting combination circuits of enhancement type transistors, depletion type transistors, and inverter circuits by the number of address signal lines (A ₀ -A ₁₉ ). The latch circuit 25 has a NOR circuit 25a, NOT circuits 25b and 25c, and a capacitor C.

Next, the operation will be described. Address coincidence detection circuit 24, when the storage address value (determined by the arrangement of transistors in the address coincidence circuit) and the input address (determined by the address signal A ₀ -A ₁₉₎ are matched outputs "0". Now, it is assumed that the storage address of the address coincidence detection circuit 24 is such that the address signal A ₀ is “1”, A ₁ is “0”, ... A ₁₉ is “0”. At this time, if any one of the address signals A ₀ -A ₁₉ does not match, the transistor at that location is turned off, and the output S ₃ becomes "1". On the other hand, when the input address coincides with the memory address, all of the transistors are turned on, the output S ₃ is "0". Once an address match is detected, the latch circuit 25 continues to output "0" regardless of which address is input, unless the power is turned off.

Normally, when the power is turned on, the memory address and input
No match with address, signal S ₆Becomes "0"
Is the signal S_Four, S_FiveIs also "0", so signal S₆Is instant
It becomes "1" in a while. Therefore, the state of address mismatch
Then, the control signal S_TwoIs "0". Then enter
If the input address matches the stored address, that is, the input address
The dress is the memory address (A₀Is "1", A₁But
"0", ... A₁₉Is equal to “0”), the signal S_ThreeIs
"0", signal S_FourBecomes "1", so the signal S₆Is
It becomes "0". As a result, the control signal S_TwoIs "1"
You. Once the signal S₆When the signal becomes "0", the signal S_FiveIs "1"
Therefore, after that, the signal S_FourSignal S regardless of the level of
₆Keeps "0", and the control signal S_TwoIs always "1"
You. This control signal S_TwoEnters the data switching circuit 30
Memory cell array data and parity output
Switching with data is performed. As a result, the input address
Memory matches the memory address, then memory
The data stored in the cell array is not output and the parity is always output.
Force data is output to the outside. Therefore, the user can copy
Access an address that is not normally accessed for purposes such as
Random number data of the parity operation circuit is output
Therefore, illegal reading for the purpose of copying stored data
Can be prevented. In addition, in the example of FIG.
The coincidence detection circuit 24 stores one specific address, but
It can also be configured to store a number of addresses
You. In that case, transistors T connected in series₀₀-T
₁₉₁Multiple storage units consisting of
I just need.Other embodiments In the above embodiment, the input of the random number generation circuit 10 is input.
Uses the address data output from the dress buffer 1
However, the input of the random number generation circuit 10 is a semiconductor
It is possible to utilize various other data used in the storage device.
And it is possible.

The structure of another example is shown in FIGS. FIG. 9 shows a case where the storage data of the memory cell array 3 is used as the input of the random number generation circuit 10.
Shows a case where a plurality of control data used in the control circuit 5 are used as inputs of the random number generation circuit 10. Also,
FIG. 11 shows a case where the address data from the address buffer 1, the storage data of the memory cell array 3 and any control data are used as inputs to the random number generation circuit 10. As described above, the parity operation circuit in the present invention functions as a random number generation circuit, and the input data is used as a random number generation source. Therefore, it can be said that the input data does not have to have a specific relationship, and it is preferable that the data have no correlation with each other from the viewpoint of generating random numbers. Therefore, it is possible to use various data other than the above examples.

Further, in the above embodiment, only one bit of the output data from the memory cell array is switched to the parity output data and output to the outside, but a plurality of parity operation circuits, data switching circuits and the like are provided. By doing so, it may be configured to switch the parity output data for more data.

[0038]

As described above, in the present invention, since the semiconductor memory device outputs the parity operation value as random number data, the random number generating circuit is provided in the semiconductor memory device despite the simple and small-scale circuit configuration. Is equivalent to the case where is provided.

Further, when it is determined that the semiconductor memory device is being illegally read, the random number data generated by the random number generation circuit is output to the outside instead of the stored data. It is possible to prevent illegal reading for the purpose of copying stored data.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor memory device according to a first example of the present invention.

FIG. 2 is a diagram showing a configuration of a random number generation circuit.

FIG. 3 is a diagram showing inputs and outputs of the random number generation circuit shown in FIG.

FIG. 4 is a diagram showing a configuration example of an output data control circuit.

5 is a diagram showing an input / output relationship of the output data control circuit shown in FIG.

FIG. 6 is a diagram showing a configuration example of a data switching circuit, and
It is a figure which shows the input / output.

7A and 7B are diagrams showing another configuration example of a data switching circuit and its input / output.

FIG. 8 is a diagram showing another configuration example of the output data control circuit.

FIG. 9 is a diagram showing the configuration of another embodiment of the semiconductor memory device according to the present invention.

FIG. 10 is a diagram showing the configuration of another embodiment of the semiconductor memory device according to the present invention.

FIG. 11 is a diagram showing the configuration of another embodiment of the semiconductor memory device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Address buffer 2 ... Row decoder 3 ... Memory cell array 4 ... Column decoder 5 ... Control circuit 6 ... Output buffer 10 ... Random number generation circuit 20 ... Output data control circuit 30 ... Data switching circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomohiro Nakayama 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takanori Shiga 1015, Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture Fujitsu Limited ( 72) Inventor Yoshiyuki Fujita 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (3)

[Claims] 1. A semiconductor memory device, wherein data used in the semiconductor memory device is input and a parity operation value of the data is output as random number data. 2. A data storage section (3), a random number generation circuit (10) for outputting parity operation values of a plurality of data used in a semiconductor storage device as random number data, and a random number generation circuit read from the data storage section. An output circuit (30) for inputting the stored data and the random number data output from the random number generation circuit, selecting the stored data in the normal read state, and selecting the random number data in the illegal read state and outputting the random number data to the outside. A semiconductor memory device comprising: 3. An address match detection circuit that stores an address that is not accessed in a normal read state and detects whether or not an input address matches the memory address, and the output circuit when an address match is detected. 4. The semiconductor memory device according to claim 3, further comprising an output data control unit (20) that generates a control signal for causing the random number data to be output to the.