JPH09331692A - Motor driving circuit - Google Patents

Motor driving circuit

Info

Publication number
JPH09331692A
JPH09331692A JP8168696A JP16869696A JPH09331692A JP H09331692 A JPH09331692 A JP H09331692A JP 8168696 A JP8168696 A JP 8168696A JP 16869696 A JP16869696 A JP 16869696A JP H09331692 A JPH09331692 A JP H09331692A
Authority
JP
Japan
Prior art keywords
channel
time
transistor
trs
mosfets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8168696A
Other languages
Japanese (ja)
Inventor
Shoji Oiwa
昭二 大岩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nidec Advanced Motor Corp
Original Assignee
Japan Servo Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Servo Corp filed Critical Japan Servo Corp
Priority to JP8168696A priority Critical patent/JPH09331692A/en
Publication of JPH09331692A publication Critical patent/JPH09331692A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To reduce the time difference between the off-delays of MOSFETs, by connecting respectively the respective gate signals of a pair of P- and N- channel MOSFETs subjected to simultaneous energization with the emitter and collector sides of one PNP transistor. SOLUTION: Connecting respectively the outputs of an IC 2 for outputting the changeover signals of the energization directions of a motor coil 9 with low-frequency complying transistors(TRs) 31a, 31b, their outputs are connected respectively both with the bases of PNP small signal TRs 30a, 30b for driving the gates of MOSFETs and with the bases of TRs 32b, 32a to connect respectively the collectors of the TRs 32b, 32a with the bases of the TRs 30b, 30a. Also the emitters of the TRs 30a, 30b are connected respectively with the gates of P-channel MOSFETs 5a, 5b, and their collectors are connected respectively with the gates of N-channel MOSFETs 6a, 6b. Turning on or off alternately the TRs 30a, 30b by the IC 2, the time difference between the off-delays of the MOSFETs is reduced. By the on-off of the TRs 30a, 30b, the direction of the energization of a motor coil 9 is inverted. Thereby, a motor driving circuit is simplified to reduce its cost.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ファン等に使用される
DCブラシレスモータの駆動回路に関し、特にモータコ
イルエネルギーの有効活用が可能なMOSFETのゲー
トドライブと貫通電流防止とを有する駆動回路を供給す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a DC brushless motor used in a fan or the like, and more particularly to a drive circuit having a MOSFET gate drive capable of effectively utilizing motor coil energy and a through current prevention. To do.

【0002】[0002]

【従来の技術】図3は単相ブラシレスDCモータコイル
にMOSFETによるバイポーラ通電の従来例を示す回
路であり、図3において、1はモータに内蔵されている
マグネットロータの回転位置を検出するホール素子、2
はコイル通電方向の切り替え信号を出力するIC、3は
モータコイルの通電方向切り替え時に信号伝達系の微少
な時間ずれにより発生する上下アームMOSFET同時
オンによる電源短絡現象を防止するための無通電時間を
発生するデッドタイム回路、4a、4bはトランジスタ
による信号反転回路、5a、5bはPチャンネルMOS
FETでゲートはトランジシタ4a及び4bのコレクタ
に接続されている、6a、6bは NチャンネルMOS
FET、9はモータコイル、7a,7b,7c,7dは
モータコイル通電方向切り替え時にモータコイルから発
生する誘導電圧をバイパスさせるダイオード、8はその
誘導エネルギーを蓄積するコンデンサである。
2. Description of the Related Art FIG. 3 is a circuit showing a conventional example of bipolar current conduction by a MOSFET in a single-phase brushless DC motor coil. In FIG. 3, 1 is a Hall element for detecting the rotational position of a magnet rotor incorporated in the motor. Two
Is an IC for outputting a switching signal of the coil energizing direction, and 3 is a non-energizing time for preventing a power source short circuit phenomenon caused by a simultaneous turn-on of the upper and lower arm MOSFETs caused by a slight time lag of the signal transmission system when switching the energizing direction of the motor coil. Dead-time circuits that occur 4a, 4b are signal inversion circuits by transistors, 5a, 5b are P-channel MOS
In FET, the gate is connected to the collectors of the transistors 4a and 4b, 6a and 6b are N-channel MOS
FET 9 is a motor coil, 7a, 7b, 7c and 7d are diodes for bypassing the induced voltage generated from the motor coil when the motor coil energization direction is switched, and 8 is a capacitor for storing the induced energy.

【0003】図4は図3の各部の信号波形を示すタイム
チャートである。図4により図3に示す回路の動作につ
いて説明する。通常運転時には、マグネットロータの回
転によりホール素子1の出力は4−1の波形となり、こ
の位置信号によりIC2は4−2a、4−2bのような
相補の信号を出力する。デッドタイム回路3の出力は4
−3a、4−3bのようにオンでTDの時間遅れを持
ち、4−5a、4−5bはPチャンネルMOSFETの
オン、オフ時間でTL1のオフ遅れ時間を示し、4−6
a、4−6bはNチャンネルMOSFETのオン、オフ
時間でTL2のオフ遅れ時間を示すもので、Pチャンネル
MOSFETのオフ時間はそれ自体の入力容量による遅
れとゲートドライブNPNスイッチングトランジスタ4
a、4bの飽和領域による蓄積時間の遅れが加わり大き
くなる。4−8はコンデンサの充放電電流を示すもの
で、正方向がモータコイルの誘導エネルギーを電流とし
てコンデンサに充電している期間である。また、負方向
は充電されたエネルギーをコンデンサから放電電流とし
てモータコイルに供給している期間で、この間は電源か
らは電流の供給は不用で効率が良くなる。また、デッド
タイム回路3については、22a、22bの抵抗と、2
3a、23bのコンデンサで時間遅れ回路を構成し、コ
ンパレータ24a、24bにて比較し、デッドタイムを
発生させている。また、トランジスタ21a、21bは
コンデンサ23a、23bの電荷を引き抜くためのもの
である。
FIG. 4 is a time chart showing signal waveforms at various parts in FIG. The operation of the circuit shown in FIG. 3 will be described with reference to FIG. During normal operation, the Hall element 1 outputs a waveform of 4-1 due to the rotation of the magnet rotor, and the position signal causes the IC 2 to output complementary signals such as 4-2a and 4-2b. The output of dead time circuit 3 is 4
-3a and 4-3b have a time delay of TD when they are on, and 4-5a and 4-5b show an off delay time of TL1 by the on and off times of the P-channel MOSFET.
Reference characters a and 4-6b indicate the ON delay time of the N-channel MOSFET and the OFF delay time of TL2. The OFF time of the P-channel MOSFET depends on the delay due to its own input capacitance and the gate drive NPN switching transistor 4.
The delay of the accumulation time due to the saturation regions of a and 4b is added and becomes large. Reference numeral 4-8 indicates a charge / discharge current of the capacitor, and the positive direction is a period during which the capacitor is charged with the induced energy of the motor coil as a current. In the negative direction, the charged energy is supplied from the capacitor to the motor coil as a discharge current. During this period, the current supply from the power supply is unnecessary and the efficiency is improved. The dead time circuit 3 includes resistors 22a and 22b and 2
A time delay circuit is formed by the capacitors 3a and 23b and compared by the comparators 24a and 24b to generate a dead time. Further, the transistors 21a and 21b are for extracting charges from the capacitors 23a and 23b.

【0004】[0004]

【発明が解決しようとする課題】従来の単相ブラシレス
モータのバイポーラ通電では、以上の様にPチャンネル
MOSFETのオフ時間が、NチャンネルMOSFET
に比べて長く、その時間差TL1−TL2の間モータコイ
ルエネルギーは、例えば、PチャンネルMOSFET5
aとモータコイルそしてダイオード7bとで形成される
ル−プで循環して消費され、その循環電流は通電切り替
えの位置で生じるためモータトルクに寄与しない。ま
た、デッドタイム時間TDは無通電時間であり、Pチャ
ンネルMOSFETのオフ時間のハ゛ラツキを考慮して決定
するが必要以上長くすることはモータ出力低下につなが
る。本発明は上記のような問題点を簡素化した回路構成
で解消することを目的とするものである。
As described above, in the bipolar conduction of the conventional single-phase brushless motor, the off time of the P-channel MOSFET is changed to the N-channel MOSFET.
Is longer than that of the motor coil energy during the time difference TL1-TL2.
It is circulated and consumed by the loop formed by a, the motor coil, and the diode 7b, and the circulating current does not contribute to the motor torque because it is generated at the switching position of energization. Further, the dead time TD is a non-energized time, and is determined in consideration of the variation of the off time of the P-channel MOSFET, but making it longer than necessary leads to a reduction in the motor output. An object of the present invention is to solve the above problems with a simplified circuit configuration.

【0005】[0005]

【課題を解決するための手段】本発明はPチャンネルM
OSFETとNチャンネルMOSFETとのオフ遅れ時
間TL1、TL2の差を極力少なくして、モータコイル循環
電流を低減し、コンデンサへの充電量を増やす。これを
簡略化した回路で実現するために、同時に通電する一対
のPチャンネルMOSFETとNチャンネルMOSFE
Tのそれぞれのゲート信号を、1個のPNPトランジス
タのエミツタ側にPチャンネルMOSFETを、コレク
タ側にNチャンネルMOSFETを接続し、且つ該トラ
ンジスタを活性領域動作としたものである。また、デッ
ドタイムは、通電方向切り替え信号を、低周波増幅用の
比較的コレクタ容量の大きなトランジスタにベース電流
を大きく流すことでトランジスタのオフ時間を遅らせて
発生させる。
The present invention is a P channel M
The difference between the off delay times TL1 and TL2 between the OSFET and the N-channel MOSFET is minimized to reduce the motor coil circulating current and increase the amount of charge to the capacitor. In order to realize this with a simplified circuit, a pair of P-channel MOSFETs and N-channel MOSFEs that conduct electricity at the same time are provided.
Each of the gate signals of T is connected to a P-channel MOSFET on the emitter side and an N-channel MOSFET on the collector side of one PNP transistor, and the transistor is operated in the active region. The dead time is generated by delaying the off-time of the transistor by causing a large base current to flow in the transistor for relatively low-frequency amplification, which has a relatively large collector capacitance, as the conduction direction switching signal.

【0006】[0006]

【作 用】上述の如き構成においては、MOSFETの
ゲートドライブに安価であるバイポーラトランジスタを
使用するが、スイッチング動作のためコレクタ電流の飽
和期間中にベースに少数キャリアが蓄積され、オフ時に
それが放電されるまでコレクタ電流が流れ続ける蓄積時
間が存在する。しかし、エミツタホロワとして使用すれ
ばオフ時の遅れはほとんど生じない。また、一般的にP
チャンネルMOSFETはNチャンネルMOSFETよ
りも入力容量が大きく、スイッチング遅れ時間も大きい
ので、PチャンネルMOSFETはエミッタホロワで早
く、NチャンネルMOSFETはコレクタ接続で若干遅
くドライブすることで、両者のオフ時間の差を軽減でき
る。また、ICからの2つの通電切り替え信号により、
それぞれのトランジスタのベース電流を大きく流し、ト
ランジスタ自体のオフ遅れ時間を30〜40μs発生さ
せる。その信号で前述のMOSFETのゲート駆動用ト
ランジスタのベースに、別のトランジスタでたすき掛け
に接続することで、強制的にオフ時間を設けられ相切り
替え毎にデッドタイム時間が生じ上下アームによる電源
短絡現象は生じない。
[Operation] In the configuration described above, an inexpensive bipolar transistor is used for the MOSFET gate drive, but minority carriers are accumulated in the base during the saturation period of the collector current due to the switching operation, and it is discharged when it is off. There is an accumulation time during which the collector current continues to flow until it is removed. However, if used as an Emitter Follower, there is almost no delay when turned off. Also, in general, P
Since the channel MOSFET has a larger input capacitance and a longer switching delay time than the N-channel MOSFET, the P-channel MOSFET is driven faster by the emitter follower, and the N-channel MOSFET is driven slightly later by the collector connection to reduce the difference between the off times of the two. it can. Also, by the two energization switching signals from the IC,
The base current of each transistor is made to flow largely, and the off delay time of the transistor itself is generated for 30 to 40 μs. By connecting the base of the gate drive transistor of the above-mentioned MOSFET with that signal in a crossing manner with another transistor by that signal, a dead time is created for each phase switching by forcibly providing an off time and a power short circuit phenomenon due to the upper and lower arms. Does not occur.

【0007】[0007]

【実施例】以下図面によって本発明の実施例を説明す
る。図1は本発明の一実施例を示す回路図である。図1
において1はモータに内蔵されているマグネットロータ
の回転位置を検出するホール素子、2はコイル通電方向
の切り替え信号を出力するICで図3に示す従来技術の
回路と同じであるが、該IC2の出力は低周波増幅用ト
ランジスタ31a、31bに接続され、該トランジスタ
31a,31bの出力は、MOSFETのゲートをドラ
イブするPNPの小信号トランジスタ30a、30bの
ベースに接続され、又、トランジスタ31a,31bの
出力は、それぞれトランジスタ32b,32aのベース
に接続され、そのコレクタはそれぞれトランジスタ30
b,30aに接続され、該小信号トランジスタ30a,
30bのエミツタはPチャンネルMOSFET5a,5
bのゲートに、コレクタはNチャンネルMOSFET6
a,6bのゲートにそれぞれ接続されており、モータコ
イル通電方向の切り替え信号を出力するIC2により、
トランジスタ30aと30bは交互にオン、オフされ
る。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG.
1 is a Hall element that detects the rotational position of a magnet rotor built in the motor, and 2 is an IC that outputs a switching signal for the coil energization direction, which is the same as the circuit of the prior art shown in FIG. The outputs are connected to low frequency amplification transistors 31a and 31b, the outputs of the transistors 31a and 31b are connected to the bases of small signal transistors 30a and 30b of the PNP that drive the gates of the MOSFETs, and the outputs of the transistors 31a and 31b. The outputs are connected to the bases of the transistors 32b and 32a, respectively, and the collectors of the outputs are connected to the transistor 30b, respectively.
b, 30a, the small signal transistor 30a,
The emitter of 30b is a P-channel MOSFET 5a, 5
The gate of b, the collector is N-channel MOSFET6
IC2, which is connected to the gates of a and 6b, and outputs a switching signal for the motor coil energization direction,
The transistors 30a and 30b are alternately turned on and off.

【0008】トランジスタ30aがオン状態ではMOS
FET5aと6aがオンとなりコイル9に左から右の方
向に通電されて、その後、トランジスタ30aがオフす
ると30bがオンとなり、MOSFET5bと6bがオ
ンとなり、モータコイル9には前とは逆方向に通電され
る。
When the transistor 30a is on, the MOS
The FETs 5a and 6a are turned on, the coil 9 is energized in the left to right direction, and when the transistor 30a is turned off, 30b is turned on, the MOSFETs 5b and 6b are turned on, and the motor coil 9 is energized in the opposite direction to the previous direction. To be done.

【0009】PチャンネルMOSFETのオフ時間はこ
れ自体の入力容量で決まり、本回路でオフ時間遅れTL1
は約20μs、NチャンネルMOSFETにはPNPト
ランジスタの遅れも加わりTL2は約15μsとなり、時
間差が約5μsと従来の半分以下になる。また、時間差
を更に少なくするには、PNPトランジスタのコレクタ
にコレクタ抵抗と並列にコンデンサを挿入して、Nチャ
ンネルMOSFETのオフ時間を遅くすればよい。 こ
の時間差の低減により、モータコイルへの循環電流の時
間が減り、MOSFETに並列に接続されたダイオード
7aと7cまたは7bと7dを経由してモータコイルエ
ネルギーは有効的にコンデンサ8にチャージされ、次の
通電方向切り替え時にモータコイルに供給される。
The off-time of the P-channel MOSFET is determined by its own input capacitance, and in this circuit the off-time delay TL1
Is about 20 μs, the delay of the PNP transistor is added to the N-channel MOSFET, and TL2 is about 15 μs, and the time difference is about 5 μs, which is less than half of the conventional value. To further reduce the time difference, a capacitor may be inserted in parallel with the collector resistance in the collector of the PNP transistor to delay the off time of the N-channel MOSFET. By reducing this time difference, the time of the circulating current to the motor coil is reduced, and the motor coil energy is effectively charged in the capacitor 8 via the diodes 7a and 7c or 7b and 7d connected in parallel to the MOSFET, Is supplied to the motor coil when the energizing direction is switched.

【0010】図2は図1の各部の信号波形を示すタイム
チャートである。図において2−2a、2bはトランジ
スタ31a,31bの出力波形で、tはトランジスタの
遅れ時間であり、2−3a,3bはゲートドライブPN
Pトランジスタ30a,30bのベース信号で、tと同
じ時間であるTDのデッドタイムが生じる。2−5a,
5bはPチャネルMOSFETのオン.オフ時間でTL
1のオフ遅れ時間は、図4の4−5a,5bに比べて短
くなる。また2−6a,6bはNチャネルMOSFET
のオンオフ時間でTL2のオフ遅れ時間は図4の4−6
a,6bに比べ長くなる。その結果、TL1とTL2の差
が2ー8のように微少となる。
FIG. 2 is a time chart showing the signal waveform of each part of FIG. In the figure, 2-2a and 2b are output waveforms of the transistors 31a and 31b, t is a delay time of the transistor, and 2-3a and 3b are gate drive PNs.
The base signals of the P transistors 30a and 30b cause a dead time of TD, which is the same time as t. 2-5a,
5b indicates that the P-channel MOSFET is on. TL in off time
The OFF delay time of 1 is shorter than that of 4-5a and 5b in FIG. 2-6a and 6b are N-channel MOSFETs.
The off delay time of TL2 is the on-off time of 4-6 of FIG.
It is longer than a and 6b. As a result, the difference between TL1 and TL2 is as small as 2-8.

【発明の効果】以上詳述したように本発明によれば、同
時に通電する一対のPチャンネルMOSFETとNチャ
ンネルMOSFETのそれぞれのゲート端子に1個のP
NPトランジスタのエミツタ側にPチャンネルMOSF
ETを、コレクタ側にNチャンネルMOSFETを接続
して、MOSFETのオフ遅れ時間差を低減し、モータ
コイルエネルギーを有効的に利用することが可能であ
る。また、従来方法の通電方向切り換え時のデットタイ
ム回路に対して時定数回路、コンパレータ等を必要とせ
ず、回路構成も簡素化できローコストに対応出来る等の
効果を有している。
As described above in detail, according to the present invention, one P-channel MOSFET and one N-channel MOSFET, each of which is energized at the same time, has one P-channel at each gate terminal.
P channel MOSF on the emitter side of the NP transistor
By connecting an N-channel MOSFET to the collector side of ET, it is possible to reduce the difference in off delay time of the MOSFET and effectively use the motor coil energy. Further, a time constant circuit, a comparator, etc. are not required for the dead time circuit at the time of switching the energizing direction of the conventional method, and the circuit configuration can be simplified and low cost can be achieved.

【0011】[0011]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に成るモータの駆動回路の一実施例を示
す回路構成図である。
FIG. 1 is a circuit configuration diagram showing an embodiment of a motor drive circuit according to the present invention.

【図2】本発明の実施例である図1の回路の動作タイミ
ングチャートと各部の波形である。
FIG. 2 is an operation timing chart of the circuit of FIG. 1 which is an embodiment of the present invention and waveforms of respective parts.

【図3】従来技術に成るモータの駆動回路の回路構成図
である。
FIG. 3 is a circuit configuration diagram of a drive circuit of a motor according to a conventional technique.

【図4】従来技術による回路構成図の図3の動作タイミ
ングチャートと各部の波形である。
FIG. 4 is an operation timing chart of FIG. 3 and a waveform of each part of a circuit configuration diagram according to a conventional technique.

【符号の説明】[Explanation of symbols]

1 ホール素子 2 IC 3 デッドタイム回路 4a,4b トランジスタ 5a,5b PチャンネルMOSFET 6a,6b NチャンネルMOSFET 7a,7b,7c,7d ダイオード 8 コンデンサ 9 モータコイル 10 基準電圧 21a,21b トランジスタ 22a,22b 抵抗 23a,23b コンデンサ 24a,24b コンパレータ 30a,30b トランジスタ 31a,31b トランジスタ 32a,32b トランジスタ 2−2a、2b トランジスタ31a,31bの出力 2−5a、5b PチャンネルMOSFET5の出力 2−6a、6b NチャンネルMOSFET6の出力 2−8 コンデンサ8の電流波形 4−1 ホール素子1の出力電圧波形 4−2a、2b IC2の出力波形 4−3a、3b デッドタイム回路3の出力 4−5a、5b PチャンネルMOSFET5の出力 4−6a、6b NチャンネルMOSFET6の出力 4−8 コンデンサ8の電流波形 1 Hall element 2 IC 3 Dead time circuit 4a, 4b Transistor 5a, 5b P-channel MOSFET 6a, 6b N-channel MOSFET 7a, 7b, 7c, 7d Diode 8 Capacitor 9 Motor coil 10 Reference voltage 21a, 21b Transistor 22a, 22b Resistor 23a , 23b Capacitor 24a, 24b Comparator 30a, 30b Transistor 31a, 31b Transistor 32a, 32b Transistor 2-2a, 2b Output of transistor 31a, 31b 2-5a, 5b Output of P-channel MOSFET 5 2-6a, 6b Output of N-channel MOSFET 6 2-8 Current waveform of capacitor 8 4-1 Output voltage waveform of Hall element 1 4-2a, 2b Output waveform of IC2 4-3a, 3b Output of dead time circuit 3 -5a, 5b P-channel MOSFET5 output 4-6a, current waveform of the output 4-8 capacitor 8 of 6b N-channel MOSFET6

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 2個のPチャンネル電界効果形トランジ
スタ(以下MOSFETと称する)を電源側に、2個の
NチャンネルMOSFETを零電位側に配置してそれぞ
れ直列に接続してHブリッジ回路を構成し、その中間接
続点に単相ブラシレスDCモータのコイルを接続し、該
コイルにバイポーラ通電するモータの駆動回路におい
て、通電切り替え毎に動作する通電停止(以下デッドタ
イムと称する)回路を具備し、同時に通電するそれぞれ
の一対のPチャンネルMOSFETとNチャンネルMO
SFETのゲート端子を1個PNPトランジスタで駆動
し、該トランジスタのエミツタ側を前記PチャンネルM
OSFETに、コレクタ側を前記NチャンネルMOSF
ETに接続すること、を特徴とするモータの駆動回路。
1. An H-bridge circuit is constructed by arranging two P-channel field effect transistors (hereinafter referred to as MOSFETs) on the power source side and two N-channel MOSFETs on the zero potential side and connecting them in series. A coil of a single-phase brushless DC motor is connected to the intermediate connection point thereof, and a drive circuit of a motor in which the coil is bipolarly energized is provided with an energization stop (hereinafter referred to as dead time) circuit that operates every energization switching, A pair of P-channel MOSFETs and N-channel MOs that are simultaneously energized
One gate terminal of the SFET is driven by a PNP transistor, and the emitter side of the transistor is the P channel M
OSFET, the collector side is the N-channel MOSF
A motor drive circuit characterized by being connected to an ET.
【請求項2】 前記デッドタイム回路は、相補動作であ
る2つの通電方向切り替え信号を受ける2つのトランジ
スタのベース電流をオーバードライブとし、トランジス
タのオフ時間を遅らせて該2つの信号を他のトランジス
タでたすき掛け接続することで、前記ゲート駆動用トラ
ンジシタを、遅れ時間だけ強制的にオフさせることを特
徴とする請求項1に記載のモータの駆動回路。
2. The dead time circuit uses the base currents of two transistors that receive two conduction direction switching signals, which are complementary operations, as overdrive, delays the off time of the transistors, and delays the two signals by another transistor. The drive circuit for the motor according to claim 1, wherein the gate drive transistor is forcibly turned off for a delay time by connecting the gate drive crosswise.
JP8168696A 1996-06-10 1996-06-10 Motor driving circuit Pending JPH09331692A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8168696A JPH09331692A (en) 1996-06-10 1996-06-10 Motor driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8168696A JPH09331692A (en) 1996-06-10 1996-06-10 Motor driving circuit

Publications (1)

Publication Number Publication Date
JPH09331692A true JPH09331692A (en) 1997-12-22

Family

ID=15872776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8168696A Pending JPH09331692A (en) 1996-06-10 1996-06-10 Motor driving circuit

Country Status (1)

Country Link
JP (1) JPH09331692A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6995531B2 (en) 2004-03-22 2006-02-07 Matsushita Electric Industrial Co., Ltd. Direct current motor drive circuit and fan motor including the same
JP2007068391A (en) * 2005-08-29 2007-03-15 Asahi Kasei Microsystems Kk Digital noise reduction for motor
JP2009136038A (en) * 2007-11-28 2009-06-18 Sanyo Electric Co Ltd Motor drive circuit, fan motor, electronic apparatus and notebook personal computer
JP2011514134A (en) * 2008-03-03 2011-04-28 ヨンチュン ジョン Phase logic circuit for controlling the motor
JP2014110761A (en) * 2012-11-30 2014-06-12 Samsung Electro-Mechanics Co Ltd System and method for controlling speed of motor
US9099952B2 (en) 2011-12-12 2015-08-04 Hyundai Motor Company Apparatus and method for controlling switching devices for DC motor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6995531B2 (en) 2004-03-22 2006-02-07 Matsushita Electric Industrial Co., Ltd. Direct current motor drive circuit and fan motor including the same
JP2007068391A (en) * 2005-08-29 2007-03-15 Asahi Kasei Microsystems Kk Digital noise reduction for motor
JP2009136038A (en) * 2007-11-28 2009-06-18 Sanyo Electric Co Ltd Motor drive circuit, fan motor, electronic apparatus and notebook personal computer
JP2011514134A (en) * 2008-03-03 2011-04-28 ヨンチュン ジョン Phase logic circuit for controlling the motor
US9099952B2 (en) 2011-12-12 2015-08-04 Hyundai Motor Company Apparatus and method for controlling switching devices for DC motor
JP2014110761A (en) * 2012-11-30 2014-06-12 Samsung Electro-Mechanics Co Ltd System and method for controlling speed of motor
US9030139B2 (en) 2012-11-30 2015-05-12 Samsung Electro-Mechanics Co., Ltd. System and method for controlling speed of motor

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